sige and ge epitaxy: channels to a higher mobilitysige and ge epitaxy: channels to a higher mobility...

Applied Materials Confidential SILICON SYSTEMS GROUP

SiGe and Ge Epitaxy: Channels to a Higher Mobility

Saurabh Chopra Front End Products March 6, 2013

Applied Materials Confidential

SILICON SYSTEMS GROUP

Outline Introduction

– Mobility enhancement – Why SiGe/ Ge channels

High mobility channel devices for pFET applications – Additive approach – Subtractive approach – Pros and Cons of the two approaches – Stressor options for high mobility channels

Advanced pre-epi cleans for high mobility channels – Preclean options for 3D structures – Preclean options for SiGe/Ge films

Summary

2


Introduction



Strain has been used in transistors (Lg<90nm) to enhance channel mobility – With each node, the mobility

enhancement due to strain has been increasing

Mobility Enhancement

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As the industry moves from planar to 3D devices, inducing stress in channels becomes less efficient – Need higher intrinsic mobility

channel materials to further enhance performance

Source: intel, 2009



Advantages – High electron/hole mobility – Compatibility to Si LSI – Lower temperature process – Possible Vdd scaling

Why SiGe/Ge Channels?

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Si Ge

Bulk µe(cm2/Vs) 1600 3900

Bulk µΗ (cm2/Vs) 430 1900

Band gap (eV, 300K) 1.12 0.66

Dielectric constant 11.9 16

Strain techniques similar to Si channels can also be applied to SiGe/Ge channels, to further enhance hole mobility – Makes this technology more

scalable


High Mobility Channel Devices for pFETs



High Mobility Channel Formation

High mobility channels will likely be implemented in 3D structures

Possible options are – SiGe or Ge channels for pFET – III-V channels for nFET

Uniaxially strained Ge pFETs are believed to offer better intrinsic mobilities compared to strained Si or relaxed Ge – Can potentially offer better

performance

Ge FINFET demonstrated @ IEDM 2012 by Van Dal et. al. (TSMC)

Ge FINFET performance modeled @ IEDM 2012 by Eneman et. al. (IMEC)



High Mobility Channel Materials for pFET SiGe and Ge Channels

Additive Approach Replacement Channel

Subtractive Approach Blanket Epi

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STI FormationRecess Si

Grow SiGe/Ge

Recess STISiGe/Ge CMP

Si TrenchSiGe/ Ge EpiSiGe/Ge CMP

Recess STISTI process

Two approaches are being considered for high mobility channels in 3D transistor structures

SiGe/ Ge FIN

Silicon substrate

STI Oxide

Si substrate/ SiGe Strain relaxed buffer

SiGe

/ Ge

FIN

STI O

xide



Ge Fin Formation Demonstration Additive Approach

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Ge FIN

Silicon substrate

STI Oxide

Ge FIN

Silicon substrate

STI Oxide

Threading dislocations

Ge FIN demonstration using the additive approach – Ge FIN fabricated by targeting epi growth rate

to stay close to STI surface – Eventually Ge CMP needed

XTEM Ge

Si Oxide



Ge Fin Formation Additive Approach Challenges

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Silicon substrate


Ge FIN

STI Oxide

1

Defect control – Aspect ratio trapping works in

FIN width direction

– Not so well in channel direction

FIN length restrictions will help trapping in channel direction

Trench widening during pre-epi clean

– Native oxide removal leads to CD blowout

Preclean process optimization will be helpful

Ge FIN

Silicon substrate

STI Oxide


2



SiGe/Ge Fin Formation Subtractive Approach

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Strain Relaxed Buffer (SRB)

Relaxed Defect Free SiGe/ Ge

Si substrate

SiGe

/ Ge

FIN

STI O

xideSiGe Strain relaxed buffer

Si substrate

SiGe/ Ge FIN

SiGe

/ Ge

FIN

SRB

Ge FIN formation using the subtractive approach – Strain relaxed buffer

layers with defect free Ge channel demonstrated

– Aspect ratio trapping not needed for defect free Ge epi

– STI process has to be compatible with SiGe and Ge films



Comparison of Additive vs. Subtractive Approach

Additive approach – Advantages

• Standard STI process • Thin epi layers needed for

defect free channels – Disadvantages

• Defect control in the channel direction

• FIN widening during pre-epi clean

• SiGe/Ge chemical mechanical polishing

Subtractive approach – Advantages

• Defect free channels in both directions (FIN width & channel)

• Ability to form strained Ge channels with strain relaxed buffer (SRB) layer

– Disadvantages • Thick epi films needed for

SRB layer • STI process compatibility

with SiGe/Ge needed • SiGe/Ge chemical

mechanical polishing

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Methods of Inducing Strain in SiGe/Ge Channel

Two options are being considered – Strain relaxed buffer layers

• Can be used to induce biaxial compressive strain in Ge channel – GeSn stressors

• GeSn and GeSnB can be used to induce uniaxial compressive strain in the Ge channel

• Sn incorporation and thermal budgets likely to be the main challenges

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Ge FINFET performance

modeled @ IEDM 2012 by Eneman et.

al. (IMEC)

Strained Ge is needed for better performance compared to strained Si channel FETs – Relaxed Ge channel pFET might

not offer an improvement over strained Si channels

These approaches have been shown to be additive and can be used individually or together for best performance


Advanced Preclean Techniques for High Mobility Channels



Advanced Preclean for High Mobility Channels

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Goals – As little SiO2 etching as

possible to avoid CD blowout – Effective clean at bottom of

trench with minimum SiO2 loss – Clean on all sides of the FIN

for stressor preclean

Goals – Cleaning native oxides on

SiGe/Ge films for epi deposition

– Clean on all sides of the FIN for stressor preclean

Pre-epi Cleaning of SiGe and Ge Films

Pre-epi Cleaning in 3D Structures

Silicon substrate

STI Oxide

CD

SiGe/ Ge FIN

Silicon substrate

STI Oxide

S/D recess

Si substrate

SiGe

/ Ge

FIN

STI O

xide

SRB



Pre-epi Cleaning in 3D Structures

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Pre-clean effectiveness – Siconi preclean was

used to perform pre-epi clean on FIN structure wafers

– Good quality defect free SiGe epitaxial growth was observed with no pre-bake

– Siconi is effective in cleaning all sides of the FIN structures

Si

SiGe

Siconi pre-epi clean



SiGe Film Clean Solution Pretreatment + Siconi Clean

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Interface

Pretreatment + Siconi can clean SiGe surface (SRB) for high channel mobility epi deposition

Pre-clean with no treatment Pre-clean with treatment

0

0.05

0.1

0.15

0.2

0.25

1E+14

1E+15

1E+16

1E+17

1E+18

1E+19

1E+20

1E+21

0 500 1000 1500 2000

SiG

e C

ompo

sitio

n (M

ole

Frac

tion

XGe)

Con

cent

ratio

n (A

tom

s/cm

3)

Depth (Å)

xGe->

C O

F

Cl

Interface

xTEM image showing good quality SiGe epi grown on

SiGe surface



Summary Higher mobility channels are expected to be the next change in

transistor evolution SiGe/Ge channels for pFETs are the most likely candidates

– Higher intrinsic mobility – Ability to apply stress techniques for extracting higher performance

Two possible approaches for SiGe/Ge channels – Both have its challenges and benefits – A choice between the two would likely depend on both the technical and

commercial aspects Integrated pre-clean is another important aspect of a successful

transition to higher channel mobility devices – Demonstrated Siconi solution for 3D structures – Demonstrated preclean solutions for SiGe/Ge films

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