sicmosfet progress at uscineil/sic_workshop/presentations_2017/0… · 100x pulse short circuit...
TRANSCRIPT
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SiC MOSFET progress at USCi
L. Fursin, X. Li, W. Simon, X. Huang, Z. Li, M. O’Grady, A. Bhalla, J. C. Dries
August 17, 2017
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 1
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Contents
� USCi product development at X-Fab
� 1200V MOSFET progress
� 3300V MOSFET built upon 1200V platform
� Summary and future work
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 2
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USCi product development at X-Fab
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 3
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USCi product development at X-Fab
Accomplishments and Outcomes - MOSFETApplications v. Current
Impact
� 650-1200V Diodes, 650-1200V JFETs, 1200V-3300V MOSFETs demonstrated and being qualified at X-Fab
� SiC devices with 6” Pure-Play Foundry Model
� 6” platform can allow 2-4X ASP reduction with volume
� Maturing 6” thick epi technology enables large die size, scaling the current to be competitive with Si
� Large area 1200V and 3300V MOSFETs target power supply, EV, industrial and traction applications
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 4
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1200V MOSFET progress
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 5
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USCi 1200V planar MOSFETs at X-fab:reliability study
Accomplishments and Outcomes - MOSFET� Established 1200V MOSFET platform at X-Fab
� Engineering TO-247 1200V MOSFET samples have passed JEDEC reliability tests
� 1200V MOSFET Qualification in Q4 2017
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 6
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USCi 1200V MOSFETs at X-fab:moisture-resistance H3TRB test
Accomplishments and Outcomes - MOSFET
1200V-40mOhm MOSFETs from 1st Engineering lot pass H3TRB burn-in
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 7
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Final 1200V-40mOhm engineering MOSFET lot:
static characteristics
Vth was on target in Final Engineering lot, and decreases with temperature as expected;
Rdson increases with temperature as expected due to positive temperature coefficient of drift layer, JFET channel and substrate resistances;Vbr steadily increases with temperature indicating avalanche nature of the breakdown
3rd quadrant body diode has low Vfdecreasing with temperature
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 8
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Final 1200V-40mOhm engineering MOSFET lot: avalanche capability
Accomplishments and Outcomes - MOSFET
1200V-40mOhm MOSFETs from Final Engineering lot pass UIS test (Eav=1.48J) without device degradation
Positive ~ 200mV Vth shift is observed with minor increase in RdsA
Id=16A
Vds=1.8kVVgs=18V
Vgs=-5V
12/7/2017 9The 5th Workshop on Wide Bandgap Power Devices and Applications
(WiPDA 2017)
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Vth shift after repetitive UIS tests , L=15mH
12/7/2017 10
100,000 repetitive UIS (avalanche) events do not induce degradation of MOSFET characteristics up to 4A peak current, except for positive Vth shift and minor increase in RdsA
Positive Vth shift increases with UIS peak current and number of UIS pulses
1200V MOSFET is robust against 1,000,000 low current (0.6A) UIS events
The 5th Workshop on Wide Bandgap Power Devices and Applications
(WiPDA 2017)
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Final 1200V-40mOhm engineering MOSFET lot:
1x pulse short circuit test
8μs: pass w/o degradation of Idsx, Igss, but with positive Vth shift
Vds
Id
Vgs
10μs: pass w/o degradation of Idsx, Igss,
but with positive Vth shift
Vds
Id
Vgs
1200V-40mOhm MOSFETs from Final Engineering lot can pass room temperature 10μs short circuit test (Vds=600V, Vgs=+20/-5V, Rg=47 Ohm) without device degradation;
Positive Vth shift is observed;
Statistics yet to be improved;
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 11
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Final 1200V-40mOhm engineering MOSFET lot:
100x pulse short circuit test Device N119: SC pulse #1
2 SC pulses
Device N119: SC pulse #2 Catastrophic fail
Device N120: SC pulse #1
100 SC pulses
Device N120: SC pulse #100
Vds
Id
Vgs
Vds
Id
Vgs
VdsId
Vgs
Vds
Id
Vgs
MOSFETs from Final Engineering lot can pass room temperature 100-pulse 10us short circuit test (Vds=600V, Vgs=+20/-5V, Rg=47 Ohm) without device degradation.
Positive Vth shift and reduction in Idsat is observed in all MOSFETs.
Some devices fail catastrophically. Fail mechanism to be investigated. Statistics yet to be improved;
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 12
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Effect of 1x and 100x short circuit pulses
(Vds=600V, Rg=47 Ohm, RT) on device characteristics
Positive Vth shift increases with short circuit pulse width – more electrons get trapped in combination with permanent gate oxide degradation?Higher Vgs results in more significant Vth shift after 1-pulse SC as Idsat increases; Vth shift does not accumulate with 100 SC pulses but saturates after 1-2 pulses (most of electron traps get populated?). For 100-pulse repetitive short circuit tests Vth shift is nearly linearly dependent upon short circuit pulse width for both Vgs=+18V and Vgs=+20V;There is practically no change in threshold voltage after 100-pulse 4μs short circuit test under Vgs=+18V, so lower operating MOSFET gate bias is clearly beneficial (trade-off with RdsA)Vth shift can be partially recovered with 150C bake for 20 hrs - trapped electrons get released?Statistics yet to be improved;
12/7/2017 13The 5th Workshop on Wide Bandgap Power Devices and Applications
(WiPDA 2017)
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3300V MOSFET built upon 1200V platform
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 14
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3300V MOSFET optimized design at X-Fab
Optimized epi and edge termination;
Optimized width of JFET region and
deep CS layer below Pbase regions;
Optimized retrograde Pbase doping profile;
Recessed Pbase contact regions;
Standard backside laser-annealed ohmic contact;
Optimization of JFET region width and
doping;
Trade-offs: Vth, Rdson, Eox.max. and Cgd;
Desired designs
Eox. max. @ Vds=3300V, MV/cm
2 2.5 3.0 3.3 4.0 R
dsA
, m
Ω·c
m2
Increasing JFET/CS
N-type implant dose
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 15
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3300V MOSFET static IV characteristics and yield:
X-fab
3mm x 3mm 3300V MOSFET blocking yield (97%
at Id=100 μA) in normally-off mode: 6-inch fab
(Showa Denko epi)
Typical RT RdsA=10 mΩ·cm2 at Id=5A, Vgs=20V
and RdsA=11 mΩ·cm2 at Id=5A, Vgs=15V;
Typical Vbr ~ 4kV in normally-off mode; 8mm x 8mm 50A 3300V schottky diode
blocking yield (72% at Id=1 mA) : 4-inch fabUMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 16
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3300V MOSFET performance
Vth is lower than the target due to single incorrectly implanted dose. Vth decreases with temperature as expected;
Rdson is dominated by series resistance of the drift layer – at higher operating junction temperatures the effect of higher Vgs (20V vs 15V) becomes negligible
Gate oxide rupture voltage (positive Vgs) is uniform across the wafer and translates into ~11-11.5MV/cm rupture electric field. Results are similar for negative Vgs
Body diode has low Vf in 3rd quadrant decreasing with temperature
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 17
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3300V MOSFET design matrix
Main design:
full MOS & JFET
channel
densities
50% MOS &
100% JFET
channel densities
50% MOS &
50% JFET
channel densities
25% MOS &
100% JFET
channel densities
A B C D
RT RdsA, mΩ·cm2
(Vgs=+15V)11.2 14.8 16.9 19.2
RT RdsA, mΩ·cm2
(Vgs=+20V)10.0 11.9 14.0 13.9
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 18
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3300V MOSFETs: 5 μs short-circuit test at Vgs=15V, Vds=1500V
All 3300V MOSFET designs pass 5 μs short-circuit test at Vgs=15V and Vds=1500V;
Saturation current is lowered by reducing densities of MOS and JFET channels;
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Type A (100% MOS/100% JFET)
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Vgs=15V
Vds=1500V
Id
Vgs=-5V
Type B (50% MOS/100% JFET) Type C (50% MOS/50% JFET)
Type D (25% MOS/100% JFET) Type E (-0.1 μm JFET width vs. Type A) Type F (+0.1 μm JFET width vs. Type A)
100A
68A 70A
51A94A
105A
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 19
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3300V MOSFETs: 5 μs short-circuit test at Vgs=20V, Vds=1500V
3300V MOSFET designs pass 5 μs short-circuit test at Vgs=20V and Vds=1500V, except for
design “F” with +0.1 μm wider JFET channel;
Saturation current increased by ~50% compared to Vgs=15V;
Main design “A” can handle 15.6 J/cm2 SC energy density;
Vgs=20V
Vds=1500V
IdVgs=-5V
150A
Vgs=20V
Vds=1500V
Id
Vgs=-5V
100A
Vgs=20V
Vds=1500V
Id
Vgs=-5V
78A
Vgs=20V
Vds=1500V
Id
Vgs=-5V
132A
Vgs=20V
Vds=1500V
Id
Vgs=-5V
154A
Esc=0.78J Esc=0.56J
Esc=0.46J FAIL!
Type A (100% MOS/100% JFET) Type B (50% MOS/100% JFET) Type C (50% MOS/50% JFET)
Type D (25% MOS/100% JFET) Type E (-0.1 μm JFET width vs. Type A) Type F (+0.1 μm JFET width vs. Type A)
Esc=0.72J
no data
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 20
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3300V MOSFETs: 5 μs short-circuit test at Vgs=15V, Vds=2200V
3300V MOSFET designs “B”, “C”, “D” with reduced saturation current pass 5 μs short-circuit test at Vgs=15V and Vds=2200V; 3300V MOSFET design “E” fail catastrophically. Main design A and its derivative F are also expected to fail, although experimental data has not been collected yet;Idsat vs short-circuit robustness trade-off;
Esc=0.78J Esc=0.56J
FAIL!
Type A (100% MOS/100% JFET) Type B (50% MOS/100% JFET) Type C (50% MOS/50% JFET)
Type D (25% MOS/100% JFET) Type E (-0.1 μm JFET width vs. Type A) Type F (+0.1 μm JFET width vs. Type A)
Id
Vds=2200VVgs=15V
Vgs=-5V
Id
Vds=2200VVgs=15
Vgs=-5V
Id
Vds=2200VVgs=15V
Vgs=-5V
NO DATA!
FAIL!
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 21
NO DATA!
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3300V MOSFETs: 7.5 μs short-circuit test at Vgs=15V, Vds=1500V
3300V MOSFET designs “B”, “C”, “D” with reduced saturation current pass 7.5 μs short-
circuit test at Vgs=15V and Vds=1500V, although with 200-400 mV positive Vth shift;
3300V MOSFET main design “A”, designs “E” and “F” all fail catastrophically;
Idsat vs short-circuit robustness trade-off;
Vgs=
15V
Vds=1500V
Id
Vgs=-5V
Id
Id Id
Esc=0.78J Esc=0.56J
Esc=0.46J FAIL!
Type A (100% MOS/100% JFET) Type B (50% MOS/100% JFET) Type C (50% MOS/50% JFET)
Type D (25% MOS/100% JFET) Type E (-0.1 μm JFET width vs. Type A) Type F (+0.1 μm JFET width vs. Type A)
Esc=0.72J
Id Id
Id Id Id
Vds=1500V Vds=1500V
Vds=1500V Vds=1500V Vds=1500V
Vgs=
15V
Vgs=-5V
Vgs=
15V
Vgs=-5V
Vgs=
15V
Vgs=-5V
Vgs=
15V
Vgs=-5V
Vgs=
15V
Vgs=-5V
FAIL!FAIL!
FAIL!
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 22
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3300V MOSFETs: 5 μs short-circuit test at Vgs=15V, Vds=2200V
3300V MOSFET designs “B”, “C”, “D” with reduced saturation current pass 5 μs short-circuit test at Vgs=15V and Vds=2200V; 3300V MOSFET design “E” fail catastrophically. Main design A and its derivative F are also expected to fail, although experimental data has not been collected yet;Idsat vs short-circuit robustness trade-off;
Esc=0.78J Esc=0.56J
FAIL!
Type A (100% MOS/100% JFET) Type B (50% MOS/100% JFET) Type C (50% MOS/50% JFET)
Type D (25% MOS/100% JFET) Type E (-0.1 μm JFET width vs. Type A) Type F (+0.1 μm JFET width vs. Type A)
Id
Vds=2200VVgs=15V
Vgs=-5V
Id
Vds=2200VVgs=15
Vgs=-5V
Id
Vds=2200VVgs=15V
Vgs=-5V
NO DATA!
FAIL!
12/7/2017 23
NO DATA!
The 5th Workshop on Wide Bandgap Power Devices and Applications
(WiPDA 2017)
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RdsA and Idsat trade-off
Trade-off between RdsA and
Idsat, and therefore between
RdsA and short-circuit
robustness;
Operating gate bias Vgs=15V is
desirable;
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 24
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3300V MOSFETs: 10 μs short-circuit test at Vgs=15V, Vds=1500V
Parts undergo catastrophic failure under 10μs short-circuit test at both Vgs=15V and Vgs=20V;
Failure mechanisms to be further studied;
Some tail leakage current cannot be turned off? Gate oxide degradation under gate oxide
leakage current at extreme temperatures with subsequent loss of gate control? Source overlay
melting?
JFET region doping and width to be further optimized, increasing Vth and sacrificing low RdsA;
Type A (100% MOS/100% JFET) Type B (50% MOS/100% JFET)
Type C (50% MOS/50% JFET) Type D (25% MOS/100% JFET)
FAIL!FAIL!
FAIL!FAIL!
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 25
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3300V MOSFETs: body-diode stressing with repeated 200μs surge current pulses
3300V MOSFETs body diode is robust against 3rd quadrant surge current
stressing: device degrades if exposed to 1000A/cm2, but not at 500A/cm2.
1200V MOSFETs do not degrade at 1000A/cm2 surge current density;
No change in MOSFET gate leakage current or Vth;
Severe degradation of unipolar (on-state, off-state) and bipolar (3rd
quadrant body diode) forward characteristics;
All suggests minor or no change at MOS interface but severe bulk material
degradation affecting both leakage, conductivity modulation and bulk
mobility – signature of SF growth;
SFs expanding from the BPD-conversion buffer? Process-induced SFs?
MOSFET degradation after stressing with surge
current pulses at 1000A/cm2 current density
12/7/2017 26
Vgs=-5V
The 5th Workshop on Wide Bandgap Power Devices and Applications
(WiPDA 2017)
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Summary
� Demonstrated 1200V and 3300V MOSFETs at X-fab concurrently with 650V-1200V JBS diodes and normally-on JFETs;
� 1200V MOSFET engineering samples pass JEDEC reliability tests;
� 1200V MOSFETs demonstrate avalanche and short-circuit robustness, including 1,000,000-pulse repetitive UIS and 100-pulse repetitive short circuit events;
� Demonstrated high MOSFET blocking yield on 3300V epi as material quality improves;
� Performance and reliability of 3300V MOSFET is affected by low Vth (accidental excessive implant dose), but the results are encouraging;
� Short-circuit robust 3300V MOSFET design has RdsA of 14.8mΩ·cm2 at Vgs=15V and can pass 7.5 μs short-circuit test at Vgs=15V and Vds=1500V and 5.0 μs short-circuit test at Vgs=15V and Vds=2200V;
� RdsA of 3300V MOSFETs will have to be further sacrificed for short circuit robustness;
� 3300V MOSFET is robust against body diode surge current stressing - degradation occurs only under very high current density and may be related to process-induced SF growth or expansion from BPD-conversion buffer. This degradation is not observed in 1200V MOSFETs for the same surge current density;
� To address BPD/SF problem, 3300V JBSFET is now doable with JBS and MOSFET diode platforms established and thick epi technology rapidly progressing on 6-inch substrates
� Continue evaluating various aspects of 1200V and 3300V MOSFET performance and reliability;
THANK YOU!
UMD/ARL: 12th annual SiC MOS workshop,
UMD College Park, August 17-18, 201712/7/2017 27