sia road map and design&test - carnegie mellon …users.ece.cmu.edu/~maly/maly/sia97.pdf · vv...

1Copyright © W. Maly

SIA Road Map SIA Road Map andand

DESIGN&TESTDESIGN&TEST

Wojciech MalyWojciech Maly

Department of Electrical and Computer Engineering Department of Electrical and Computer Engineering

Carnegie Mellon UniversityCarnegie Mellon UniversityPittsburgh, Pa. 15213.Pittsburgh, Pa. 15213.


ObjectiveObjective

D&T Current and Future ProblemsD&T Current and Future Problems

Future of IC Technology

SIA Road Map

To discuss fundamental research in Design and Test (D&T) of VLSI ICs


OutlineOutline

3. D&T Current and Future 3. D&T Current and Future ProblemsProblems

2. Future of IC Technology

1. SIA Road Map

New and very efficient design strategies capable of producing

very high QUALITY IC DESIGNS will eventually

became the key enablers of the SIA Road Map vision.

4. Proposal of an approach to fundamental research

problems in D&T.

Cost of silicon will have to consume a rapidly increasing portion of the available profit

margins


SIA Road MapSIA Road Map

1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 20100.05

0.1

1

5Minimum Feature Size [µm]

0.2

0.4

0.8

256k DRAM(1.6 µm) 4M DRAM

(0.8 µm) 16M DRAM(0.5 µm) 64M DRAM

(0.35 µm)

Prediction

HH

HH

Year


1994 SIA Road Map Assumptions1994 SIA Road Map Assumptions

64

0.017

190

34

256

0.007

280

91

1024

0.003

420

244

4096

0.001

640

640

16384

0.0005

960

1707

65536

0.0002

1400

4681

0.35

200

0.25

200

0.18

300

0.12

300

0.1

400

0.08

400

Feature size [µm]

Cost per tr. [millicents]

Wafer diameter [mm]

1995 1998 2001 2004 2007 2010Year

Tr. per chip [10 ] 6

Chip size [mm ] 2

Tr. density [10 # tr. / cm ]26

10

1

250

4

21

0.5

300

7

46.8

0.2

360

13

107.5

0.1

430

25

260

0.05

520

50

558

0.02

620

90



Chip size [mm ] 2


M E M O R Y

µ P R O C S S O R


SIA Road MapSIA Road Map

vv SIA Road Map is a collective view on the future of SIA Road Map is a collective view on the future of thethemicroelectronics industry; microelectronics industry;

vv The objective of the SIA Road Map was a consolidation of the The objective of the SIA Road Map was a consolidation of the vision for the entire semiconductor industry;vision for the entire semiconductor industry;

vv Such a consolidation was a necessary step in focusing industry, Such a consolidation was a necessary step in focusing industry, governments and universities on the same technology governments and universities on the same technology development objectives; development objectives;

vv The SIA Road Map has a strong “technology/ manufacturing/The SIA Road Map has a strong “technology/ manufacturing/equipment” orientation; equipment” orientation;

vv The SIA Road Map is a “linear extrapolation” of the trends The SIA Road Map is a “linear extrapolation” of the trends known from the past;known from the past;

vv The SIA Road Map is a “self-fulfilling prophecy” which The SIA Road Map is a “self-fulfilling prophecy” which facilitates continuation of the evolution of the semiconductor facilitates continuation of the evolution of the semiconductor industry along Moore’s Law;industry along Moore’s Law;


SIA Road Map: ImplicationsSIA Road Map: Implications

( Cost per tr.) X

( Yield) X (Number of chips per wafer) =

= Number of chips per wafer

Number of good chips

Cost per chip

( Cost per wafer )

Tr. per chip

( Wafer area )

( Chip size ) X( Tr. density) =

( Tr. per chip) =

( Number of good chips ) X(Cost per chip) = Cost per wafer

( Chip size )

(( Number of masks ) X (Wafer area ))= Cost per mask per sq.


SIA Road Map : MEMORYSIA Road Map : MEMORY

64

0.017

190

34

90

142

314

127

10.88

1382

18

0.24

256

0.007

280

91

90

93

314

83

17.92

1487

20

0.24

1024

0.003

420

244

90

148

706.5

133

30.72

4086

20

0.29

4096

0.001

640

640

90

91

706.5

81

40.96

3318

22

0.21

16384

0.0005

960

1707

90

110

1256

99

81.92

8110

22

0.29

65536

0.0002

1400

4681

90

72

1256

64

131.07

8389

24

0.28

0.35

200

0.25

200

0.18

300

0.12

300

0.1

400

0.08

400

Feature size [µm]


Wafer diameter [mm]

Yield [%]

Number of chips per wafer


Cost per chip [$]

Cost per wafer [$]

Number of masks

1995 1998 2001 2004 2007 2010Year

Cost per mask per sq.[$/cm ]2


Wafer area [cm ]2

Chip size [mm ]2


Slide only for the discussion


SIA Road Map : SIA Road Map : µµPROCESSORPROCESSOR

10

1

250

4

104

93

100

9300

1.65

21

0.5

300

7

89

80

105

8400

22

1.22

46.8

0.2

360

13

168

151

14134

22

0.91

107.5

0.1

430

25

140

126

107.5

13545

24

0.80

260

0.05

520

50

211

189

130

24570

24

0.82

558

0.02

620

90

177

159

111.6

17744

26

0.54

90

314

18

90

314

90

706.5

90

706.5

90

1256

90

1256

93.6

0.35

200

0.25

200

0.18

300

0.12

300 400 400

1995 1998 2001 2004 2007 2010

Feature size [µm]


Wafer diameter [mm]

Yield [%]

Number of chips per wafer


Cost per chip [$]

Cost per wafer [$]

Number of masks

Year

Cost per mask per sq.[$/cm ]2


Wafer area [cm ]2

Chip size [mm ]2


0.1 0.08



SIA Road Map Assumptions -SIA Road Map Assumptions -Chip SizeChip Size

BB

B

B

B

B

JJ

JJ

JJ

B

J µ


SIA Road Map Assumptions - SIA Road Map Assumptions - Transistor DensityTransistor Density

B

B

B

B

B

B

JJ

J

J

JJ

B

J µ


SIA Road Map Consequences - SIA Road Map Consequences - Number of TransistorsNumber of Transistors

B

B

B

B

B

B

JJ

J

J

JJ

B

J µ


SIA Road Map Assumptions - SIA Road Map Assumptions - CostCost

B

B

B

B

B

B

J

J

J

J

J

J

B

J µ


SIA Road Map Consequences - SIA Road Map Consequences - Chip CostChip Cost

BB

B

B

B

B

J J

J

J

J

J

B

J µ


SIA Road Map Consequences - SIA Road Map Consequences - Manufacturing Costs Manufacturing Costs

B B BB

B B

J

J

JJ J

J

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

00.20.40.60.8

11.21.41.61.8

Cost of Manufacturing per Layer [$/cm ]

Year

B Cost per layer per cm - Memory

J Cost per layer per cm - µProc.

2

22



1994 SIA Road Map assumes that: 1994 SIA Road Map assumes that:

–– exponential growth in die size,exponential growth in die size,

–– exponential growth in transistor density and exponential growth in transistor density and

–– exponential decrease in cost per transistor, exponential decrease in cost per transistor,

can be handled with unchanged (or even can be handled with unchanged (or even decreased) manufacturing cost per unit square.decreased) manufacturing cost per unit square.

Is such a goal really feasible ?Is such a goal really feasible ?


Implications of SIA Road Map: Implications of SIA Road Map: InterconnectInterconnect

Year Min.FeatureSize[µm]

1995 0.40 35 380

1998 0.30 50 840

2001 0.22 70

2004 0.15 105

2007 0.11 125

2010 0.08 155

Interconnect Density

cm 2[m/ /level]

2100

4100

6300

10,000

Interconnect Length

[m]


Implications of SIA Road Map: Implications of SIA Road Map: InterconnectInterconnect

Metal 2Metal 2

Metal 1Metal 1

WW

WW

WW

AlAl

RRcc

RR ww

RRcc

RRcc

RRcc

x 100 000 000x 100 000 000

CC


Implications of SIA Road Map: Implications of SIA Road Map:

InterconnectInterconnect

Interconnect may become a main show Interconnect may become a main show stopper of the SIA Road Map.stopper of the SIA Road Map.

Complexity of the interconnect will strongly affectComplexity of the interconnect will strongly affectthe methodology of DESIGN, the methodology of DESIGN,

MANUFACTURING and TEST.MANUFACTURING and TEST.


R = 15 cmR = 15 cm

Silicon WaferSilicon Wafer

D = 100 D = 100 µµ mm

Cross-section Cross-section of a human hairof a human hair

Edge of the Edge of the die die (3x3 cm)(3x3 cm)

1 cm1 cm



D = 100 D = 100 µµ mmHuman hairHuman hair

D = 0.25 D = 0.25 µµ mm

ContaminationContaminationSlide only for the discussion


Implications of SIA Road Map: Implications of SIA Road Map: ManufacturingManufacturing

BB

BBBB

BB

BB

BB

445566778899

10101111121213131414

0.050.05 0.10.1 0.150.15 0.20.2 0.250.25 0.30.3 0.350.35

Die Area [cm Die Area [cm 22]]

Feature Size [Feature Size [µµm]m]

For Y = 70% D0 = .43

Ach

For Y = 90% D0 = .11

Ach

DD00 = = 1 - Y 1 - YYYAAchch

Y = Y = 11 1 + 1 + AAchch DD00



BB

BB

BB

BB

BB

BB

JJJJ

JJJJJJJJ4499

141419192424292934343939

0.050.05 0.10.1 0.150.15 0.20.2 0.250.25 0.30.3 0.350.35

Acceptable number of defects per waferAcceptable number of defects per wafer

Feature Size [Feature Size [µµm]m]

BB Y=70%Y=70% JJ Y=90%Y=90%

No more thanNo more than10 defects in 10 defects in

400 + 400 + manufacturing manufacturing

steps !steps !



Cost of manufacturing may become a main Cost of manufacturing may become a main show stopper on the SIA Road Map.show stopper on the SIA Road Map.

Complexity of IC processes must cause rapid Complexity of IC processes must cause rapid increase in cost of IC manufacturing.increase in cost of IC manufacturing.


SIA Road Map Consequences - SIA Road Map Consequences - Transistors per Test PointTransistors per Test Point

B B B BB

B

JJ

J

J

J

J

B

J


Implications of SIA Road Map:Implications of SIA Road Map: Testing Testing

Metal 2Metal 2

Metal 1Metal 1

WW

WW

WW

AlAl

RR cc

RRww

RRcc

RRdd

RR dd

CC



vv Testing will have to handle very large devices/ Testing will have to handle very large devices/systems;systems;

vv New difficult-to-detect failures will have to be tested. New difficult-to-detect failures will have to be tested.–– Data dependent cross-talk failures;Data dependent cross-talk failures;

–– Power bus noise generated faults;Power bus noise generated faults;

–– R-F coupling generated faults.R-F coupling generated faults.

vv Very high band-width testers will be required; Very high band-width testers will be required;

vv Massive application of DFT will be a must.Massive application of DFT will be a must.



Tester limitations may become a main show Tester limitations may become a main show stopper on the SIA Road Map.stopper on the SIA Road Map.

Complexity of ICs to be tested will soon reach levels Complexity of ICs to be tested will soon reach levels impossible to be handled with the testing paradigm as it is impossible to be handled with the testing paradigm as it is

known today.known today.


Implications of SIA Road Map:Implications of SIA Road Map: Design Design

SEMATECH

O OO

O

O

O

G G GG

G

G

1995 1998 2001 2004 2007 2010

100

200

300

400

500

600

Num

ber

of T

rans

isto

rs p

er C

hip[

10

]

Year

O Tr. per Chip

G Tr. per Year per Designer

Design Productivity [T

ransistors per

Year per D

esigner * 10 ]

0.1

0.2

0.3

0.4

0.5

0.6

66



vv Design productivity will have to increase by Design productivity will have to increase by orders of magnitude;orders of magnitude;

vv Design verification (on all levels of design Design verification (on all levels of design abstraction) will become an absolute necessity;abstraction) will become an absolute necessity;



Design productivity and design verification Design productivity and design verification may become key show stoppers on the SIA may become key show stoppers on the SIA

Road Map.Road Map.

Size of ICs to be designed will soon reach levels Size of ICs to be designed will soon reach levels impossible to be handled with the design paradigm as it is impossible to be handled with the design paradigm as it is

known today.known today.



1994 SIA Road Map assumes that 1994 SIA Road Map assumes that

the substantial increase in complexity of : the substantial increase in complexity of :

–– manufacturing,manufacturing,

–– test and test and

–– design, design,

can be handled with unchanged (or even decreased) can be handled with unchanged (or even decreased) manufacturing cost per unit square.manufacturing cost per unit square.




1994 SIA Road Map assumes that 1994 SIA Road Map assumes that

the substantial increase in complexity of : the substantial increase in complexity of :

–– manufacturing,manufacturing,

–– test and test and

–– design, design,

can be handled with unchanged (or even decreased) can be handled with unchanged (or even decreased) manufacturing cost per unit square.manufacturing cost per unit square.


1997 Road Map says NO !1997 Road Map says NO !

Cost of silicon will have to consume a rapidly increasing portion of the available profit margins.



[$/ chip]

Profit margin

D&T

Package

Silicon

1997 2003 2006

100

500

1000

vv It is likely that the It is likely that the cost of silicon will cost of silicon will grow more than the grow more than the SIA Road Map SIA Road Map allows.allows.

Cost and profit



Profit margin

D&T

Package

Silicon

C = C +D&T TE

C + CD TG

V Ch

C = C +Silicon Material Own. V Ch

C

TEC

TDC+

vv Cost of D&T can be Cost of D&T can be substantially reduced by increasing substantially reduced by increasing volume of sold chips.volume of sold chips.

vv Cost of silicon cannot be reduced Cost of silicon cannot be reduced beyond a certain level by increasing beyond a certain level by increasing volume of sold chips.volume of sold chips.



[$/ chip]

Profit margin

D&T

Package

Silicon

1997 2003 2006

100

500

1000

vv It is possible that the It is possible that the only market only market advantage for many advantage for many IC producers will be IC producers will be achievable via high achievable via high efficiency and high efficiency and high quality design and quality design and test;test;

Cost and profit


Design QualityDesign Quality

Intel P6 ( Kalmath)Intel P6 ( Kalmath)

CISC (32 bit data/instr.)CISC (32 bit data/instr.)

Universal (MPEG2, ...)Universal (MPEG2, ...)

100 %100 %

0.28 0.28 µµm CMOSm CMOS

233 MHz;233 MHz;

7.5 M (with 32K L1 cache)7.5 M (with 32K L1 cache)

203 mm203 mm

TBA TBA

(PPro - 200 MHz = $1072)(PPro - 200 MHz = $1072)

Type: Type:

Applications:Applications:

Load for DVD:Load for DVD:

Technology:Technology:

Clock:Clock:

# Trans. Total:# Trans. Total:

Area:Area:

Price:Price:

Mitsubishi D30VMitsubishi D30V

DSP LIW (64 bit instr.)DSP LIW (64 bit instr.)

M-Media (MPEG2, V-ph.)M-Media (MPEG2, V-ph.)

90 %90 %

0.3 0.3 µµm CMOSm CMOS

250 MHz;250 MHz;

300 K + 64K SRAM 300 K + 64K SRAM

37 mm37 mm

TBA TBA

(Est. < $50)(Est. < $50)

Compiled by Pierre Paulin of ST based on the data published in EE Times and µP Rep.

22 22


SIA Road Map ImplicationsSIA Road Map Implications

SIA Road Map will cause: SIA Road Map will cause:

–– Cost of silicon to go up;Cost of silicon to go up;

–– Price of chips to go up (but with well defined upper limit); Price of chips to go up (but with well defined upper limit);

–– Progress along Moore’s curve to slow down; Progress along Moore’s curve to slow down;

–– Design and test budgets to go down; Design and test budgets to go down;

–– Design efficiency and design quality to become the most important Design efficiency and design quality to become the most important

knobs in profit maximization. knobs in profit maximization.

New and very efficient design strategies capable of producing very high QUALITY IC

DESIGNS will eventually became the key enablers of the SIA Road Map vision.


OutlineOutline

3. D&T Current and Future Problems

2. Future of IC Technology

1. SIA Road Map

4. Proposal of an approach to fundamental research

problems in D&T.


Fundamental Problems: TESTFundamental Problems: TEST

FUNDAMENTAL TEST PROBLEMS

INSUFFICIENT TESTING BANDWIDTH INADEQUATE TEST QUALITY

INSUFFICIENT SPEED OF TESTING

DECREASING CIRCUIT OBSERVABILITY

INCOMPLETE TEST SET

SIMPLISTIC FAULT MODELS

Tester Pin Electronics

Tester Architecture

Growing Die Size

Too Costly DFT

Immature Test Generation

Methodologies

Too High Complexity of

Fault Simulation

Lack of Understanding of Fault Mechanism


Fundamental Test ProblemFundamental Test Problem

Uncertain region

1.0E+5

1.0E+6

1.0E+7

1.0E+8

0.5 1 1.5 2 2.5 3 3.5 4Die Size [cm2]

Ann

ual V

olum

e[#

of

dies

per

yea

r]

Curve obtained for the “worst set” of DFT parameters

DO NOT APPLY DFT

APPLY DFT

Curve obtained for the “best set” of DFT parameters

High QUALITY Design for Testability (DFT) impossible !



Cost ofTesting

Test-RelatedSilicon

TestPreparation

TestGeneration

TesterProgram

DFTDesign

TestExecution

Hardware Tester

Imperfect TestQuality

Escape LostPerformance

LostYield

ProbeCost

ManpowerCost

Volume DieArea

WaferCost

DefectDensity

WaferRadius

TestCardCost

DepreciationProbeLife

TesterCapitalCost

TesterSetupTime



Cprep = Ctest _ gen + Ctest _ prog + Cdesign _ of _ DFT

Ctest _ gen =Rman_hourTtest _ gen

V

Ttest _ gen = Ktest_geneA0 Ctest _ prog = βtest_progCtest _ gen

0

Examples of FUNDAMENTAL test problems:Examples of FUNDAMENTAL test problems:

vv Lack of the theory bridging the gap between circuit design Lack of the theory bridging the gap between circuit design decisions and test generation complexity.decisions and test generation complexity.

vv Superficial understanding of delay testing needs and principles. Superficial understanding of delay testing needs and principles.

vv ............................................................................................................................................................................................................


Fundamental Problems: DESIGNFundamental Problems: DESIGN

FUNDAMENTAL DESIGN PROBLEMS

INADEQUATE DESIGN QUALITY INSUFFICIENT DESIGN PRODUCTIVITY

INSUFFICIENT DESIGN

x -ABILITIES

INCOMPLETE DESIGN

OBJECTIVES SPECIFICATION

INEFFECTIVEAND UNRELIABLE INTRA AND INTER

DESIGN TEAM COMMUNICATION

CHANNELS

INADEQUATE CAD

ENVIRONMENTS/TOOLS

INSUFFICIENT DESIGN SPEC

VERIFICATION

INCREASING RESTRICTIVENESS

OF DESIGN DOMAIN

ACCEPTANCE OF SUB-

OPTIMUM SOLUTIONS

DESIGN LIMITEDVOLUME

INSUFFICIENT LEVELS OF DESIGN

REUSABILITY


Limitations of Design DomainLimitations of Design Domain

Metal 2Metal 2

Metal 1Metal 1

RRcc

RR ww

RRcc

RRcc

RRcc

x 100 000 000x 100 000 000

CC

Example of a Example of a FUNDAMENTAL FUNDAMENTAL

CAD problem:CAD problem:Lack of adequate Lack of adequate design data base design data base which:which:

–– Allows to model Allows to model all timing relevant all timing relevant interconnect interconnect geometry details;geometry details;–– Enables efficient Enables efficient parasitic extraction parasitic extraction in VERY large in VERY large circuits;circuits;–– .......................... ..........................


Sub-optimum DesignsSub-optimum Designs

Intel P6 ( Kalmath)Intel P6 ( Kalmath)

CISC (32 bit data/instr.)CISC (32 bit data/instr.)

MPEG2MPEG2

7.5 M (with 32K L1 cache)7.5 M (with 32K L1 cache)

203 mm203 mm

Mitsubishi D30VMitsubishi D30V

DSP LIW (64 bit instr.)DSP LIW (64 bit instr.)

MPEG2MPEG2

300 K + 64K SRAM 300 K + 64K SRAM

37 mm37 mm

22 22

Is Mitsubishi design close enough to optimum ?

Example of a FUNDAMENTAL design problem:Example of a FUNDAMENTAL design problem: Lack of adequate objective functions for hardware-Lack of adequate objective functions for hardware-software co-design which :software co-design which :

–– Take into account cost and time of design process; Take into account cost and time of design process;–– Forecast volume to be sold; Forecast volume to be sold;–– Predict true cost of manufacturing. Predict true cost of manufacturing.


ConclusionsConclusions

vv Microelectronics industry may approach a high-Microelectronics industry may approach a high-cost-of-manufacturing-based crisis;cost-of-manufacturing-based crisis;

vv Design&Test may need to:Design&Test may need to:

–– operate with lower time and “$” budgets;operate with lower time and “$” budgets;

–– become a main and the only provider of market become a main and the only provider of market advantage;advantage;

–– deliver much deliver much betterbetter designs. designs.

vv Design&Test community need to re-think the Design&Test community need to re-think the traditional view on its role and strategy;traditional view on its role and strategy;


ConclusionsConclusions

vv Community-wide collaboration;Community-wide collaboration;

vv Consensus on the initial “Vision”.Consensus on the initial “Vision”.

vv SIA Focus Center ?SIA Focus Center ?

vv Multi-disciplinary cross-domain approaches;Multi-disciplinary cross-domain approaches;

FUNDAMENTAL DESIGN PROBLEMS

INADEQUATE DESIGN QUALITY INSUFFICIENT DESIGN PRODUCTIVITY

D&T Research Strategy ProposalD&T Research Strategy Proposal

Step #1:Step #1:

sia road map and design&test - carnegie mellon …users.ece.cmu.edu/~maly/maly/sia97.pdf · vv...

Documents