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SGBB GOVT POLYTECHNIC COLLEGE, SIROHI

SUB- BASIC ELECTRONICS (EE201) CLASS TEST-II (SESSION 2017-18) MAX MARKS-15

DATE-25 Jan 2018 II YEAR-ELECTRICAL MAX TIME- 1 HR

Name of Faculty-RAHUL SINGH RAJPUROHIT (LECT-EL)

Q1 ) Explain the construction and working operation of JFET. (3+4=7)

Q 2) What is analog and digital signals? Draw its diagram. (3)

Q 3) Write short note on any one- (5)

(i)Varactor Diode (ii)Advantage of Digital Techniques

Model Answer

Q 1) Explain the construction and working operation of JFET. (3+4=7)

Ans- In an N-channel JFET an N-type silicon bar, referred to as the channel, has two smaller pieces of

P-type silicon material diffused on the opposite sides of its middle part, forming P-N junctions, as

illustrated in figure. The two P-N junctions forming diodes or gates are connected internally and a

common terminal, called the gate terminal, is brought out. Ohmic contacts (direct electrical connections)

are made at the two ends of the channel—one lead is called the Source terminal S and the other Drain

terminal D.

Fig- Construction of N-channel JFET

Working- The working of JFET can be explained by discussing about how to turn on N-channel JFET

and how to turn off N-channel JFET. For turning ON a N-channel JFET, positive voltage of VDD has to

be applied to the drain terminal of the transistor w.r.t (with respect to) source terminal such that the drain

terminal must be appropriately more positive than the source terminal. Thus, current flow is allowed

through the drain to source channel. If the voltage at the gate terminal, VGG is 0V, then there will be

maximum current at the drain terminal and N-channel JFET is said to be in ON condition.

For turning off the N-channel JFET, the positive bias voltage can be turned off or a negative voltage can

be applied to the gate terminal. Thus, by changing the polarity of the gate voltage the drain current can

be reduced and then N-channel JFET is said to be in OFF condition.

2) What is analog and digital signals? Draw its diagram. (3)

Ans- An analog signal is a continuous wave denoted by a sine wave (pictured below) and may vary in

signal strength (amplitude) or frequency (time). It has infinite amplitude levels.

A digital signal is a signal that is being used to represent data as a sequence of discrete values; at any

given time it can only take on one of a finite number of values. It has two fixed amplitude level i.e. High

+5 Volatge(1) and Ground (0).

Q 3) Write short note on any one- (5)

(i)Varactor Diode (ii)Advantage of Digital Techniques

(i)Varactor Diode- Avaricap diode, varactor diode, variable capacitance diode, variable reactance

diode or tuning diode is a type of diode designed to exploit the voltage-dependent capacitance of a

reversed-biased p–n junction. Varactors are used as voltage-controlled capacitors.

Varactors are operated in a reverse-biased state, so no DC current flows through the device. The amount

of reverse bias controls the thickness of the depletion zone and therefore the varactor's junction

capacitance. Generally, the depletion region thickness is proportional to the square root of the applied

voltage, and capacitance is inversely proportional to the depletion region thickness. Thus, the

capacitance is inversely proportional to the square root of applied voltage.

All diodes exhibit this variable junction capacitance, but varactors are manufactured to exploit the effect

and increase the capacitance variation.

https://en.wikipedia.org/wiki/Signal_(electrical_engineering)https://en.wikipedia.org/wiki/Discrete_spacehttps://en.wikipedia.org/wiki/Diodehttps://en.wikipedia.org/wiki/Capacitancehttps://en.wikipedia.org/wiki/P%E2%80%93n_junctionhttps://en.wikipedia.org/wiki/Capacitorshttps://en.wikipedia.org/wiki/Reverse-biasedhttps://en.wikipedia.org/wiki/Depletion_zonehttps://en.wikipedia.org/wiki/Square_roothttps://en.wikipedia.org/wiki/Capacitance

(ii)Advantage of Digital Techniques

Ans-

1. Digital systems are generally easier to design. This is because the circuits that are used are switching

circuits, where exact values of voltage or current are not important, only the range (HIGH or LOW) in

which they fall.

2. Information storage is easy. this is accomplished by special switching circuits that can latch onto

information and hold it for as long as necessary.

3. Accuracy and precision are greater. Digital systems can handle as many digits of precision as you

need simply by adding more switching circuits. In analog systems, precision is usually limited to three

or four digits because the values of voltage and cureent are directly dependent on the circuit component

values.

4. Operation of digital techniques can be programmed.

5. Digital circuits are less affected by noise. Spurious fluctuations in voltage (noise) are not as critical in

digital systems because the exact value of a voltage is not important, as long as the noise is not large

enough to prevent us from distinguishing a HIGH from a LOW.

6. More digital circuitry can be fabricated on IC chips.

7. Less expensive and more reliable.


MAX TIME- 1 HR CLASS TEST-II (SESSION 2017-18) MAX MARKS-15

SUB- ELECTRICAL CIRCUIT THEORY (EE205) DATE-29/01/2018

NOTE- ATTEMPT ALL THREE QUESTIONS.

(1) Write the statement of Maximum Power transfer theorem and prove it.

(2) In following circuit, find thevenin voltage and thevenin resistance across terminals A and B :-

(3) In following circuit, find Node voltages 𝑉1 and 𝑉2 :-

MODEL ANSWERS

Answer 1:-

Statement :-

The maximum power transfer theorem states that in a linear , bilateral DC

network , maximum power is delivered to the load when the load resistance is

equal to the internal resistance of a source.

If it is an independent voltage source, then its series resistance (internal

resistance Rs) or if it is independent current source, then its parallel resistance

(internal resistance Rs) must equal to the load resistance RL to deliver maximum

power to the load.

Proof of Maximum Power Transfer Theorem

The maximum power transfer theorem ensures the value of the load resistance ,

at which the maximum power is transferred to the load.

Consider the below DC two terminal network (left side circuit) , to which the

condition for maximum power is determined , by obtaining the expression of

power absorbed by load with use of mesh or nodal current methods and then

derivating the resulting expression with respect to load resistance RL.

But this is quite a complex procedure. But in previous articles we have seen that

the complex part of the network can be replaced with a Thevenin’s equivalent as

shown below.

The original two terminal circuit is replaced with a Thevenin’s equivalent circuit

across the variable load resistance. The current through the load for any value of

load resistance is

Form the above expression the power delivered depends on the values of RTH and

RL. However the Thevenin’s equivalent is constant, the power delivered from this

equivalent source to the load entirely depends on the load resistance RL. To find

the exact value of RL, we apply differentiation to PL with respect to RL and

equating it to zero as

Therefore, this is the condition of matching the load where the maximum power

transfer occurs when the load resistance is equal to the Thevenin’s resistance of

the circuit. By substituting the Rth = RL in equation 1 we get

The maximum power delivered to the load is,

Total power transferred from source is

PT = IL2 (RTH + RL)

= 2 IL2 RL …………….(2)

Hence, the maximum power transfer theorem expresses the state at which

maximum power is delivered to the load , that is , when the load resistance is

equal to the Thevenin’s equivalent resistance of the circuit. Below figure shows a

curve of power delivered to the load with respect to the load resistance.

Answer 2:-

Step 1:- Calculation of Thevenin Voltage (𝑉𝑡ℎ)

According to question terminals A & B are open, so current through 1 ohm

resistor is 0. So voltage through it 0. So 𝑉𝑡ℎ is voltage across 5A current source.

And 5A & 3 ohm are in parallel, so 𝑉𝑡ℎ is across 3 ohm resistance.

So our circuit is

Applying KCL at node P, I1 + I2 + I3 = 0

𝑉𝑡ℎ−10

2 +

𝑉𝑡ℎ

3 - 5 = 0 →

3𝑉𝑡ℎ−30+2𝑉𝑡ℎ

6 = 5

5𝑉𝑡ℎ = 60

𝑉𝑡ℎ = 60

5 = 12 volt.

Step 2:- Calculation of thevenin resistance (𝑅𝑡ℎ)

For this independent sources (voltage, current ) are replace by their internal

resistances. So 10V voltage source is short-circuit and 5A current source is open-

circuited.

In above circuit, 2 ohm and 3 ohm resistance are in parallel, so net resistance is

=2∗3

2+3 =

6

5 ohm

So Thevenin resistance 𝑅𝑡ℎ = 6

5 + 1 =

11

5ohm

Answer 3:-

Applying KCL at node 1

𝑉 1 − 𝑉2

2 +

𝑉1

5 +

𝑉1− 10

1 = 0 →

5𝑉1− 5𝑉2+ 2𝑉1+ 10𝑉1− 100

10 =

0

17𝑉1 - 5𝑉2 = 100 …………….. (1)

Applying KCL at node 2

𝑉2− 𝑉1

2 +

𝑉2

10 - 2 =0 →

5𝑉2− 5𝑉1+𝑉2− 20

10 = 0

6𝑉2 − 5𝑉1 = 20 ……………….. (2)

Equation 1 is multiply with 6 and equation 2 is multiply with 5 and adding both

102𝑉1 - 30𝑉2 = 600

-25𝑉1 + 30𝑉2 = 100 → 77𝑉1 = 700 → 𝑉1 = 700

77 = 9.09

Put 𝑉1 in equation (2), we get

6𝑉2 - 5*9.09 = 20 → 6𝑉2 = 20 – 45.45

𝑉2 = −25.45

6 = -4.241


MAX TIME- 1 HR CLASS TEST-II (SESSION 2017-18) MAX MARKS-15

SUB- MICROPROCESSOR & C-PROGRAMING (EE208) DATE-29/01/2018

NOTE- ATTEMPT ALL THREE QUESTIONS.

1) Draw pin diagram of 8085 microprocessor.

2) Explain arithmetic and logical operations.

3) Write keywords used in C-language.

MODEL ANSWERS

Answer 1:-

The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte

of memory.

It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3

MHz.

The pins on the chip can be grouped into 6 groups:

Address Bus.

Data Bus.

Control and Status Signals.

Power supply and frequency.

Externally Initiated Signals.

Serial I/O ports.

8085 Pin description

Higher Order Address pins- A15 – A8

The address bus has 8 signal lines A8 – A15 which are unidirectional.

Lower Order Address/ Data Pins- AD7-AD0

These are time multiplexed pins and are de-multiplexed using the pin ALE

So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 –

D7 at the same time.

During the execution of the instruction, these lines carry the address

bits during the early part, then during the late parts of the execution,

they carry the 8 data bits.

In order to separate the address from the data, we can use a latch to

save the value before the function of the bits changes.

Control Pins – RD, WR

These are active low Read & Write pins

Status Pins – ALE, IO/M (active low), S1, S0

ALE (Address Latch Enable)-Used to de-multiplex AD7-AD0

IO/M – Used to select I/O or Memory operation

S1,S0 – Denote the status of data on data bus

Interrupt Pins – TRAP, RST7.5, RST 6.5, RST 5.5, INTR, INTA

These are hardware interrupts used to initiate an interrupt service

routine stored at predefined locations of the system memory.

Serial I/O pins – SID (Serial Input Data), SOD (Serial Output Data)

These pins are used to interface 8085 with a serial device.

Clock Pins- X1, X2, CLK(OUT)

X1, X2– These are clock input pins. A crystal is connected between these

pins such that fcrystal= 2f8085 where fcrystal= crystal frequency & f8085 =

operating frequency of 8085

CLK(OUT) – This is an auxiliary clock output source

Reset Pins – Reset In (active low), Reset Out

Reset In is used to reset 8085 whereas Reset Out can be used to reset

other devices in the system

DMA (Direct Memory Access) pins – HOLD, HLDA

These pins are used when data transfer is to be performed directly

between an external device and the main memory of the system.

Power Supply Pins – +VCC, VSS

Answer 2:- Logical Instructions:-

Opcode Operand Explanation

of

Instruction

Description

CMP R

M

Compare

register or

memory

with

accumulator

The contents of the operand (register or memory) are M

compared with the contents of the accumulator. Both contents

are preserved . The result of the comparison is shown by setting

the flags of the PSW as follows:

if (A) < (reg/mem): carry flag is set

if (A) = (reg/mem): zero flag is set

if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

CPI 8-bit

data

Compare

immediate

with

accumulator

The second byte (8-bit data) is compared with the contents of

the accumulator. The values being compared remain

unchanged. The result of the comparison is shown by setting the

flags of the PSW as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set

if (A) > data: carry and zero flags are reset

Example: CPI 89H

ANA R

M

Logical AND

register or

memory

with

accumulator

The contents of the accumulator are logically ANDed with M the

contents of the operand (register or memory), and the result is

placed in the accumulator. If the operand is a memory location,

its address is specified by the contents of HL registers. S, Z, P are

modified to reflect the result of the operation. CY is reset. AC is

set.

Example: ANA B or ANA M

ANI 8-bit

data

Logical AND

immediate

with

accumulator

The contents of the accumulator are logically ANDed with the

8-bit data (operand) and the result is placed in the

accumulator. S, Z, P are modified to reflect the result of the

operation. CY is reset. AC is set.

Example: ANI 86H

XRA R

M

Exclusive OR

register or

memory

with

accumulator

The contents of the accumulator are Exclusive ORed with M the




modified to reflect the result of the operation. CY and AC are

reset.

Example: XRA B or XRA M

XRI 8-bit

data

Exclusive OR

immediate

with

accumulator

The contents of the accumulator are Exclusive ORed with the 8-

bit data (operand) and the result is placed in the accumulator. S,

Z, P are modified to reflect the result of the operation. CY and

AC are reset.

Example: XRI 86H

ORA R

M

Logical OR

register or

memory

with

accumulator

The contents of the accumulator are logically ORed with M the




modified to reflect the result of the operation. CY and AC are

reset.

Example: ORA B or ORA M

ORI 8-bit

data

Logical OR

immediate

with

accumulator

The contents of the accumulator are logically ORed with the 8-

bit data (operand) and the result is placed in the accumulator. S,

Z, P are modified to reflect the result of the operation. CY and

AC are reset.

Example: ORI 86H

RLC none Rotate

accumulator

left

Each binary bit of the accumulator is rotated left by one

position. Bit D7 is placed in the position of D0 as well as in the

Carry flag. CY is modified according to bit D7. S, Z, P, AC are not

affected.

Example: RLC

RRC none Rotate

accumulator

right

Each binary bit of the accumulator is rotated right by one

position. Bit D0 is placed in the position of D7 as well as in the

Carry flag. CY is modified according to bit D0. S, Z, P, AC are not

affected.

Arithmetic Instructions:-

Opcode Operand Explanation of

Instruction

Description

ADD R

M

Add register or

memory, to

accumulator

The contents of the operand (register or memory)

are added to the contents of the accumulator and

the result is stored in the accumulator. If the

operand is a memory location, its location is

Example: RRC

RAL none Rotate

accumulator

left through

carry

Each binary bit of the accumulator is rotated left by one position

through the Carry flag. Bit D7 is placed in the Carry flag, and the

Carry flag is placed in the least significant position D0. CY is

modified according to bit D7. S, Z, P, AC are not affected.

Example: RAL

RAR none Rotate

accumulator

right

through

carry

Each binary bit of the accumulator is rotated right by one

position through the Carry flag. Bit D0 is placed in the Carry flag,

and the Carry flag is placed in the most significant position D7.

CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RAR

CMA none Complement

accumulator

The contents of the accumulator are complemented. No flags

are affected.

Example: CMA

CMC none Complement

carry

The Carry flag is complemented. No other flags are affected.

Example: CMC

STC none Set Carry Set Carry

Example: STC

specified by the contents of the HL registers. All flags

are modified to reflect the result of the addition.

Example: ADD B or ADD M

ADC R

M

Add register to

accumulator with

carry

The contents of the operand (register or memory)

and M the Carry flag are added to the contents of

the accumulator and the result is stored in the

accumulator. If the operand is a memory location,

its location is specified by the contents of the HL

registers. All flags are modified to reflect the result

of the addition.

Example: ADC B or ADC M

ADI 8-bit data Add immediate to

accumulator

The 8-bit data (operand) is added to the contents of

the accumulator and the result is stored in the

accumulator. All flags are modified to reflect the

result of the addition.

Example: ADI 45H

ACI 8-bit data Add immediate to

accumulator with

carry

The 8-bit data (operand) and the Carry flag are

added to the contents of the accumulator and the

result is stored in the accumulator. All flags are

modified to reflect the result of the addition.

Example: ACI 45H

LXI Reg. pair,

16-bit data

Load register pair

immediate

The instruction loads 16-bit data in the register pair

designated in the operand.

Example: LXI H, 2034H or LXI H, XYZ

DAD Reg. pair Add register pair

to H and L

registers

The 16-bit contents of the specified register pair are

added to the contents of the HL register and the

sum is stored in the HL register. The contents of the

source register pair are not altered. If the result is

larger than 16 bits, the CY flag is set. No other flags

are affected.

Example: DAD H

SUB R

M

Subtract register

or memory from

accumulator

The contents of the operand (register or memory )

are subtracted from the contents of the

accumulator, and the result is stored in the

accumulator. If the operand is a memory location,


registers. All flags are modified to reflect the result

of the subtraction.

Example: SUB B or SUB M

SBB R

M

Subtract source

and borrow from

accumulator

The contents of the operand (register or memory )

and M the Borrow flag are subtracted from the

contents of the accumulator and the result is placed

in the accumulator. If the operand is a memory

location, its location is specified by the contents of

the HL registers. All flags are modified to reflect the

result of the subtraction.

Example: SBB B or SBB M

SUI 8-bit data Subtract

immediate from

accumulator

The 8-bit data (operand) is subtracted from the

contents of the accumulator and the result is stored

in the accumulator. All flags are modified to reflect

the result of the subtraction.

Example: SUI 45H

SBI 8-bit data Subtract

immediate from

accumulator with

borrow

The contents of register H are exchanged with the

contents of register D, and the contents of register L

are exchanged with the contents of register E.

Example: XCHG

INR R

M

Increment

register or

memory by 1

The contents of the designated register or memory)

are incremented by 1 and the result is stored in the

same place. If the operand is a memory location, its

location is specified by the contents of the HL

registers.

Example: INR B or INR M

INX R Increment

register pair by 1

The contents of the designated register pair are

incremented by 1 and the result is stored in the

same place.

Example: INX H

DCR R

M

Decrement

register or

memory by 1

The contents of the designated register or memory

are M decremented by 1 and the result is stored in

the same place. If the operand is a memory location,


registers.

Example: DCR B or DCR M

DCX R Decrement

register pair by 1

The contents of the designated register pair are

decremented by 1 and the result is stored in the

same place.

Example: DCX H

DAA none Decimal adjust

accumulator

The contents of the accumulator are changed from a

binary value to two 4-bit binary coded decimal (BCD)

digits. This is the only instruction that uses the

auxiliary flag to perform the binary to BCD

conversion, and the conversion procedure is

described below. S, Z, AC, P, CY flags are altered to

reflect the results of the operation.

If the value of the low-order 4-bits in the

accumulator is greater than 9 or if AC flag is set, the

instruction adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the

accumulator is greater than 9 or if the Carry flag is

set, the instruction adds 6 to the high-order four

bits.

Example: DAA

Answer 3:-

Keywords in C Programming Language :

1. Keywords are those words whose meaning is already defined by Compiler.

2. Cannot be used as Variable Name.

3. There are 32 Keywords in C.

4. C Keywords are also called as Reserved words .

32 Keywords in C Programming Language:-

auto double int struct

break else long switch

case enum register typedef

char extern return union

const float short unsigned

continue for signed void

default goto sizeof volatile

do if static while

SGBB Government Polytechnic College Sirohi2nd Class Test 2017-18Management (EE210)

Date 31/01/2018 Time:- 1Hr MM:- 151. लघघउधधोग कका पपंजजीकरण कजी ककारर्य वविवध कका विणर्यन कजीवजए I

Answer: लघघ उधधोग कका पपंजजीकरण करकानने सने उधमजी उन सभजी वविभकागधोपं सने सहयधोग एविपं स घवविधकाए पपरकाप्त कर सकतका हहै जधो लघघ उधधोगधो कने वहत कने वलए सरककार दकारका स्थकावपत वकयने गयने हहै I उधधोग वनदनेशकालय ममें पपंजजीकरण करनने कका ककायर्य दधो चरणधोपं ममें वकयका जकातका हहै-(i) अस्थकाई पपंजजीकरण ( Provisional Registration): जब कधोई उधमजी लघघ उदधोग आरम्भ करनका चकाहतका हहै

तधो उसने अस्थकाई पपंजजीकरणकने वलए सम्बपंवधत वजलका उदधोग कमें दपर कने कयकार्यलय ममें वनधकार्यवरत फफॉमर्य पर आविनेदन करनका पड़तका हहै I आविनेदन पतपर दधो पपरवतयधोपं ममें दनेनका पड़तका हहै I अस्थकाई पपंजजीकरण कने पश्चकातप हजी कधोई उदमजी उदधोग कधो पपरकारम्भ करनने कने वलए वनम्नवलवखित ककायर्यविकाहजी कर सकतका हहै: (a) औदधोवगक बस्तजी ममें शनेड कने वलए आविनेदन(b) उदधोग कजी इमकारत बनकानने कने वलए स्विजीकक वत कने वलए आविनेदन,(c) वबजलजी- पकानजी कननेक्शन कने वलए आविनेदन,रकाज्य ववित्त वनगम यका वकसजी अन्य ववित्तजीय सपंस्थकान सने ववित्तजीय सहकायतका कने

वलए आविनेदन,(d) वबकप रजी कर, एक्सकाइज ड्ययटजी आवद कका पपंजजीकरण (e) कच्चने मकाल कधो आयत करनने कने वलए आविनेदन आवद

(ii) स्थकारजी पपंजजीकरण (Permanent Registration): जब उदमजी उदधोग स्थकावपत करनने कजी सब ककायर्यविकाहजी पयणर्य कर चयकका हधोतका हहै जहैसने-उदधोग कजी Building तहैयकार हधो, वबजलजी-पकानजी कननेक्शन वमल जकायने, ककारखिकानने कजी मशजीन स्थकावपतहधो जकायने तधो विह स्थकायजी पपंजजीकरण कने वलए आविनेदन कर सकतका हहै I स्थकायजी पपंजजीकरण कने वलए एक वनधकार्यवरत आविनेदन पतपर भकार कने वजलका उदधोग कमें दपर कने ककायकार्यलय ममें जमका करकानका पड़तका हहै I आविनेदन पतपर कने जमका करनने कने सकात वदन कने अन्दर वजलका अवधककारजी, उदमजी कधो उदधोग कने वनरजीक्षण कने वलए तकारजीखि वि समय दने दनेतका हहै I जब वनरजीक्षणकतकार्य पयणर्यतयका सपंत घष्ट हधो जकातने हहै तधो पपंजजीकरण पपरमकाण पतपर जरजी कर दनेतने हहै I

2. वनवविदका वकतनने पपरककार कजी हधोतजी हहै तथका वनवविदका पपरवकप ररका कने पद वलवखिए I

Ans. वनवविदका सकामकान्यतका तजीन पपरककार कजी हधोतजी हहै—

(i) एकल वनवविदका: ज़ब कने विल एक हजी फमर्य सने वनवविदका आमपंवतपरत कजी जकाय तधो इसने एकल वनवविदका पद्धवत कहतने हहैं । पपरकाय यह पद्धवत एककावधकक त विस्त घओपं कने मकामलने ममें अपनकाई जकातजी हहै । कई बकार अत्यकावधक आविश्यकतका अथविका आपकातककालजीन वस्थवतयधोपं ममें अपनकाई जकातजी हहै । इसने अनघमकावनत मयल्य 10 हज़कार रूपयने सने कम कने सकामकान कने कप रय ममें अपनकायका जकातका हहै ।

(ii) सजीवमत वनवविदका: इसममें सजीवमत सपंख्यका ममें आपयवतर्यकत्तकार्यओपं सने वनवविदकाएएँ आमपंवतपरत कजी जकातजी हहैं । इसने अन घमकावनत मयल्य 10 लकाखि रूपयने सने कम कने मकामलने ममें अपनकायका जकातका हहै । सजीवमत वनवविदकाएएँ उन सभजी फमर्मों कधो भनेजजी जकानजी चकावहयने जधो पपंजजीकक त सयचजी ममें हधो तथका वपछपलने सफल आपयवतर्यकतकार्य कधो भजी अविश्य भनेजजी जकानजी चकावहयने । कम सने कम 3 वनवविदका पपरकाप्त हधोनने पर हजी विस्त घ कप रय कजी जका सकतजी हहै I

(iii) खिघलजी वनवविदका जब आम जनतका कधो वविजकापन जकारजी करकने वनवविदकाएएँ आमपंवत परत कजी जकातजी हहै तधो इसने खि घलजी वनवविदका पद्धवत कहतने हहै यह पद्धवत पपरकाय 10 लकाखि सने अवधक मयल्य कने सभजी मकामलधोपं ममें अपनकाई जकातजी हहै । खि घलजी वनवविदका कने मकामलने ममें वनवविदका सयचनका कका ठजीक ठजीक पपरककाशन अत्यपंत महत्विपयणर्य हहै वनवविदका सयचनका ममें मद कका सपंवक्षप्त वविविरण, वविवशष्ट, सघप घदर्यगजी कका स्थकान, बयकानका रकावश, वनरजीक्षण कजी शतर्ते तथका वनवविदका फमर्य कका मयल्य आवद वदयका जकानका आविश्यक हहैं । वनवविदका सयचनका कका पपरककाशन जनसम्पकर्य अवधककारजी कने मकाध्यम सने पपरम घखि दहैवनक समकाचकार पतपरधोपं ममें पपरककावशत वकए जकानने चकावहयने I

वनवविदका पपरवकप ररका : वनवविदकाओपं कने जकारजी करनने ममें एविपं भपंडकार सकामगपरजी कने कप रय हनेत घ कप रय आदनेश जकारजी करनने ममें वनम्न चरणधोपं सने ग घजरनका पड़तकाहहै I

1. वनवविदका पपरपतपर तहैयकार करनका ।

2. वनवविदका सयचनका जकारजी करनका ।

3. वनवविदका कजी फमर्मों कधो सयवचत करनका ।

4. मघहरबपंद वनवविदका पपरस्तकावि पपरकाप्त करनका ।

5. वनवविदका पपरस्तकावि कका खिधोलनका ।

6. पपरकाप्त वनवविदका पपरस्तकाविधोपं कका मयल्यकापंकन ।

7. तघल्नकात्मक दरधोपं विकालजी टहैब घलनेशन शजीट तहैयकार करनका ।

8. वनवविदका सवमवत कजी बहैठक एविपं वविविरणजी तहैयकार करनका ।

9. वनवविदका सवमवत दकारका तहैयकार वरपधोटर्य कका सक्षम अवधककारजी दकारका अन घमधोदन ।

10.कप रय आदनेश जकारजी करनका ।

3. रकाज्र ववित्त वनगमधोपं कजी ऋण रधोजनओपं पर वटिपण्णजी कजीवजरने IAns. रकाजस्थकान रकाज्र ववित्त वनगम दकारका उद्यवमरधोपं कधो ऋण पपरदकान करनने कने वलए वनम्नवलवखित रधोजनकाए शघरू कजी हहै:(i) सकामकान्र अविवध ऋण (Normal Term Loan): इस यधोजनका कने अपंतगतर्य वकसजी भजी यधोग्य इककाई कधो स्थकायजी

सम्पवतयधो कने वलए यवद विह वनजजी यका सकाविर्यजवनक कपं पनजी कने रूप ममें स्थकावपत हधो तधो अवधकतम 90 लकाखि और यवद विह एककाकजी यका सकाझनेदकारजी फकामर्य कने रूप ममें सपंगवठत कजी गई हहै तधो अवधकतम 30 लकाखि रुपयने तक कका ऋण स्विजीकक त वकयका जका सकतका हहै I वकन्त घ ऋण पपरकाप्त करनने विकालजी सपंस्थका कजी पवरयधोजनका लगत 5 करधोड़ रुपयने सने अवधक नका हधो I ऋण कका प घनर्यभ घगतकान अवधकतम 10 विरधोर्य ममें करनका हधोतका हहै I ऋण : स्विकामजी पयएँजजी अनघपकात 10 लकाखि रूपयने तक कने ऋण कने वलए 3 :1 तथका 10 लकाखि रूपयने सने अवधक कने ऋण कने वलए 2 : 1 हधोतका हहै I

(ii) कम्पधोवजटि टिमर्य लधोन (Composite Term Loan) : भविन वनमकार्यण, उपकरणधोपं कजी पपरकावप्त एविपं ककायर्यशजील पयएँजजी कजी आविश्यकतका कधो पयरका करनने हनेत घ वदयका जकातका हहै I अवधकतम सहकायतका रकाशजी 50000 रुपयने हहै I ऋण कका प घनर्यभ घगतकान 3 सने 10 विरधोर्य ममें करनका हधोतका हहै I

(iii) एकल वखिड़कजी ऋण (Single Window Loan) : इस यधोजनका कने तहत लघघ, अवत लघघ क्षनेतपर ममें स्थकावपत हधोनने विकालजी ऐसजी इककाईयका वजनकजी पवरयधोजनका लकागत 50 लकाखि रूपयने सने अवधक नहजी पं हहै उनकजी स्थकाई पवरसम्पवतयधो एविपं ककायर्यशजील पयएँजजी कने ऋण स्विजीकक त वकयने जकातने हहै I ऋण कका प घनर्यभ घगतकान अवधकतम 10 विरधोर्य ममें करनका हधोतका हहै I ऋण : स्विकामजी पयएँजजी अनघपकात 10 लकाखि रूपयने तक कने ऋण कने वलए 3 : 1 तथका 10 लकाखि रूपयने सने अवधक कने ऋण कने वलए 2 : 1 हधोतका हहै I

(iv) मवहलका उद्यमजी वनवध रधोजनका : यह यधोजनका मवहलकाओ ममें उदमशजीलतका कधो पपरधोत्सकावहत एविपं उनकका सम्विद्धर्यन करनने कने वलए लकाग घ कजी गयजी हहै I इस यधोजनका कने तहत उन इककाईयधोपं कधो सहकायतका पपरदकान कजी जकातजी हहै वजनकजी पवरयधोजनका लकागत 10 लकाखिरूपयने सने अवधक नहजी पं हधो I सकाझनेदकारजी सपंगठन कजी वस्थवत ममें मवहलका उदमजी कजी पयएँजजी भकागजीदकारजी न्ययनतम 51 % हधोनजी चकावहए Iऋण कजी प घनर्यभ घगतकान अविवध 10 विरर्य हधोतजी हहै I

(v) सहैम्फने क्स रधोजनका : यह यधोजनका भयतपयविर्य सहैवनकधो यका भयतपयविर्य सहैवनकधो कजी वविधविकाओ कधो स्विरधोजगकार पपरदकान करनने कने वलए लकाग घकजी गयजी हहै I यधोजनका ममें वमयकादजी ऋण 75 % तक एविपं ककायर्यशजील पयएँजजी ऋण 15 % कघ ल पवरयधोजनका लकागत कका वदयका जकाएगकाI ऋण कका प घनर्यभ घगतकान अवधकतम 5 विरधोर्य ममें करनका हधोतका हहै I

(vi) हधोटिल उद्यधोग सहकारतका रधोजनका(vii) तकनजीवशरनधोपं कने वलए ऋण (viii) अनघससवचित जकातजी / जनजकावत उद्यवमरधोपं कने वलए ऋण(ix) वशल्पबकाडजी रधोजनका आवद

€E- 242-2ndTest

Q-l 1k8 Steam at 20 bar sup€r heated lo 350 "c find the following :

l.Enthalphy 2. SPecificvolume 3 lnternalEneryX given tr = 212 4"c h.

= 2799.5 Ki /Kc vs=o.o995mr/Kc

Ans EnthalpY of super heated steam

-Hsup = hs + K! {q,'' t l

Hsup = 2799.5+2 1(350'212{)

=2799.5+288.96 : 30E8.46 K'IKC

Spe.ific volume of super Heated steam: v' = Vsx T"+ Ts

V, = o.O995rl35o+273) + 1212.4+271)

v, = 0.0995x{623) + (a85.al

v" = 1.283 m3/Kc

Intern.lEnergy -U.= h,- Px v'

=3088.46-20x100x1.2E3

=3088.45-255.67

= 2A32.79 $lKC

a- of 8en5on Boilerwith neat sket'h

5. Convection SuPer heater

6. Fumace

4. Convection Evaporator

s!pe.criucal, water tube steamboler with forc€d clrculationThh boiler was invented n theyear 1922 bY Mark Benson Thls

boiler is a suPer critical boiler nwhich the feed water lscomprest€d to a s!percfiticalpressure and ihis prevents theformatlon of bubbLes in thewate'tube surface. The bubbles do not

form becalse at supercrit capressure the densitv ofwater and

steam becones same li wasMark Be.son who fnst Proposedthe rdea to conpress rhewaieratsupercrltlcal Pressure beforeheatinginto boilerand du€ to th s

the Latent heat of water redlcesto zero. As the atent heat ofwater reduces to zefo the warcrdirecty changes into sreamwlthout the formation of bubbL€s

?. Feed Pump

Workingln Bcnso' Boiler. rhe f@d pudp increa$s e pe$urc ofrhe *rcr ro $e suFcrniel ple$ue iid thenn enreE inio rhe sonomizcr. Frcm economizs. rhc mtr rhc NaEr p6sl?ler rceives rhe hear rbrouCl nd'ation ad pdly Bss co.vened rn@ $Bn. Tre tnp€iarure misesalmo{ ro lho supercn cal remp€€rua Anft ftar nix(urc of $€m ond wdd enGB i'to converiveevapoaroi where ir is compldely hivened inroleam.nd may supelher.d @ sone degFe Final/y ilhp6*d $tough thc super hsrer to ob€ined the desired superheated $€m Inn supcd.aLed iem n the'!sd by turbines orcneim to pmduce rheelecdciLy.

AdvantagesThe vdiou adEnbges of the boiler m

lr n a drun Les boiler and hene rhe weiShr of rhi5 rype or boiler is 20'lo lss 6 compmd wil\

ll c.nbesrded very esily wirhin l5 [email protected] avoids bubble lmarion dle to rhe n'p€r nirical PlasuE ol w.rer'

This boilerm6y echieverhemsl.ficiency upro 90 %.

Applicationlhis supercriticalboiltis used in difrerenr indusrr6nechanisl pow*. The aveoee ope€tng pesua,degreCelsirs,250 br and 135 Lornerh.

Q-3 Expllid the wo.king of wate.level

ro geneftte nm lor ftc poducrionofelecricilyorEmp.nruE and €prcily ol beisor bo'ler is 6s0

indicaior Dd its use :

It is indicates tnewater level inside theboile.to an obseruer.

The wate. of the boiler cones into the Class tube lhrough the lower tube and thesteam

rhrough the uppertube. The water then stands in theslass tube at the sane level at in lhe

boiler Two.ock are used to cont.ol rhe Pa$ase of between the bo er and the glas tube

while the thi.d cock is in used to discharge sone oilhe water Fom inside th€ boiler to see

whethef the sauge is in p.ope. order or nor The gla$ tube is protectedbv neans of a

cove., nade orspe.iallytoughened class,whi.h will prevent ahv accident that mavhappen

due to breakinS of slars tube.ltis used toro.dinarvboilers

FCu.e water t evel Indicator

WATER LEVEL INDICAToR: Ihe function of the w.ter lev€l indicator is to ascertain

constantly and exactly the levelofwater in the boiter thetl.lt tu fitted in th€ front of

rhe boiler kom where it it earily visible to rhe oper.tor.

The unit consitB ot a strons glass tube whose ends pass throuch stufiing boxes

consi5ts of heat r€3ittin8 rubber packing to prevent leakage steam and water' The

llanses are bolted tofront end plate of the boiler, the upPer flange bein8nfted to the

stean spa.e and the lower to wrter 5p.ce in the boiler. There are rwo 'o(kt namelv

steam cock 6nd water cock lhich Gommunicate the boiler 5hell spa@s to the salge

Cla5s tube. When the handle of the cock, are vertical; thev are in opetation and the

water levelin the tub€ coiespo.ds towater level in the 5hell. A red mark on the Clas5

tube indicates the safe water level

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