session 5: projects 1. physical limits of technology scaling : 2 scaling and efficiency

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Introduction to VLSI Interconnect Design Session 5: Projects 1

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Page 1: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Introduction to VLSI Interconnect

Design

Session 5: Projects

1

Page 2: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsPhysical Limits of Technology Scaling :

2

SCALING AND EFFICIENCY

Page 3: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsRLC extraction :

3

Inductance Modeling

Reducing Capacitance

Skin Effect / Anomalous Skin Effect

Page 4: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsInterconnect Delay :

4

High Speed Global On-Chip Interconnects

Compact Model for Delay

Near Speed-of-Light On-Chip Electrical Interconnects

Moment-Matching Technique

Page 5: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsInterconnect Noise :

5

Moment-Matching Technique

Page 6: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsRepeater Insertion:

6

Page 7: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsBit Rate Limitation :

7

Data Integrity : maximum data transfer rate.

Digital communication

Throughput-Centric Wave-Pipelined Interconnect

Page 8: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsProcess Variations :

8

Page 9: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsPower Dissipation :

9

Page 10: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsClock Distribution :

10

Page 11: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project Topics3D Integration:

11

Electrical modeling of Interconnects in 3-D ICs

Page 12: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsSpeed/Power/Area Tradeoffs :

12

Page 13: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsPower Distribution / Electromigration :

13

• Design / Analysis / Optimization of power distribution network Local power distribution network Global power distribution network

Page 14: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsImpact of Cu vs. Al Metallization on Performance :

14

Page 15: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsThermal Modeling of Metallic Interconnects :

15

Page 16: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsCNTs as Interconnect:

16

PERFORMANCE COMPARISON BETWEEN COPPER, CARBON NANOTUBE, AND OPTICS FOR OFF-CHIP AND ON-CHIP INTERCONNECTS

Page 17: Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

Project TopicsOptical Interconnects :

17