August, 1987 008155-001

4-Way Controller Service Manual

M8155A

PAGE STATUS

Effective Date

Page status iii/iv August, 1987

Table of Contents v through vii/viii August, 1987

Preface lX August, 1987

Section 1 1-1 through 1-4 August, 1987

Section 2 2-1 through 2-2 August, 1987

Section 3 3-1 through 3-20 August, 1987

Section 4 4-1 through 4-6 August, 1987

Section 5 5-1 through 5-2 August, 1987

Section 6 6-1 through 6-6 August, 1987

Section 7 7-1 through 7-12 August, 1987

Appendix A A-I through A-6 August, 1987

iii/iv M8155A

1.1 1.2 1.3

SECTICE 2

2.1 2.2 2.3

SECTICE 3

3.1 3.2-3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.4 3.2.4.1 3.2.4.2 3.2.4.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 3;4.1 3.4.2 3.4.2.1 3.4.2.2 3.4.3 3.4.3.1 3.4.3.2 3.4.4 3.4.5

TABLE OF <nll'ENI'S

Page

~neral ••••••••••••••• ~ ••••••••••••••••.•.•••••••••••• •• 1-1 PCBt\ ~scription •••••••••••••••••••••••••••••••••••••• -•• 1-1 S~if ications •••••••••••••••••••••••••••••••••••••••••• 1-1

~neral •••••••••••••••• " •••••••••••••••••••••••••••••••• • 2-1 Unpacking/Packing Instructions •••••••••••••••••••••••••• 2-1 O{::erator Interface •••••••••••••••••••••••••••••••••••••• 2-1

~neral ••••••••••••••••••••••••••••••••••••••.••••••••• • 3-1 System I/O Interface ••••••••••••••

I/O Protocol Phases ••••••••••• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

••• 3-1 • •• 3-1

Data Packet Preparation ••••••••••••••••••••••••• 3-3 Command Block Preparation ••••••••••••••••••••••• 3-3 Corrrnand Execution ••••••••••• Conmand Tennination ••••••

................... . 3-4

Interrupt Structure ••••• Z80A Interrupts •••••

• • • • • • • • • • • • • • • • • • • • • • .3-6 • • • • • • • • • • • • • • • • • • • • • • • • • • • .3-6 • • • • • • • • • • • • • • • • • • • • • • • • • • • .3-6

System Interrupts ••••••••••••••••••••••••••••••• 3-6 Serial Communications Channels ••••••••••••••••••• ••• 3-7

••• 3-7 ~s~ge i?OI1nlElt ••••••••••••••••••••••••••••••• Signal I.<>a.ding •••••••••••••••••••••••••••••••••• 3-8

4-way Asynchronous Protocol ••••••••••••••••••••••••• 3-8 Data Line i?OI1nlElt ••••••••••• • • • • • • • • • • • • • • • • • Buffer i?low Control ~thods •••••••••••••••••

•••• 3-8 •••• 3-9

RS-232C Protocol Used by the 4-way ••••••••••• ••• 3-9 4-way Initialization •••••••••••••••••••••••••••••••••••• 3-11

Initialization Criteria ••••••••••••••••••••••••••••• 3-11 ROO Checkstnn ..•..................................... 3-11 ~.ry Test ......................................... 3-11 sec l.A:::x:>p Test ....................................... 3-11 Error Re]?C>rting ••••••••••••••••••••••••••••••••••••• 3-12 Reset Routine ••••••••••••••••••••••••••••••••••••••• 3-12

~tailed Hardware ~scription ••••••••••••••••••••••••••• 3-13 r:t1A Interface Circuits •••••••••••••••••••••••••••••• 3-13 Communications Interface Circuits ••••••••••••••••••• 3-14

••••• 3-14 ••••• 3-14

Serial Communications Controllers (Sces) ••• SCC Interrupt Acknowledge ••••••••••••••••••

Central Processor Logic ••••••••••••••••••••••••••• • .3-14 Read/Write System Memory •••••••••••••••••••••• • .3-14 Read Only Merrory (RCM) • • • • • • • • • • • • • • • • • • • • • • • • • .3-15

Read/Write Registers ••••••••••••••••••••••••••• :Ba.ud Rate Progranming ••••••••••••••••••••••••••

v

••••• 3-15 ••••• 3-17

M8155A

3.4.6 3.4.7 3.4.8

4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4

6.1

7.1

APPmDIX A

M8155A

TABLE OF <XNrENrS (cont' d)

Page

FONC.rICtiAL DESCRIPl'ICfi (cont' d)

status Registers •••••••••••••••••••••••••••••••••••• 3-17 Instruction Register •••••••••••••••••••••••••••••••• 3-18 Clock Circuitry •••••••••••••• " •••••••••••••••••••••• 3-19

Preventive t1a.intenance." ••••••••••••••••••••••••••••••••• 4-1 Corrective t1a.intenance •••••••••••••••••••••••••••••••••• 4-1 Power-Up Initialization And Self Test ••••••••••••••••••• 4-1

Power-Up or Hard Reset Self-Tests ••••••••••••••••••• 4-1 Soft Reset Self-Test •••••••••••••••••••••••••••••••• 4-2

Four-way Diagnostics •••••••••••••••••••••••••••••••••••• 4-2 System Power-Dn Self-Tests •••••••••••••••••••••••••• 4-2 Four-Way Logic Test (~y) •••••••••••••••••••••••••• 4-3 Four-way Function Select Test (FWFS) •••••••••••••••• 4-3 System Interaction Test (SIT) ••••••••••••••••••••••• 4-3

Hardware Configuration •••••••••••••••••••••••••••••••••• 4-3

ILLUSTRATED PARI'S LIST

Introduction •••••••••••••••••••••••••••••••••••••••••••• 6-1

IOOIC DIAGRAM

Introduction •••••••••••••••••••••••••••••••••••••••••••• 7-1

LIST OF ImIC DIAGRAM ~CS

Vl.

Figure

1-1 1-2 3-1 6-1 7-1

Table

1-1 3-1 3-2 3-3 3-4

6-1

LIST OF ILLUSTRATIOOS

Page

4-Way Controller PCBA - Part No. 903390 ••••••••• ~ ••••••• x Location of Major Components on PCBA •••••••••••••••••••• 1-2 4-way Controller Functional Block Diagram ••••••••••••••• 3-2 4-way Controller PCsA (P/N 903390) •••••••••••••••••••••• 6-2 4-way Controller PCBA - Logic Diagram ••••••••••••••••••• 7-1

LIST OF TABT.ES

Page

4-way Controller Specifications ••••••••••••••••••••••••• 1-1 Asynchronous Communications Connector Data •••••••••••••• 3-8 RS-232C Signals Used by the 4-Way ••••••••••••••••••••••• 3-10 Functions Assigned to Each Read/Write Register •••••••••• 3-16 Time Constant Divisors Required for

Various Bctud Rates •••••••••••••••••••••••••••••••••••• 3-17 4-Way Controller PCBA Parts List •••••••••••••••••••••••• 6-3

vii/viii M8155A

This manual provides servlce information for the 4-way Controller Printed Cir­cuit Board Assembly. The information is presented as an aid for field service personnel, and supports the installation, operation, and maintenance of the PCBA.

The major topics covered in this manual are:.

Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Appendix A

Introduction Installation Functional Description Maintenance Removal/Replacement Illustrated Parts List Logic Diagrams List of Logic Diagram Mnemonics

This equipoent generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the in­struction manual, may cause interference to radio CCIlI'IIlDications. It has been tested and found to cutply with the limits for Class A CCIIplting devices pn-suant to SUbpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a cumterCial enviromelt. ~ration of this equipoent in a residential area is likely to calJse inter­ference in which case the user at his own expense will be required to take whatever measures that may be required to correct the in-terference. .

The use of shielded I/O cables is required when connecting writ to any and all optional peripheral or host devices. Failure to do so may violate FCC rules.

1.X M8155A

Figure 1-1. 4--way Controller PCR2\ - Part No. 903390

M8155A x

1.1 GENERAL

The 4-Way Controller PCBA, part number 903390, Figure 1-1, provides the means by which a MAl 2000/3000 computer system communicates with up to four RS-232C asynchronous data I ines to which Data Corrmunications Equipnent (DeE) can be connected. Each Serial Communications Channel ( SCC) has software programnable character formats and baud rates.

1.2 PCBA DESCRIPl'IOO

The 4-Way PCBA is designed for horizontal mounting in the 2000/3000 housing. All components are mounted on one side of the board and are hard wired and soldered except for the mrrcroprocessor, controller, controller firmware, input RAM and driver chips, which are socketed. Connections to the DeE equipnent being serviced are made via four metal-faced 9-pin D-type female connectors on one side of the PCBA. In addition to the electronic and electric components, the PCBA also contains a lO-position DIP switch for establishing bus conten­tion priorities and a green LED for indicating Initialization/PASS status (ON) or FAIL status (OFF). See Figure 1-2.

1.3 SPECIFICATIOOS

Table 1-1. 4-way Controller Specifications

~ating Environnent

Temperature:

Humidity:

Pressure:

20% to 80% relative humidity with a maximum gradient of 10% per hour, non-condensing.

Altitude equivalent 10,000 feet, maxlffium

storage and Shiwing Environnent

Temperature: -15° to 65°C (storage) -47° to 150°F -40° to 71°C (shipping) -72° to 160°F

Humidity: 10% to 90% relative humidity with no condensation permitted.

Pressure: Altitude equivalent 40,000 feet, maximum

1-1 M8155A

Figure 1-2. Location of Major CalPlnents on PCB1\

M8155A 1-2

1-3 M8155A

M8155A 1-4

INSTALIATION

2.1 GmFlW..

This section contains unpacking/packing instructions and installation requlre­ments for the 4-way Controller.

The 4-Way is shipped in an anti-static bag, inserted between two layers of styrofoam and sealed in a cardboard shipping carton. Unpack the 4-Way as follows:

1. Prior to accepting the package from the carrier, inspect the shi~ ping carton for signs of external damage. Any indication of ex­ternal damage must be noted on the carriers's shipping form and reported immediately to the MBF Sales Office.

When unpacking the PCBA, set aside the packing materials and shipping carton for use if it should become necessary to reship. The PCBA is ESD sensitive. Proper handling procedures should be used.

2. With the PCBA shipping carton in its upright position, open the carton and carefully remove the PCBA.

3. Unwrap the PCBA and inspect it for signs of shipping damage. Im­mediately report any damage to the MBF Sales Office.

2.3 OPmA'Im INTERFACE

There is no operator interface to the 4-way Controller.

2-1 M8155A

M8155A 2-2

SEX!1'ICfi 3

3.1 GEmlW,

This section contains a functional description of the 4-Way Controller on three levels: a general block diagram description, a discussion of the system 1/0 interface characteristics, and a detailed discussion of the 4-Way Control­ler circuits.

Figure 3-1 is a functional block diagram of the 4~y, showing the rela­tionship among the several functional areas of the controller. The ZaOA-CPU is the central processing element in the 4-Way Controller. (A detailed dis­cussion of the ZaOA-CPU is contained in the Zilog "ZaOA-CPU Technical Manual", which is not furnished.)

The Z-aOA-CPU provides data handling assistance to the Central Microprocessor Board (eM) in the DTU and controls overall 4-Way operations. When service is required to receive characters or other special conditions, the 4-Way issues an interrupt to the CMB. The CMB prep3res a data packet of between 1 and 512 bytes in length, creates a Command Block containing the location of the packet and places the information in a preprogrammed location in DTU memory. The 4-Way fetches the data from CMB Inem)ry one word at a time and sends an interrupt upon completion of the transfer.

3.2 SYSTEM I/O IN1'ERFACE

The System Software Interface consists of activation paths which allow the DTU software to communicate with the four SCCs (Serial Communications Channels) via the ZaOA-CPU and response (interrupt) paths which allow the SCCs to inter­rupt the CPU in the DTU .via the zaOA-CPU.

3.2.1 I/O Protocol Phases

The softwarelhardware protocol consists of from one to four separate phases which are described in the paragraphs indicated, as follows:

o Data Packet Preparation (paragraph 3.2.1.1) a Command Block Preparation (paragraph 3.2.1.2) o Command Execution (paragraph 3.2.1.3) o Command Termination (paragraph 3.2.1.4)

3-1 M8155A

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M5B DATA ~l5374 v--, ~8-D1~ 5240 k B : • 4 .I"vl I B 4.

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TRANSMIT STATUS

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LS374 STATUS : 8530 SCC-2

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~~~~----------~I , >I DATA

DRIVERS

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CONTROL ~~g~5~s --"'-""r-----s Vt ~ S240 BUS

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INTRPT LOGIC

Z80A CPUDATAK :

/16 A I /ADDRESS

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P2

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P4

3.2.1.1 Data Packet Preparation

A Data Packet (DP) must be established by the host CPU before any data trans­mission can be accomplished. The DP can be between 1 and 512 bytes in length and is organized as follows: The MSB of each word is sent first, followed by the LSB. The DP starting address is then placed in the preassigned Corrtnand Block for the specified fX)rt. The starting address must be placed on a word boundary, since the 4-Way is unable to address odd-byte locations.

3.2.1.2 Cbmmand Block Preparation

The Command Block is the mechanism that the host CMB uses to inform the 4-Way what corrtnand is to be performed, where the DP is, and how large the DP is. The following is the format required for each Corrtnand Block memory area:

(HJ AIDmSS <nll'ENrS

Base Address Command Word, Port A Add + 2 Data Byte Count, Port A Add + 4 Data Packet Address, MSB, Port A Add + 6 Data Packet Address, LSB, Port A Add + 8 Transfer status (4-Way to CMB), Port A Add + 10 Corrmand Word, Port B Add + 12 Data Byte Count, Port B Add + 14 Data Packet Address, MSB, PQrt B Add + 16 Data Packet Address, LSB, Port B Add + 18 Transfer status (4-Way to CMB), Port B Add + 20 Corrtnand Word, Port C Add + 22 Data Byte Count, Port C Add + 24 Data Packet Address, MSB, Port C Add + 26 Data Packet Address, LSB, Port C Add + 28 Transfer status (4-Way to CMB), Port C Add + 30 Coomand 'Word, Port D Add + 32 Data Byte Count, Port D Add + 34 Data Packet Address, MSB, Port D Add + 36 Data Packet Address, LSB, Port D Add + 38 Transfer status (4-Way to CMB) , Port D

SAMPLE <XHWID BI.DCK

15 14 13 12 11 10 09 08 I 07 I 06 I 05 I 04 03 02 I 01 I I I I I

0 0 0 0 0 0 0 0 I 0 I 0 I 0 I 0 0 Corrrnand I I I I

0 0 0 0 0 0 0 Data Packet Byte Count 0 0 0 0 0 0 0 0 MSB Data Packet Address

MID Data Packet Address LSB Data Packet Address 0 0 I 0 I 0 I 0 I o : 0 0 Command status (from 4-Way) I I I I

The CMB activates the 4-Way to execute a corrtnand by outputting the appropriate bit to the Instruction Register (Port Address D(x)AOOOH)

3-3 M8155A

All addresses sent to the 4-way must be on word boundaries; therefore, the actual 4-way starting address has been shifted one bit to the right. Example: To reach ad­dress 0640AH, the 4-way must recei ve OlAOSH.

3.2.1.3 Cbmmand Execution

Receipt in the Instruction Register of a valid flag from the CMB causes the 4-way to read the identified Command Block and execute the command as specified by the Command Word. The current command can be overridden or terminated under special conditions, as follows:

o The Port Reset/X-oN Reset command will clear all buffers and pointers in a port which is "hung up," without affecting the other ports. If an X­OFF condition exists in the same port, the Reset command will 1ssue an X-oN to the port and continue without loss of data.

o If a Command Word is not recognized by the 4-Way, it will transmit an Illegal Comnand code (OFF H) to the status byte of- the Command Block being serviced, causing a termination o~ the command.

The following are the commands issued to the 4-Way in the Command Block:

CDDE (Hex)

00 01 02 03 04 05 06 07 08 09 OA

OB-FF

OPEBATIOO

Not Used * Configure Data Transfer status Load Default Parameters Load X~N Value Load X~FF Value Single Byte Transfer X~N Enable/Disable Hard Flow Enable/Disable 7 Bit/8 Bit Not Used *

* - Illegal Command status 1S returned.

mJHN[C

(CONF) (Dr) (STS) (IDDEF) (IDXON) (IDXOF) (SINGL) (ENXON) (FLOW)

(EIGT)

o Cbmmand Configuration - For each register to be changed, the Data Packet (DP) must specify the register number first, followed by the new com­mand.

M8155A 3-4

o Data Transfer - UfX)n rece1v1ng the Command Block, the ZSOA-CPU causes the packet to be transferred a word at a time and simultaneously pro­grams the selected SCC in the proper sequence to handle the serial transmission of data to the neE being serviced. The Z80A-CPU then 1S­sues an interrupt to the CMB upon completion (Command Executed Interrupt) •

o status - The status Command is the only command that allows the 4-Way to write to system memory; therefore, the CMB reserves 8 consecutive word memory locations prior to issuing the status Command. UfX)n receiving the status Command, the 4-Way sends (via DMA) all the data in the Read Registers of the specified SCC. The Corrmand Block byte count is ignored while the 4-Way status information is written into CMB memory using the lower 8 data lines (the UJ;.Per lines· are indeterminate). The 8 lines contain the following information:

Add + 0

Add + 2 Add + 4 Add + 6 Add + 8 Add + 10

Add + 12

Add + 14

RmISrER ID.

RRO

RR1 RR2 RR3 RR10 RR12

RR13

RR15

DESCRIPrION

Transmit/Receive Buffer status; External status Special Receive status Unrocxiified Interrupt Vector Interrupt Pending Bits Miscellaneous status Lower Byte of Baud Rate Generator Time Constant Upper Byte of Baud Rate Generator Time Constant External/Status Interrupt Control In­formation

o IDad Port Default ParaIEte.rs - This command tells the 4-Way to load the default parameters to the SCC fX)rt being addressed: 9600 Baud, 1 start Bit, 1 stop Bit, Odd Parity.

o !Dad x-on Value - This conmand allows the CMB to alter, via software, the ASCII character which is used as the X-oN character for each fX)rt. The default values of 011H and 091H are assigned to all fX)rts of the 4-Way during initial Reset. The new value is placed in the Command Block in place of the Byte Count (lower 8 bits). An eight-bit alternate form of the X-oN value can also be used.

o IDad X-off Value - This command allows the CMB to alter, V1a software, the ASCII character which is used as the X-oFF character for each fX)rt. The default values of 013H and 093H are assigned to all fX)rts of the 4-Way during initial Reset. The new value is placed in the Command Block in place of the Byte Count (lower 8 bits). An eight-bit alternate form of the X-oFF value can also be used.

o Single Byte Transfer - This conmand allows the CMB to transfer a single byte of data from the CMB to the specified fX)rt. The data to be trans­ferred is placed in the Command Block in place of the Byte Count (lower 8 bits). No DP address is required. A Command Executed Interrupt is sent ufX)n completion of the transfer.

3-5 M8155A

o X-aN Enable/Disable - This command toggles the DTR and CTS lines to enable or disable the hardware flow controls. Flow control is enabled when the Byte Count of the Command Block equals 1 (OlH), and is disabled by any otQer Byte Count value. The default setting is Hardware Flow Control Enabled.

o 7-Bit/8-Bit Data - This command tells the 4-way whether it is handling 7-bit or 8-bit data. If 7-bit data is selected, the eighth bit is stripped off by the CMB. If 8-bit data is selected, all data is passed along to the 4-way with no conditioning. A Byte Count value of 1 (OlH) in the Command Block configures the specified 4-way receive port for 7 bits; any other value configures the port for 8 bits. The default set­ting is for 7 bits.

3.2.1.4 Oommand Termination

After each command is received, the 4-way firrrMare writes the status in the awropriate Coomand Block to infonn the CMB that the command has been executed ( 081H) or the 4-way did not understand the command (083H). If a Bus Error oc­curs during any of the DMAs, the 4-way terminates the current operation and places the value 083H in the status Byte of the awropriate Command Block.

3.2.2 Interrupt structure

3.2.2.1 Z80A Interrups

SCCs are programmed to interrupt the Z80A when they need service. An inter­rupt vector, originating the Read/Write registers, points to a transmit or receive service routine or to an external/status condition. As many as 17 different interrupt routines (four per channel and one board level) can be enabled under program control. Channel A has a higher priority than Channel B, C or D; Channel B has a higher priority than ehannel C or D, and so on. Within each channel, the priority levels are: receive, transmit, external/ status, respectively.

The see interrupt ~ignals share a cammon level and are OR'ed to a common in­terrupt signal. The first request for service is serviced first; the other secs are disabled. Simultaneous requests are handled on the basis of an A-B­c-o priority. When the command has been executed, or is detennined to be un­executable, the Z80A polls the SCCs for an empty FIFO transmit buffer and loads it. The 4-way then sends the CMB an awropriate interrupt.

3.2.2.2 System Interrups

When the CMB receives the transmitted interrupt from the 4-way, it responds with an Interrupt Acknowledge, causing the 4-Way to transmit an Interrupt Vec­tor containing the status information for the selected channel. The Interrupt Vector consists of a Base Address followed by three Additional Addresses, structured as follows:

M8155A 3-6

Base Address Add + 1 Add + 2 Add + 3

Add + 4 Add + 5 Add + 6 Add + 7

Add + a Add + 9 Add + 10 Add + 11

Add + 12 Add + 13 Add + 14 Add + 15

Ch A External/Status Change Ch A Receive Character Available Ch A Special Receive Condition Ch A Command Executed

Ch B External/Status Change Ch B Receive Character Available Ch B Special Receive Condition Ch B Command Executed

Ch C External/Status Change Ch C Receive Character Available Ch C Special Receive Condition Ch C Command Executed

Ch D External/Status Change Ch D Receive Character Available Ch D Special Receive Condition Ch D Command Executed

3.2.3 Serial Cammri.cations Channels

The four asynchronous communications channels are serviced by two USARTs which support only primary RS-232C signals. Secondary signals and the time options of the RS-232C are not supported. Communication may be single channel full­duplex or single channel half-duplex.

3.2.3.1 Message Format

A typical 7-bit asynchronous message format consists of one start bit, seven data bits, one parity bit and one or two stop bits. (An a-bit message format may also be called for.) The following discussion of the characteristics of the message format assumes the active signal condition to be the mark state (-3 to -25 volts):

o start Bit - Its transition to mark state notifies the 4-Way receiver of an incoming message; also initiates a clock circuit to provide latching pulses during the expected data bit intervals.

o Data Bits - Data bits have standard TIL values: 0.0 to +0.4 VOC equals logic low; +2.4 VOC to Vcc equals logic high.

o Parity Bit - Provided for error checking, it rests in the quiescent (0) state or the mark state (1), depending upon whether the accumulated l's in the data bits are odd or even. The parity bit is calculated in both the sender and receiver and the results for each data word are compared to ensure that the actual and expected data-bit values match.

3-7 M8155A

o stqp Bit(s) - The stop bit momentarily transits from its normal high state to its mark state at the end of each message unit, causing the receiving circuits to be reset in preparation for the next start bit. During reception, the start and stop bits are stripped away, leaving only the working data for CPU interaction.

3.2.3.2 Signal Loading

Each communications channel (gate) uses one 1489 line receiver for input load­ing and one 1488 line driver for output. The- four channels corrmunicate with the connected equipment via a 9-pin connector which has the characteristics specified in Table 3-1. An open DSR or nco pin is biased to be in the active (mark) state so that communication will not be blocked by non-~lemented Slg­nals. (The biasing can be rennved or Irodified by manipulating the jumper block for the port in accordance with the information shown in the logic diagram in Section 7 of this manual.) The device type data suppl ied by the CMB software informs the 4-Way what equipnent is connected, and thus what protocol is needed; the 4-Way masks out the undesired signals when reading from the see status Registers.

Table 3-1. Asynchronous camunication Connector Data

PIN t SIGNAL mNJ[~/mIVER RF.Ml\RKS

1 TxD 1488 (Driver) Transmitted Data 2 RxD 1489 (Receiver) Received Data 3 RTS 1488 (Driver) Request to Send 4 crs 1489 (Receiver) Clear to Send 5 DSR 1489 (Receiver) Data Set Ready 6 SG Signal Ground 7 nco 1489 (Receiver) Data Carrier Detect 8 9 JJrR 1488 (Driver) Data Terminal Ready

3.2.4 4-way Asynchronous Protocol

This discussion of 4-Way asynchronous protocol assumes that the data sender (or data sourcer) is called Data Set, and the data receiver (or data sink) is called Data Terminal.

3.2.4.1 Data Line Format

A character or message unit is defined by a start bit and one or two stop bits. Traditionally, one stop bit is used when the baud rate is higher than 110 baud; two stop bits are used when the baud rate is lower than 150 baud. One-and-a-half stop bits are also possible in some terminals. Character length can be programmed from 5 to 8 bits, excluding the parity bit, and parity can be programmed as odd, even or no parity.

M8155A 3-8

3.2.4.2 Buffer Flow Control Methods

If the Data Tenninal has slower throughput than its input, the Data Terminal buffer may become full. One of three flow control methods is used to prevent buffer overflow, as follows:

o X~/X~FF Protocol o Data Tenninal Ready Control o Data Set Ready Control

X~/X-{)FF Protocol - Two otherwise unused ASCII codes are embedded in the output message by the Data Tenninal to announce the full/empty condition of its receive buffer. The codes are software configurable for each fX)rt, but have default values of 011H and 091H for X-GN, and 013H and 093H for X-GFF. The CMB can also send an X~N to the 4-Way by issuing a port Reset command while the fX)rt is in an X-GFF condition. When under the control of the Data Terminal, the protocol gives the following instructions to the CMB: 1) When X-GFF is received, halt transmission; 2) Wait for X~N code; 3) Continue transmission until X ~FF code is received.

Data Tenni.nal Ready Control - When on-line to the CMB, the Data Tenninal can control the input to its buffer by toggling the Data Terminal Ready (DTR) line as follows: DTR in the mark state means buffer is full and transmission is to be hal ted; otherwise, continue transmission.

Data Set Ready Control - This method is used when the Data Tenninal speed ex­ceeds that of the data source, or when the tenninal is unable to receive any character within certain time intervals after a carriage return or line feed is received. In this event, the Data Set Ready (DSR) line is held in a mark state and the Data Set controls the transmission speed. If necessary, null codes are inserted between characters to slow the transmission speed. If this method is used, the data sink software should reject the null codes before storing the received data.

3.2.4.3 RS-232C Protocol Used h¥ the 4~y

Table 3-2 identifies all the standard RS-232C signals that are available; those that are involved in 4-Way protocol are discussed in the paragraphs that follow.

•

3-9 M8155A

Table 3-2. RS-232C Signals used by the 4~y

st.aOOard RS-232C InplE!DeDtation

M AS CE CD CC EA DA

DB

DD CA CB CF CG CH CI SEA SBB SCB SCF

Protective Ground Signal Ground Ring Indicator Data Tenninal Ready Data Set Ready Transmitted Data Transmitter Signal Element Timing

(DTE Source) Transmitter Signal Element Timing

(DCE Source) Receiver Signal Element Timing Request to Send Clear to Send Data Carrier Detect Signal Quality Detector Data Signal Rate Selector (IJrE Source) Data Signal Rate Selector (DCE Source) Secondary Transmitted Data Secondary Received Data Secondary Clear to Send Secondary Received Line Signal Detector

4-way

NO YES NO YES YES YES

NO

NO NO YES YES YES NO NO NO NO NO NO NO

Transmitted Data (TXD) - Signals on this circuit are generated by the IJrE and are transferred to the 4-Way USART for transmission to the host. The signal is held in the marking state during intervals between characters and at all times when no data is being transmitted.

Received Data (RxD) - Signals on this circuit are generated by the host in re5pJnse to data signals received from the 4-way USART. This line is held in the marking state during intervals between characters and at all times when no data is being received (DCD off).

On a half-duplex channel, the Received Data line is held in the marking state when RTS is asserted and for a brief interval following the ON (~sserted) to OFF transition of RTS to allow transmission to be completed.

Data carrier Detect UXD) - Data Carrier Detect is generated by the host to qualify the Received Data line signal. Based on the protocol, if Auto Enable r.bde is not selected, data can still be received when DCD is in the mark state (FALSE). The 4-Way software decides whether data is acceptable or not.

Request to SeOO (RrS)/Clear to Send (c.rs) - Request to Send (RTS) and Clear to Send (CTS) are meaningful when a half-duplex Irodem is involved. RTS requests a communication channel from the host; CTS from the host acknowledges the re­quest. In half-duplex communication, the 4-way must send RTS and the host ac­knowledge with CTS before each character can be transmitted. The Transmitter Shift Register Empty signal in the SCC status Register is used to ensure that the last stop bit is fully transmitted before RTS is released.

M8155A 3-10

Data Set Ready (£Sl) ...:. Data Set Ready is sent to the 4-way by the rrodem to in­dicate its on-line condition. DSR is also frequently used to indicate that a connected DTE element is in the proper condition to receive data (on-line, with receiving buffer not yet full). DSR is placed at the External Sync pin of the SCC and can generate an External status Interrupt on any transition. The DSR bits can also be read from the 4-Way status Register at any time.

Data Temri.nal Ready (UlIU - Data Terminal Ready is set to its marking state (FALSE) to indicate that the 4-Way is on-line and ready to receive data (receive buffer not yet full).

3.3 4-wAY INITIALIZATIOO

The 4~y is initialized by a Master Reset or a Power On Reset (POR). The condition causes the 4-way to initiate a Self-Test routine during which several power-on (or reset) tests are performed, as discussed in the para­graphs that follow. Successful completion of the Self-Tests is signalled by illuminating the green LED light on the PCBA.

3.3.1 Initialization Criteria

On a cold-start initialization, the LED is OFF. It is turned ON if and when the Self-Tests are successful. On a warm-start initialization (Software Reset Command), the LED is ON and is momentarily toggled OFF as an indication that all hardware has been initialized. If the LED remains OFF, a Fatal Error has occurred and the 4~y is inoperable and remains so until the Fatal Error is fixed.

3.3.2 IDt Checkstn

As the 4-way enters the PROM Checksum routine, the LED is set to OFF. All PRCM locations are added together in rrodulo 256 and compared to' an expected sum stored in the PROM. If the checksum fails, a Fatal Error Code is genera­ted.

3.3.3 Memory Test

A series of simple data patterns are run through 4-way memory to verify the ability of each memory cell to hold both ones and zeroes.

3.3.4 sec Wop Test

All four channels are loop-tested in asynchronous mode to verify interrupt, data continuity, and basic timing. During the test, the serial lines are dis­abled to ensure that devices on the line are not affected by the testing. All parallel-to-serial logic on the 4-Way is tested except the driver/- receivers of the serial interface.

3-11 M8155A

3.3.5 Error Reporting

During Self-Test, the Self-Test bit in the Transmit Status Register is set and remains set for the duration of the tests. Should a test fail, an error code is placed in the Receive Data Register to indicate which test failed. If the test is critical to the operation of the 4-way, the Fatal Error bit is set and the 4~y will go off-line. The Error Code bits for the Receive Data Register have the following significance when set during Self-Test mode:

Bit O(ISB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

3.3.6 Reset Routine

RAM Failure Always Zero Always Zero Always Zero see Port A Failure sec Port B Failure sec Port C Failure SCC Port D Failure

Upon successful completion of Self-Test (no errors), the LED is set to ON and control is passed to the Reset routine, which proceeds as follows:

1. The asynchronous parameters of the sec are set as follows: 1 start bit, 7 data bits, odd parity, one stop bit, 9600 baud.

2. Bits 2 and 3 are set in the status Register to indicate to the CMB that the Base Interrupt Vector and the Base Command Block Address have not been set for the 4-Way. The CMB then writes the least significant word of the Command Block Address to the 4-way Instruc­tion Register.

3. The CMB monitors the BUSY flag (bit 0) of the 4-way status Regis­ter. Bit 0 is set and remains set until the Z80A has transferred the address to memory and is ready for the next address.

4. The CMB, upon sensing the reset of Bit 0, writes the most Slg­nificant byte of the Command Block to the lower byte of the host data bus.

5. The process 1S repeated for the Base Interrupt Vector.

6. The 4-Way enters the Executive Program, in which data is passed along to the appropriate devices connected to the 4-way.

M8155A 3-12

3.4 IEl'AILED ~ DESCRIPrICE

In this section, the operating characteristics of the electronic and logical elements of the 4-Way Controller are described 1n terms of their functional groupings, as follows:

o DMA Interface Circuits (paragraph 3.4.1) o Communications Interface Circuits (paragraph 3.4.2) o Central Processor Logic (paragraph }.4.3) o Read/Write Registers (paragraph 3.4.4) o Prograrrmable Baud Rate Generator (paragraph 3.4.5) o status Register (3.4.6 ) o Instruction Register (paragraph 3.4.7) o Clock Circuitry (paragraph 3.4.8)

3.4.1 rM\ Interface Circuits

The DMA interface (see sheet 5 of the Logic Diagram) is activated when the Z80A asserts SETBREQ-, which forces the Bus Request signal BR- onto the EBUS, and into the DMAI/Interrupt Arbitration portion of the DMA Interface. At this time REQ2+ is generated to activate the arbitration process. The settings of dip switches 1 thru 6 (AFSA-l to ASSA-3) determine the priority level the 4-Way will use in any DMA or Interrupt arbitration. The S157, S38 and S64 chips determine if the arbitration levels match.

If the first stage of arbitration is correct, PG2- is set; if the second stage of arbitration matches, MYTORN- is asserted TRUE. If AS+, IACK+ and ~CK+ are all inactive (FALSE) the DMA cycle commences with the next GO+ strobe. Several strobes are created:

a. !II;ACK+, which becomes :EG\CK- (Bus Grant Acknowledge signal on EBUS)

b. I~-, which enables·the address drivers to place the pre-loaded DMA address on the EBUS.

c. START+, which creates IJtWD+ to keep the Drive Bus Signal OOBOS­alive until the DMA cycle is completed.

To terminate the DMA cycle, one of two events occur, either of which causes the ~p- and WHOA- signals to turn off the DMA cycle: ~+ (Data Transfer Acknow ledge) or amR+ (Bus Error).

The following are the only valid arbitration switch settings for the 4-Way:

Board

1 2 3 4

AFSAl

o o o o

1 1 1 1

1 1 1 1

3-13

1 o o o

1 1 o o

1 1 1 o

M8155A

3.4.2 camuni.cations Interface Circuits

3.4.2.1 Serial camuni.cati9flS Controllers (SCCs)

All RS-232C communications are handled by the SCC chips. These chips handle the protocol, baud rate, and characteristics of the input and output serial

. data. Refer to the Zilog 8530 Technical Manual for de~ils of the SCCs.

3.4.2.2 sec Interrupt. h::knowledge

The timing arrangements of the SCCs require that a Z80A wait state be genera­ted to allow the scc to complete daisy chain prioritization during an Inter­rupt Acknowledge cycle. During an Interrupt Acknowledge cycle, ZINTACK­asserts Read strobe READ- to SCCs and issues wait strobe ~- to the Z80A.

3.4.3 central Processor Wgic

The Z80A-CPU Microprocessor is the central processing element in the 4-way Controller. The operation of the Z80A-CPU is described in full detail in the Zilog Z80A-CPU Technical Manual (not supplied).

3.4.3.1 ReadlWrite Systan Me!oory

The Read/Write System Metoory contains interface logic to the Z80A bus, address buffering and timing logic, and a 2K x 8 Type 6116 RAM IC. The memory 1S

divided into 9 sections, one 256-byte section for the Z80A scratchpad, four 192-byte FIFO sections for transmitted data, and four 256-byte sections for received-data buffering. The following RAM memory map shows the starting ad­dress for each of the 9 sections:

Address 2000H - Z80A Scratchpad, 256 Bytes Address 2100H - Channel A FIFO, 192 Bytes Address 21COH - Channel B FIFO, 192 Bytes Address 2280H - Channel C FIFO, 192 Bytes Address 2340B - Channel D FIFO, 192 Bytes Address 2400H - Channel A Receive Buffer, 256 Bytes Address 2500B - Channel B Receive Buffer, 256 Bytes Address 2600B - Channel C Receive Buffer, 256 Bytes Address 2700H - Channel D Receive Buffer, 256 Bytes

M8155A 3-14

3.4.3.2 Read Only Mem>ry (RCM)

The 4-Way ROM consists of a Type 2764 EPROM, which provides 8k x 8 bits of microprocessor firmware storage. The following functions are provided within the ROM address range of OOOOH to 2000H:

Self-Test Routine - The Self-Test Routine is activated upon initial power up or Power On Reset (POR). The ROM, RAM, SCC Channels, and Il1A logic are all tested, and if anyone should fail, a Fatal Error is generated an~ sent to the CMB. The 4-Way becomes inoperative and remains so until the error is cor­rected. If no Fatal Error is detected, 4-Way control is passed on to the Reset function.

Reset Routine - The Reset function causes the 4-Way to begin executing the routine located at address 066H. Reset initializes the SCCs with a default configuration and then allows the CMB to initialize the 4-way Command Block Address and Interrupt Vector before passing control to the Executive Routine.

Executive Routine - This resident program is stored 1n an 8K x 8 EPROM and 2K x 8 of RAM to provide initial 4-way control after a Reset in the following manner:

o The Executive monitors the Instruction Register and reports to the OMS whether a Data Packet has been prepared for transmission.

o The Executive handles all data transfers between the 4-way and the OMS and between the 4-way and each of the four asynchronous ports.

3.4.4 ReadlWrite Registers

The center of data activity in the 4-Way revolves around the internal Read/ Write Registers, the programming of which provides the SCC with a functional "personality." This programming is controlled from the Z80A which uses the 8-bit address bus to control an address decoder. Through these decoders the register values can be assigned before or during program sequencing to determine how each SCC will establish a given communication protocol. All communication modes are established by the bit values of the Write Registers. As data is received or transmitted, the bit values of the Read Register change. These changed values may promote software action or internal hardware action which result in further Read Register changes.

The register set for each channel includes 16 Write Registers and 9 Read Reg­isters. Ten Write Registers are used for control, two for sync character gen­eration, and two for baud rate generation. The two remaining Write Registers are shared by both channels: one for processing Interrupt Vectors and one as Master Interrupt Control. Of the nine Read Registers, four indicate status functions, two are used by the Baud Rate Generator, one is for the Interrupt Vector, one for the Receive Buffer, and one is for reading the Interrupt Pend­ing bits. The assigned functions for each Read/Write Register are listed and described in Table 3-3.

3-15 M8155A

Table 3-3. Functions Assigned to Each ReadlWrite Register

RFAD REX;ISrER FDNCrIONS

RRO

RR1

RR2

RR3

RR8

RR10

RR12

RR13

RR15

M8155A

Transmit/receive buffer status; external status

Special receive condition status; error conditions

Modified (Channel B only) Interrupt Vector; unmod­ified vector (Channel A only)

Interrupt Pending bits (Channel A only)

Receive buffer

Miscellaneous status parameters

Lower byte of baud rate generator time constant

Upper byte of baud rate generator time constant

External/status inter-rupt control information

WRO

WR1

WR2

WR3

Command Register pointers; CRC initialization; commands for various modes

Interrupt conditions; data transfer modes

Interrupt Vector (access through either channel)

Receive/control parameters; No. bits/character

WR4 Transmit/receive miscellaneous parameters and modes

WR5 Transmit parameters and control

WR6 Sync character or SDLC address field (1st byte)

WR7 Sync character or SDLC flag (2nd byte)

WR8 Transmit buffer

WR9 Master Interrupt Control and Reset (accessed thru either channel)

WR10

WR11

WR12

WR13

WR14

WR15

3-16

Miscellaneous transmitter/ receiver control bits

Clock mode control

Lower byte of baud rate generator time constant

Upper byte of baud rate generator time constant

Miscellaneous control bits

External/status interrupt control information

3.4.5 Bam Rate Progranming

Each channel in the 4-Way contains a Baud Rate Generator which consists of a 16-bit down counter (two 8-bit time-constant registers), and a square-wave outplt flip flop. The time constant can be changed at any time to program a new baud rate, under the following conditions: .

o The new value will take effect only up:m the next load of the counter.

o No attempt is made to synchronize the new time constant with the clock used to drive the generator.

o When the time constant is to be changed, the Baud Rate Generator is stopped by writing an enable bit inWR14 to ensure that the correct time constant is loaded.

Table 3-4 shows the divisors needed to produce the time constant needed to generate a x16 clock for the various baud rates. The divisor is calculated ln accordance with the formula: Divisor = [1/(2 * BR* 1/Freq)] - 2, where Freq = 3.6864 MHz.

Table 3-4. Time Constant Divisors Required for Various Bam Rates

DESIRED B.2\UD RATE

50 75

150 300 600

1200 1800 2400 3600 4800 7200 9600

19200 38400

DIVI&Jl RBJUIRED F<E X16 CIDCK

2.302 1,534

766 382 190

94 62 46 30 22 14 10

4 1

8FE 5FE 2FE 17E

BE 5E 3E 2E 1E 16

E A 4 1

DESIRED VS AcruAL PmcENl' ERRCE OF DIFFERENCE

Percent Error = 100 * [(Desired BR - Actual BR)/Desired BR]

3.4.6 status Register

The status Register contains information on the readiness of the· 4-Way to receive data, which is sent to the OMS in response to the Transmit status Reg­ister command, via the lower 8 bits of the 4-Way to CMB Data Bus. The CMB in­terprets the status Register bit pattern differently, depending upon whether Self-Test Bit 1 is set (Self-Test Mode) or not set (Normal Mode).

3-17 M8155A

The significance of the bits (when set) for Normal Mode and Self-Test Mode are as follows:

Normal M:xie

Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB)

Self-Test ~

Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB)

Busy (4-Way not ready) Self-Test off (must be zero) Conmand Block Address not received Base Interrupt Vector not received DSR Channel A (negative TRUE) DSR Channel B ( negative TRUE) DSR Channel C (negative TRUE) DSR Channel D (negative TRUE)

Fatal Error (4-Way inoperative) Self-Test in progress (must be set) RCM Failure (Fatal Error) DMA Bus Failure (Fatal Error) DSR Channel A (negative TRUE) DSR Channel B (negative TRUE) DSR Channel C (negative TRUE) DSR Channel D (negative TRUE)

3.4. 7 . Instruction Register

The 4-Way Instruction Register is accessed by the OMS after a Data Packet has been prepared and a Conmand Block is ready to be read. The corrmand is: D(x)AOOOOH, where (x) is the 4-Way Controller ID. The following is the In­struction Register format:

Bit 0 (LSB) Bit 1 Bit 2 Bit 3

Bit 4 Bit 5

Bit 6

Bit 7

M8155A

Port A Conmand Block Ready (when set) Port B Conmand Block Ready (when set) Port C Corrmand Block Ready (when set) Port D Corrmand Block Ready (when set) Port pp Reset/X-oN Reset (bits 4 and 5):

pp = 00 - Port A 01 - Port B 10 - Port C 11 - Port D

Port Reset Select: o = No Reset 1 = Reset Port pp

Interrupt Inhibit

3-18

3.4.8 Clock Circuitry

A clock buffer is provided which supplies the' following clock frequencies:

System/Bus I/O Clock

The System/Bus I/O Clock is the 8-MHz square wave I/O clock from the CMB. The 8-MHz clock is buffered in the 4-Way and used to develop I/O timing. A 4-MHz clock is derived from the 8-MHz clock for use by the Z80A-CPU.

Bald Rate Clock

The Baud Rate Clock is a 3.6864 MHz square wave PCLK signal from the CMB which is used to generate the various 4-Way baud rates.

3-19 M8155A

M8155A 3-20

4.1 PREVENl'IVE MAINl'ENANCE

Maintenance of the 4-way PCBA consists of general cleaning, which should be accomplished along with scheduled maintenance on the host system. Cleaning of the 4-way is done in the following manner:

Ib rx:>t use abrasive cleaners aId chemical cleaning agents that contain acetone, toluene, xylene, or benzene. These cleaners may cause equipnent damage that requires major repair. ESD sensitivity requires proper handling of boards.

1. Use a soft bristle brush to clean dust from the surface of the printed circuit board.

2. Use a lint-free cloth dampened with a solution of 90 percent isopropyl alcohol to clean non-electrical surfaces.

4.2 <DmFrI'IVE MAINl'ENANCE

The paragraphs that follow describe power-on, hard reset, soft. reset and the diagnostic tests available for the 4-way PCBAs. These tests are included to insure the integrity of the 4-way hardware and to isolate a hardware problem if one exists. Also included are descriptions of switch settings and cable connections for adding a 4-way PCBA to. a system.

4.3 ~-UP INITIALIZATIOO AND SELF-TFSl'

4.3.1 Power-Up or Hard Reset Self-Tests

Upon power-up or a hard reset, the 4-way firmware performs a low-level hardware functionality checkout which 1S crucial to correct operation of the controller.

Following either reset, the 4~ay turns on the on board led, sets the proper status in the status bytes and turns control over to the 4-way firmware EXEC for further use of the board.

At any time during these self-test, if an error occurs the firmware goes into looping on that error to signal that error to the CMB and to lock up the 4-way so that it cannot accept any commands.

4-1 M8155A

The Hard Reset self-test is made up of the following tests:

a. Board initial ization. b. RCM Test. c. RAM Test. d. see Test. e • r:MA. Test.

4.3.2 Soft Reset Self-Test

In addition to the hard reset, the 4~ay firmware can perform a 'soft-reset' which is accessible via software. This s~ft reset performs a subset of the hard reset self-tests:

a. Board initialization. b. Zero-out RAM. c. Reset see chips. d. Initialize firmware pointers.

4.4 FOUR-wAY D~CS

For diagnostic purposes there exist tests on the various diagnostic media which have varying levels of complexity to aid in the diagnosis of a 4-way failure and its isolation. The diagnostic media include diagnostic MTS tape and "MeS cartridges for both the MAl 2000/3000, diagnostic floppy disks for the MAl 2000 and on the MAl 3000 there is a diagnostic partition on the Winchester disk. The set of diagnostic tests for the 4~ay boards includes:

a. System power-on self-test. b. 4-way logic test (FWAY). c. 4-way function select test ( FWFS) • d. System Interaction Test (SIT).

4.4.1 System Pawer-on Self-Tests

The system power-on self-tests exist in the CMB boot PROMs for the MAl 2000 and in the Micro-Diagnostic System (MOS) for the MAl 3000. These tests check the 4~ay board self-test status for correct operation of the 4-way firmware self-test. These tests are low-level and only to insure minimal usage of the ports on the 4-way. For further information please see the MDS Users's Guide document #011526.

M8155A 4-2

4.4.2 Four-May lDgic Test (FWAY)

The 4~ay logic test (FWAY) is an off-line functionality diagnostic which is to be used when a 4-way PCB.Z\ is suspected of having hardware failures or to insure 4~ay hardware integrity. This requires taking the system off-line and booting the Diagnostic Exec from one of the diagnostic media. (See MAl 2000/3000 Diagnostic Exec Specification, MBF #011489 for more details.) Once the Exec is loaded the FWAY test can be loaded. The FWAY test is designed to be a load-and-run type of test requiring no intervention by the user unless specified and even then the user has to select the Manual option. The FWAY test runs the 4~ay PCBAs which were found on the system through a series of tests with increasing complexity until the entire functionality of the board has been exercised. At any point in the tests if an error is found an error message is displayed to the user on the screen along with pertinent informa­tion concerning the error. For more details see MAl 2000/3000 4-Way Logic Test Specification, #011177.

4.4.3 Four-May Fur¥:±ion Select Test (EWFS)

The 4~ay Function Select test (FWFS) is also an off-line functionality diag­nostic. The FWFS test is used to further isolate problems that may have been found by the FWAY or other tests. The FWFS test al so requires that the system be taken off-line and that the Diagnostic Exec be booted. Whereas the FWAY test was a load-and-run type test the FWFS requires that the user set up the test parameters for each board and each specific test. For more details see MAl 2000/3000 4-Way Function Select Test Specification, #011178.

4.4.4 System Interaction Test (SIT)

The System Interaction Test (SIT) fills the remalnlng gap in diagnosing the system hardware. SIT puts all devices specified into a multi-user test en­vironment and points out errors which occur from bus contention and interrupt arbitration. As in FWAY and FWFS, SIT also requires that the system be taken off-line and that the Diagnostic Exec be booted. Also as in FWAY, SIT is a load-and-run type of test. For more details see System Interaction Test Spec­ification, #011310.

4.4 BARIH\RE cnwIGORATIOO

The switch settings for the 4-way board are as follows:

Board #1 Board #2 Board #3 Board #4

r:MA Arbitration

o 1 1 111 Oil 011 Oil 0 0 1 011 000

4-3

Board Address

101 0 1 011 1 1 0 0 1 1 0 1

M8155A

Where 0 represents the ON position of the switch and 1 represents the OFF position of the switch.

The cable connectors on the board are numbered from 0 to 3 where the connector number increases from left to right toward the system power supply.

M8155A

MIrES

4-5 M8155A

M8155A 4-6

Removal/replacement instructions for the 4~ay controller PCBA are contained in M8079, MAl 2000 Service Manual and M8l08, MAl 3009 Service Manual.

5-1 M8155A

M8155A 5-2

SEX:tIOO 6

ILLUSTRATED PARI'S LIsr

6.1 IN1KDUCTICfi

This section provides parts information for the 4-way Controller PCBA. Figure 6-1 illustrates the 4~y PCBA (PIN 903390) and Table 6-1 lists the parts of the 4-way Controller PCBA.

6-1 M8155A

Figure 6-1. 4~y Controller PCBA (PIN 903390)

M8155A 6-2

Table 6-1. 4-way Controller PCBA Parts List

REF m. PART m. DE3XIPrIOO REFERENCE

0001 904943-001 PCBA. 4-WAY CONTROLLER * 0003 762022-003 lABEL TAB • 375X1. 250 YEL * 0005 101613 IC MC1488L QUAD LINE DRIVER 4C,5C,6C 0006 101612 IC MC1489L QUAD LINE RECEIVER 2B,3B,3C,5B,

6B 0007 101315 IC 74S00 QUAD 2 INPUT POS NAND GATE 4D 0008 101655 IC 74S02 POS-NOR GATE TOTEM-POLE 2C,3E 0009 101541 IC 74S04 INVERTER HEX 2H,4G,4K 0010 101615 IC 74S08 QUAD 2 INPUT FOS AND GATE 4F,4N,4P 0011 101776 IC 74LS11 TRIPLE 3-INPUT POS AND GATE 4E 0012 101713 IC 74LS30 8 IN NAND 3J 0013 101625 IC 74S32 QUAD 2 INPUT POSITIVE-QR GATE 4L 0014 101627 IC SN74S38 QUAD 2 INPT POS NAND BUFFER 1F,lG 0015 101740 IC 74LS51 DUAL 2-~DE 2-IN-&IOR-INVERT 3F 0016 101628 IC 74S64 4-2-3-2 INPUT &IOR INV GATE 1E 0017 101629 IC SN74S74 DUAL D-TYPE FLIP/FDOP 2D,2E 0018 101741 IC 74LS74 DUAL D-TYPE POS EDG-TRIG F/F 4H, 4R, 6R 0019 101742 IC 74LS85 4 BIT MAGNITUDE CONPARATOR 1D 0020 101630 IC 74S112 DUAL J-K EDGE TRIG FLIP/FDOP 2F,2G 0021 101719 IC 74LS138 3-8 LINE DECODER/DEMLTIPLXR 2R,3R,5N,5P 0022 161086-001 IC 74LS139 DECODER/DEMLTIPLXR 5M 0023 101633 IC SN74S157 QUAD 2-1LINEDATA SLCT/MUX 1C 0024 161009 IC 74S240 OCTAL BUFFER 3-STATE TTL 1H,1J,2J 0025 161064-001 IC 74LS240 BUFF LINE DR 3-ST OCTAL 1L,lM,lN,lP,

1R 0026 161066-001 IC 74LS245 OCTAL BUS XCVR 5L 0027 101637 IC SN74S260 DUAL 5 INPUT POS-NOR GATE 3H 0028 161023 IC 74LS273 OCTAL D-TYPE FLIP/FDOP 2M, 2N, 2P, 3G 0029 161049-001 IC 74279 QUAD S-R lATCH 5R 0030 161013 IC 74LS373 OCTAL D-TYPE lATCH 3-STATE 2K,3N 0031 161065-001 IC 74LS374 OCTAL REGISTER D-TYPE F/F 2L,3K,3L,3M 0032 161111-001 IC 74LS640 OCTAL BUS TRANS INV 3-STATE 1K 0033 161108-001 IC RAM STATIC 2KX8 CMOS 200NS 5J 0034 165047-042 IC 2764 8KX8-4-WAY CONTROLLER FIRMWARE 6J 0035 162002-002 IC Z80A 8 BIT MICRO-P 6N 0036 162031-001 IC SERIAL CCM1UNICATIONS CONTROLLER 5F,6F 0041 111000-043 RES CARBON FIIM .25W 5% 1000HM R4,5 0042 119000-003 RES N'IWK DIP 16 PIN 15 RES 1. OK OHM R1(4J) 0043 119000-006 RES N'IWK DIP 16 PIN 15 RES 3. 9K OHM R2 (4B) ,R3 (1B) 0046 104008-004 CAP CERAMITC X7R DIP 220PF 5% 50V C7,8 0047 104010-001 CAP CERAMITC Z5U AXL .1UF +80 -20% 50V C9-54 0048 102000-012 CAP SOLID TANTALUM 33UF 20% 10V Cl-4 0049 101127 CAP SOLID TANTALUM AXIAL 47UF 10% 20V C5,6 0052 152003-001 DIODE LIGHT EMITTING DS1 0054 331014-007 SWITCH DIP SLIDE SPST AUTOINSERT 10SEC S1(lA) 0055 .325005-003 SOCKET IC DIP 4-LFAF CONT GOLD 14 POS (2B,3B,3C,

4C,58,5c,6B, 6C)

6-3 M8155A

Table 6-1. 4-way Controller J?CRl'\ Parts List (cont'd)

REF ID. " PART ID. DESCRIPl'ICE REFERENCE

0056 325005-007 8CX:KET IC DIP 4-LEAF CONT GOLD 28 POS (6J) 0057 325005-010 scx:::KET IC DIP 4-LEAF CONT GOLD 40 POS (5F,6F,6N) 0059 3000.32-003 CONN HDR DBL ROW .100~S .025SQ 4 POS PG1l-4" 0060 300032-002 CONN HDR DBL ROW .100ers .025SQ 6 POS PG1l-4 0061 325033-001 JUMPER 0.025 SQ 0.100 CENTERS GOLD PL (PG1l-4) 0063 300091-001 CONN D FML RT /ANG PC Mr MrL FACE 9POS Pl-4 0064 208000-001 RIVET BLIND • 116DX .188L ALUM (Pl-4) 0065 907402-001 CONNECTOR PLATE 4WAY CONTROLLER * 0066 310006-002 SCREWLOCK FML/ML 4-40 D CONN STD (Pl-4) 0068 300092-001 CONN DIN FML 3X32 PRESS-FIT 64 POS A&C J1,2 0069 310019-001 CONN HOUSING/GUIDE DIN 3X32 .100ers ML (J1,2) 0073 907388-001 EJECTOR EURO-DIN CONN STACK * 0074 907769-001 LATCH EURO-DIN CONNECI'OR STACK * 0075 907985-001 CATCH PCBA STACK CONTROLLERS * 0076 214027-001 FASTENER"PUSH-oN .312 DIA STUD * 0077 211001-002 WASHER SPLIT LOCK STEEL 04 *

M8155A 6-4

6-5 M8155A

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CK3.68M

APPENDIX A

LIST OF IffiIC D~ ~CS

This signal enables the 4-Way's internal status onto the Z-80A's data bus.

This signal indicates that the 4-way has been addressed.

These signals are the EBUS address lines.

This signal indicates that 'the 4-way has been addressed and enables the slave mode registers to be accessed.

These signals are the switch selected first stage arbitration level for DMA and Interrupt arbitration.

These signals are the switch selected second stage arbitration level for DMA and Interrupt arbitration.

This is the EBUS Address strobe which indicates that the ad­dress currently on the EBUS is valid.

This is the EBUS generated Bus Error signal which indicates that an operation on the EBUS was unsuccessful.

This signal is the Bus Grant Acknowledge that is generated by the requesting device to acknowledge being given control of the bus.

This is the Bus Grant signal generated by the CMB to glve con­trol of the bus to the requesting device.

This signal is a slave mode command to place the 4-way's Board status on the EBUS.

These EBUS signals determine the priority arbitratio~ during a DMA or Interrupt.

This signal is the EBUS Bus Request signal that 1S generated by the device requesting control of the bus.

This signal is generated by the Z-80A to inform the CMB that the 4-way is currently unable to receive any new commands from the CMB.

This 1S the 8 MHz system clock.

This is the 3.6864 MHz clock required for the see chips to gen­erate the required baud rates.

A-I M8155A

CK4M

CLRBUSY

C1'SA - 0

DATOO'l'EN

DBOO - OB1S

DCDA - 0

mBUS

OORA - 0

M81S5A

This is the 4 MHz clcx::k, derived from the system clock, re­quired for the Z-80A.

This is the split baud rate clock, generated by the CMB, re­quired for uses when the serial transmit and receive clocks are different.

This signal clears the BUSY flag given to the OMS.

This signal clears the Command Receives flip-flop that informs the Z-80A that a cammand was received.

This signal turns off the LED.

This signal informs the CMB that the base command block address is required by the 4-way.

This is the status bit that the Z-80A reads to determine if a command was received.

;

This signal latches the new command and sets a flip-flop that will inform the Z-80A that a command has been received.

These are the Clear To Send signals required for each of the RS232C ports.

This signal informs the transceiver that data 1S being sent to the CMB.

This signal latches the data being brought onto the 4-Way from the CMB.

This enables the lower. 8 bits of the data brought 1n from the CMB onto the Z-80A data bus.

This line informs the Z-80A that data has been latched for the CMB and it has not yet been used.

This signal latches the data on the Z-80A data bus prl0r to sending it to the EBUS.

This enables the data onto the EBUS from the 4-Way.

This is the EBUS Data Bus.

These are the Data carrier Detects required for each RS232C serial port.

This signal starts the DMA cycle after completing arbitration.

This signal activates the data drivers during a DMA cycle.

These are the Data Set Ready's required for each RS232C post.

A-2

lJIRA - D

00

IACK

IBR

IINT4

This is the Data Transfer Acknowledge signal. This signal is generated by the slave device to acknowledge being addressed by the master.

These are the Data Terminal Ready's required for each RS232C p::>rt •

This places the data to be sent to the CMB on the EBUS.

This signal latches the data or command being 'sent to the 4-Way from the CMB.

This enables the data onto the EBUS as a slave mode read opera­tion.

This places the Interrupt Vector on the EBUS data lines for the CMB to read. It also terminates an interrupt operation and resets the interrupt request.

This signal is used as a timang signal for the DMA circuit at the start of the cycle.

This signal indicates that both stages of the arbitration passed.

This signal informs the DMA circuitry that the proper condi­tions exist for a DMA to take place.

This signal informs the interrupt circuitry that the proper conditions exist for an interrupt acknowledge.

This signal informs the arbitration logic that a level 4 inter­rupt has been acknowledged and starts the arbitration sequence to determine if this board is being acknowledged.

This signal is sent by the CMB on the EBUS to acknowledge an interrupt.

This signal is the Internal Bus Grant Acknowledge which informs the address drivers to place the DMA address on the EBUS. This signal also drives BGACK.

This signal is the Internal Bus Request that will drive the BR signal on the EBUS and will start the DMA cycle.

This is the Internal Data Transfer Acknowledge which informs the CMB that the 4-Way has acknowledged a slave mode request.

This is the Internal Interrupt request that starts the inter­rupt cycle and drives the interrupt line for the 4-Way.

This is the delayed read strobe required by the SCC's during an interrupt acknowledge.

A-3 M8155A

lCEQ

T.FJX)FF

PRIOl - 3

RFAD

RBJl - 2

RESEt

RIA - D

RCJtC;

RSTIBR

RSTINIR

RTSA - D

RxDA - D

SCC01CE SCC02CE

M8155A

This 1S the Z-80A's IIO Request strobe.

This strobe allows the Z-80A to load the lower 8 bits of the DMA address prior to a DMA cycle.

This strobe allows the Z-80A to load the middle 8 bits of the DMA address prior to a DMA cycle.

This strobe allows the Z-80A to load the upper bits of the OMS address prior to a DMA cycle.

This strobe allows the Z-80A to load the interrupt vector prior to an interrupt cycle.

This strobe turns off the LED.

This strobe turns on the LED.

This is the memory request strobe of the Z-80A. i

This strobe enables the upper 8 data bits latched from the CMB onto the Z-80A data bus.

This signal indicates to both the DMA and Interrupt logic that the 4-way has successfully completed arbitration for the bus.

These are the boards bus priority lines which are compared with the priority lines on the EBUS.

This signal is the RAM chip select.

This is the read signal that the see's rece1ve.

These are timing signals used during arbitration.

This is the reset signal received from the EBUS and used to place the 4-way in a known condition.

These are the Ring Indicator signals required for the RS232e p:>rts.

This signal 1S the PROM chip select.

This signal resets the internal bus request.

This signal resets the internal interrupt request. •

These are the Request To Send signals required for each RS232e port.

These are the Receive Data lines required for each RS232e port.

These are the see chip enables.

A-4

SErBOSRD

~

SE1'BUSY

SETINTR

SLtifST

SIDP

Txm - 0

ZAOO - ZAl3

zoo - 7

ZIlATOOTEN

This signal sets the internal bus request signal and starts a EMA cycle.

This signal sets the Il1A circuitry for a read operation.

This signal sets the I:MA circuitry for a write operation.

This strobe sets the BUSY bit in the status register.

This signal sets the internal interrupt request and starts the interrupt cycle.

This signal is activated during the self test portion of the firmware and disables the data drivers to prevent unwanted characters from reaching the screen.

This signal is a' slave mode reset to the board.

This is the second stage enable of the arbitration logic.

This signal starts the driver bus portion of the EMA cycle.

This signal starts the wait cycle necessary for the Z-80A to acknowledge an sec interrupt.

This signal starts the shutdown cycle of the EMA in progress.

These are the Transmit Data lines required for each Rs232C port.

This signal informs the CMB that the base interrupt vector 1S required by, the 4-Way.

This is the wait strobe that is sent to the Z-80A during an 1n­terrupt acknowledge to the sec's.

This turns off the wait line after the wait states are added to the acknowledge cycle.

This signal is activated during the shutdown portion of the current DMA cycle.

This is the write strobe that the sec's rece1ve.

These are the Z-80A's address lines.

These are the Z-80A's data lines.

This signal indicates that the Il1A circuit 1S bringing in data from the CMB.

This signal indicates that the DMA circuit 1S sending data to the CMB.

A-5 M8155A

M8155A A-6