seriallite iii streaming ip core design example user guide · generated ips, such as demo_mgmt,...

SerialLite III Streaming IP Core Design Example User Guide

UG-200302016.10.28

Last updated for Quartus Prime Design Suite: 16.1

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Contents

1 Quick Start Guide.............................................................................................................41.1 Directory Structure................................................................................................. 41.2 Design Example Components................................................................................... 61.3 Generating the Design.............................................................................................7

1.3.1 Procedure..................................................................................................71.3.2 Design Example Parameters.........................................................................81.3.3 Presets......................................................................................................8

1.4 Simulating the Design............................................................................................. 91.4.1 Procedure................................................................................................ 10

1.5 Compiling and Testing the Design............................................................................10

2 Detailed Description for Stratix 10 SerialLite III Streaming Standard Clocking Mode.... 122.1 Features.............................................................................................................. 122.2 Hardware and Software Requirements..................................................................... 122.3 Functional Description........................................................................................... 12

2.3.1 Design Example Components......................................................................132.3.2 Reset Scheme.......................................................................................... 152.3.3 Clocking Scheme...................................................................................... 16

2.4 Simulation........................................................................................................... 172.4.1 Testbench................................................................................................ 17

2.5 Hardware Testing..................................................................................................182.5.1 Design Setup ...........................................................................................18

2.6 Signals................................................................................................................19

3 Detailed Description for Stratix 10 SerialLite III Streaming Advanced Clocking Mode... 213.1 Features.............................................................................................................. 213.2 Hardware and Software Requirements..................................................................... 213.3 Functional Description........................................................................................... 21



3.5 Hardware Testing..................................................................................................273.5.1 Design Setup............................................................................................27

3.6 Signals................................................................................................................28

4 Detailed Description for Arria 10 SerialLite III Streaming Standard Clocking ModeDesign Example....................................................................................................... 304.1 Features.............................................................................................................. 304.2 Hardware and Software Requirements..................................................................... 304.3 Functional Description........................................................................................... 30



4.5 Hardware Testing..................................................................................................37

Contents

SerialLite III Streaming IP Core Design Example User Guide2

4.5.1 Design Setup............................................................................................384.6 Signals................................................................................................................39

5 Arria 10 SerialLite III Streaming Advanced Clocking Mode Design Example.................. 415.1 Features.............................................................................................................. 415.2 Hardware and Software Requirements..................................................................... 415.3 Functional Description........................................................................................... 41



5.5 Hardware Testing..................................................................................................515.5.1 Design Setup............................................................................................51

5.6 Signals................................................................................................................52

A SerialLite III Streaming IP Core Design Example User Guide Document Archives......... 54

B SerialLite III Streaming IP Core Design Example User Guide Document RevisionHistory.....................................................................................................................55

Contents


1 Quick Start GuideThe SerialLite III Streaming IP core provides the capability of generating designexamples for selected configurations.

Figure 1. Development Stages for the Design Example

DesignExample

Generation

Compilation(Simulator)

FunctionalSimulation

Compilation(Quartus Prime)

HardwareTesting

Related Links

SerialLite III Streaming IP Core Design Example User Guide Document Archives onpage 54

Provides a list of user guides for previous versions of the SerialLite III Streaming IPCore IP Core Design Example.

1.1 Directory Structure

The Quartus® Prime software generates the design example files in the followingfolders:

• <user_defined_design_example_directory>/ed_sim

• <user_defined_design_example_directory>/ed_synth

• <user_defined_design_example_directory>/ed_hwtest

The following diagrams show the directories that contain the generated files for thedesign examples.

1 Quick Start Guide

© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX,Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/orother countries. Other marks and brands may be claimed as the property of others. Intel warrants performanceof its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Intel assumesno responsibility or liability arising out of the application or use of any information, product, or servicedescribed herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain thelatest version of device specifications before relying on any published information and before placing orders forproducts or services.

ISO9001:2008Registered

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



Figure 2. Directory Structure for Stratix 10 SerialLite III Streaming Design Example

<Example>

ed_sim ed_synth ed_hwtest

src

altera_sl3_dup

synopsys

cadence

mentor

tb_components

aldec software

Figure 3. Directory Structure for Arria 10 SerialLite III Streaming Design Example

<Example>

ed_sim ed_synth ed_hwtest

src

seriallite_iii_streaming

synopsys

cadence

mentor

tb_components

aldec software

Table 1. Directory and File Description for Design Example Folder

Directory/File Description

ed_sim/tb_components The folder that contains the testbench files.

ed_sim/cadence

ed_sim/mentor

ed_sim/aldec

ed_sim/synopsys/vcs or ed_sim/synopsys/vcsmx

The folder that contains the simulation script. It also servesas a working area for the simulator.

ed_sim/altera_sl3_dup (Stratix® 10)ed_sim/seriallite_iii_streaming (Arria® 10)

The folder that contains the design example simulationsource files.

ed_synth/seriallite_iii_streaming_demo.qpf Quartus project file.

ed_synth/seriallite_iii_streaming_demo.qsf Quartus settings file.

ed_synth/seriallite_iii_streaming_demo.sdc Synopsys Design Constraints (SDC) file.

continued...

1 Quick Start Guide


Directory/File Description

ed_synth/src The folder that contains the design example synthesizablecomponents.

ed_synth/src/seriallite_iii_streaming_demo.v Design example top-level HDL.

ed_synth/altera_sl3_dup/synth/altera_sl3_dup.v (Stratix 10)ed_synth/src/seriallite_iii_streaming/synth/seriallite_iii_streaming.v (Arria 10)

Design example DUT top-level files.

ed_synth/demo_control (Stratix 10)ed_synth/src/demo_control (Arria 10)

The folder for each synthesizable component including Qsysgenerated IPs, such as demo_mgmt, demo_control, ATXPLL, I/O PLL and so forth.

ed_hwtest The folder that contains the design example hardware setupfiles.

ed_hwtest/Readme.txt Instruction file to download the generated design exampleon the development kit.

ed_hwtest/build_demo_control.sh A script to generate demo control and PLL IPs with NIOS IIprocessor.

ed_hwtest/master_export.v User interface Verilog design file.

ed_hwtest/master_export_hw.tcl Component description file for master export custom IP.

ed_hwtest/software The folder that contains scripts to download thedemo_control program into NIOS II processor and open aninteractive terminal to run the design example.

1.2 Design Example Components

Figure 4. Design Example Block Diagram

DemoManagement

TrafficGenerator

TrafficChecker

JTAGinterface

SerialLite III Streaming IP Core

SerialLite IIIStreaming

Duplex

SerialLite III Streaming Link Tx

SerialLite III Streaming Link Rx

Demo ControlQsys Subsystem

Demo ManagementInterface

ATX PLL

fPLL or I/O PLL

Synchronizer

1 Quick Start Guide


1.3 Generating the Design

You can use the SerialLite III Streaming IP core parameter editor in the Quartus Primesoftware to generate the design example.

Figure 5. Procedure

Start ParameterEditor

Specify IP Variationand Select Device

SelectDesign Parameters

InitiateDesign Generation

Specify Example Design

Figure 6. Example Design Tab

Preset Library

Initiates DesignGeneration

1.3.1 Procedure

This is a general procedure on how to generate the design example.

To generate the design example from the IP parameter editor:

1. In the IP Catalog (Tools > IP Catalog), locate and select SerialLite IIIStreaming. The IP parameter editor appears.

2. Specify a top-level name and the folder for your custom IP variation, and thetarget device. Click OK.

3. Select a design from the Presets library. When you select a design, the systemautomatically populates the IP parameters for the design.

Note: If you select another design, the settings of the IP parameters changeaccordingly.

4. Specify the parameters for your design.

5. Click the Generate Example Design button.

The software generates all design files in the sub-directories. These files are requiredto run simulation, compilation, and hardware testing.

1 Quick Start Guide


1.3.2 Design Example Parameters

The SerialLite III Streaming IP parameter editor includes an Example Design tab foryou to specify certain parameters before generating the design example.

Table 2. Parameters in the Example Design Tab

Parameter Description

Select Design Available example designs for the IP parameter settings. When youselect a design from the Preset library, this field shows the selecteddesign.

Generate Files for The files to generate for different development phases.Simulation—when selected, the necessary files for simulating the designexample are generated.Synthesis—when selected, the synthesis files are generated. Use thesefiles to compile the design in the Quartus Prime software for hardwaretesting.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.

Select Board Supported hardware for design implementation. When you select anAltera development board, the Target Device is the one that matches thedevice on the Development Kit.If this menu is grayed out, there is no supported board for the optionsthat you select.Stratix 10 GX Signal Integrity Development Kit: This option allowsyou to test the design example on selected Altera development kit. Thisselection automatically selects the Target Device to match the device onthe Altera development kit. If your board revision has a different devicegrade, you can change the target device.Arria 10 GX Transceiver Signal Integrity Development Kit: Thisoption allows you to test the design example on selected Alteradevelopment kit. This selection automatically selects the Target Deviceto match the device on the Altera development kit. If your boardrevision has a different device grade, you can change the target device.Custom Development Kit: This option allows you to test the designexample on a third party development kit with Altera device, a customdesigned board with Altera device, or a standard Altera development kitnot available for selection. You can also select a custom device for thecustom development kit.No Development Kit: This option excludes the hardware aspects forthe design example.

Change Target Device Select a different device grade for Altera development kit. For device-specific details, refer to the device datasheet on the Altera website.

1.3.3 Presets

Standard presets allow instant entry of pre-selected parameter values in the IP andExample Design tabs. You can select the presets at the lower right window in theparameter editor.

The parameter values chosen for the presets belong to the group of supportedSerialLite III Streaming IP configurations for design example generation. You canselect one of the presets available for your target device to quickly generate a designexample without having to manually set each parameter in the IP tab and verifyingthat the parameter matches the supported configurations set. There are four presetsettings available in the library that support Duplex, Sink and Source modes:

1 Quick Start Guide


• Advanced Clocking Mode 2x10G (Arria 10 devices)

• Advanced Clocking Mode 6x12.5G

• Standard Clocking Mode 2x10G (Arria 10 devices)

• Standard Clocking Mode 6x12.5G

Table 3. Parameter Settings for Stratix 10 Design Example PresetsStratix 10 SerialLite III Streaming IP core design examples are only available in Quartus Prime Pro – Stratix 10Edition Beta. Please contact your local Intel representative for more information.

Presets Advanced Clocking Mode 6x12.5G Standard Clocking Mode 6x12.5G

Direction Duplex, Duplex

Number of lanes 6 6

Meta frame length in words 200 200

Transceiver reference clockfrequency (MHz)

312.5 312.5

Enable M20K ECC support ON and OFF ON and OFF

Clocking Mode Advanced clocking mode Standard clocking mode

Required user clock frequency(MHz)

182.835821 177.556818

Transceiver data rate (Gbps) 12.5 12.5

Table 4. Parameter Settings for Arria 10 Design Example Presets

Presets Advanced ClockingMode 2x10G

Advanced ClockingMode 6x12.5G

Standard ClockingMode 2x10G (Arria

10)

Standard ClockingMode 6x12.5G

Direction Duplex, Sink, andSource

Duplex, Sink, andSource



Number of lanes 2 6 2 6

Meta framelength in words

200 8191 200 8191

Transceiverreference clockfrequency (MHz)

644.53125 312.5 644.531187 312.5

Enable M20KECC support

ON and OFF ON and OFF ON and OFF ON and OFF

Clocking Mode Advanced clockingmode

Advanced clockingmode

Standard clockingmode

Standard clockingmode

Required userclock frequency(MHz)

150.8395522 186.4760558 146.484375 177.556818

Transceiver datarate (Gbps)

10.3125 12.5 10.312499 12.5

1.4 Simulating the Design

These general steps describe how to compile and run the design example simulation.For specific commands for each design example variant, refer to its respective section.

1 Quick Start Guide


Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1.4.1 Procedure

To compile and simulate the design:

Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1. Change the working directory to <example_design_directory>example/ed_sim/<simulator>.

2. Run the simulation script for the simulator of your choice.

Simulator Command

ModelSim® do run_tb.tcl

VCS®/VCS MX sh run_tb.sh

Aldec™ do run_tb.tcl

NC-Sim sh run_tb.sh

A successful simulation ends with the following message, "Test Passed."

After successful completion, you can analyze the results.

1.5 Compiling and Testing the Design

The SerialLite III Streaming IP Core parameter editor allows you to compile and runthe design example on a target development kit.

Complie Designin Quartus Prime

Software

Set up Hardware Program Device Test Designin Hardware

Follow these steps to compile and test the design in hardware:

1. Launch the Quartus Prime software and compile the design (Processing> StartCompilation).

The timing constraints for the design example and the design components areautomatically loaded during compilation.

2. Connect the development board to the host computer.

3. Configure the FPGA on the development board using the generated .soffile(Tools> Programmer).

1 Quick Start Guide


The Quartus Prime version 15.1 only supports programming file generation forArria 10 engineering sample devices. For more information on support for Arria 10production devices, contact your local Intel representative or use the support linkfrom Intel website.

The design example targets the Arria 10 Transceiver Signal Intergrity DevelopmentKit.

The design includes an SDC script as well as a QSF with verified constraints inloopback mode. If you use the design example with another device or developmentboard, you may need to update the device setting and constraints in the QSF file.

You must use correct pin constraints when using the core in simplex mode or whenusing more than one reconfiguration controller. The synthesized design typicallyincludes a reconfiguration interface for at least three channels because three channelsshare an Avalon® Memory Mapped (Avalon- MM) slave interface, which connects tothe Transceiver Reconfiguration Controller IP core. Conversely, you cannot connectthree channels that share an Avalon-MM interface to different TransceiverReconfiguration Controller IP cores or you will receive a Fitter error.

Related Links

SerialLite III Streaming IP Core User Guide

1 Quick Start Guide


https://documentation.altera.com/#/link/bhc1411113020049/bhc1411112778182/en-us

2 Detailed Description for Stratix 10 SerialLite IIIStreaming Standard Clocking Mode

This design example demonstrate the functionalities of data streaming using standardclocking mode.

To generate the design example, select the Standard Clocking Mode 6x12.5G preset.By default, the design examples are generated as duplex core.

Note: Stratix 10 SerialLite III Streaming IP core design examples are only available inQuartus Prime Pro – Stratix 10 Edition Beta. Please contact your local Intelrepresentative for more information.

Related Links

• Testbench on page 17

• SerialLite III Errata

2.1 Features

Features for Standard Clocking Mode 6x12.5G design example includes:

• Support 6 lanes with 12.5Gpbs transceiver data rate

• Support duplex transmission mode

• Traffic checker for data verification and lane de-skew verification

• Support CRC error injection using Nios II processor

2.2 Hardware and Software Requirements

Intel uses the following hardware and software to test the example designs in a Linuxsystem:

• Quartus® Prime software

• ModelSim-AE, Modelsim-SE, NC-Sim (Verilog only), or VCS simulator

• Stratix 10 GX Transceiver Signal Integrity Development Kit for hardware testing

2.3 Functional Description

The design examples consist of various components. The following block diagramshow the design components and the top level connections of the design example.

Figure 7. Design Example for Duplex Core in Standard Clocking Mode

2 Detailed Description for Stratix 10 SerialLite III Streaming Standard Clocking Mode



http://www.altera.com/support/kdb/search?q=sl_iii_streaming_ki




DemoManagement

TrafficGenerator

TrafficChecker

Duplex Standard Clocking Variation


Duplex

mgmt_reset_n




ATX PLL

PHY Management Clock

Demo Management Clock

UARTJTAGAvalon Master

Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

pll_ref_clk

fPLL

Synchronizer

rx_activity_n

snk_link_up_n

src_link_up_n

tx_activity_nsrc_core_reset_n

snk_core_reset_n

TX Serial Clock

source_user_clock

2.3.1 Design Example Components

The design example consists of following components:

• SerialLite III Streaming IP core variation

• Source and sink user clock—fPLL

• ATX PLL

• Traffic generator

• Traffic checker

• Demo control

• Demo management

2.3.1.1 SerialLite III Streaming IP Core

The SerialLite III Streaming IP core variation accepts data from the traffic generatorand formats the data for transmission. It also receives data from the link, strips theheaders, and presents it to the traffic checker for analysis. The core is generated usingthe parameter editor in the Quartus Prime software.

2.3.1.2 User Clock

The fPLL generates a user clock for sourcing and sinking data into the SerialLite IIIStreaming IP core.



2.3.1.3 Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data istransmitted correctly across the link. Traffic consists of sets of sample words, one foreach lane on the link, that are presented to the source user interface.

Figure 8. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.

Word ID Burst Count Word Count

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

Table 5. Traffic Generator Sample Word Fields

Field Bits Description

Word ID 63–59 Contains a static value to distinguish which 64-bit word on the user interface that thissample was presented on. The Word ID value ranges from 0 to (lanes–1).

Burst Count 58–32 Tracks the number of bursts used to transfer the sample data. This field value starts withone after reset and is incremented each time the start_of_burst signal is asserted onthe source user interface.

Word Count 31–0 Tracks the number of valid sample words that have been transferred, across all bursts, tothe source user interface.

2.3.1.4 Traffic Checker

The traffic checker performs the following inspections to verify that the received dataconforms to the expected format:

• Checks each sample word to verify that the expected word ID was received.

• Checks each sample word to verify that the word count value is higher than theword count value from the last valid sample word.

• Verifies that lane de-skew has been properly performed by validating that theword count and burst count values from the sample word are the same as thevalues received from the adjacent lane.

• If the start_of_burst signal is asserted on the user interface, verifies that theburst count value in the current sample word is higher than the burst count valuefrom the last valid sample word. Otherwise, it verifies that the burst count valuehas not changed.

2.3.1.5 Demo Control

The demo control module is a Nios® II processor system, generated in Qsys, to controlthe demo hardware. In addition to the Nios II processor system, this module alsoincludes reconfiguration controllers for the transceivers and PLL channels in theSerialLite III Streaming IP core. The number of reconfiguration interfaces equal to thenumber of transceivers plus PLL channels for the source and duplex cores, and thenumber of transceivers for the sink cores.

Demo control module also consists of a timer to track interrupt occurence, Avalon-MMinterface to access demo management and the SerialLite III Streaming IP PHYinterface, a reset controller, an UART interface, and an Avalon Streaming (Avalon-ST)interface.



2.3.1.6 Demo Management

The demo management module controls the user modules interaction with theSerialLite III Streaming IP core such as enable and disable traffic generator and trafficchecker, enable CRC error insertion, and provide user clock reset for SerialLite IIIStreaming IP core. The module also implements CSRs to control and monitor thedesign operation. This includes CSRs to monitor and log errors that occur during theoperation.

2.3.1.7 Nios II Processor Code

The Nios II processor controls the options exercised in the design example. The codealso enables CRAM bits for CRC-32 error injection support. The error injection supportin 10G PCS is based on groups of three channels or triplets. Setting the correspondingbit for a given channel in the triplet enables CRC error injection for all of the lanes thatuse any channel in the given triplet.

The design example sets the bit for channel 0 that connects to lane 0 in the designexample. Therefore, CRC error injection is exercisable for lane 0 only. Refer to theNios II processor source code (demo_control.c) for information on setting bits forother channels.

2.3.2 Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the designexample. This is an asynchronous and active-low signal. Asserting this signal resetsthe demo control module and the SerialLite III Streaming IP core. The trafficgenerator and traffic checker modules get reset through the demo management andthe reset synchronizer.

The following diagram show the reset scheme implemented in the design example.



Figure 9. Reset Scheme for Stratix 10 SerialLite III Streaming Duplex Core in StandardClocking Mode

DemoManagement

TrafficGenerator

TrafficChecker



Duplex

mgmt_reset_n

ATX PLL


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

source_reset

user_clock_reset_tx

sink_reset

fPLL

Synchronizer

phy_mgmt_clk_resetsource_user_clock_reset

user_clock_reset

snk_core_reset

src_core_reset

user_clock_reset_rx

sink_user_clock_reset

demo_mgmt_clk_reset_n

pll_lockedpll_locked

2.3.3 Clocking Scheme

The following diagrams show the clocking scheme for the design example.



Figure 10. Clocking Scheme for Stratix 10 SerialLite III Streaming Duplex Core inStandard Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker



Duplex

ATX PLL

Transceiver Reset Controller

mgmt_clk

demo_mgmt_clk


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

pll_ref_clk

fPLL

Synchronizer

tx_serial_clk

phy_mgmt_clk

xcvr_pll_ref_clk

pll_refclk0

user_clock

src_user_clock

snk_user_clock

clk_clk

clk_clk

clk_clk

2.4 Simulation

The simulation test cases demonstrate continuous streaming of 2000 sample data for6 lanes with 12.5Gbps transceiver data rate from traffic generator to the SerialLite IIIStreaming source core and externally loopback to the sink core in standard clockingmode.

The simulation test case performs the following steps:

1. Initialize and configures SerialLite III Streaming IP core, traffic generator andtraffic checker.

2. Traffic generator generates data and starts data transmission.

3. Logs and display link up status and burst information.

4. Traffic checker verifies received data and stop transmission.

5. Testbench logs and displays test result and test information.

2.4.1 Testbench

The generated example testbench is dynamic and has the same configuration as theIP. When you choose the duplex direction, the parameter editor generates an externaltransceiver ATX PLL for use in the Stratix 10 testbench. Therefore, Intel recommendsthat you generate the Stratix 10 simulation testbench for designs using the duplexdirection.



Note: The Stratix 10 example testbench includes the external transceiver PLL; the IP coredoes not include the transceiver PLL for these devices.

Figure 11. SerialLite III Streaming Example Testbench (Duplex) for Stratix 10 Devices

Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

NativePHY IP

Duplex -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Loopback

Device Under Test (Duplex Mode)Test Environment

SinkApplication

2.5 Hardware Testing

Once you download the design and accompanying software into the FPGA, you cantest the design operation through the interactive session. The interactive sessionprovides helpful statistics, as well as controls for controlling various aspects of thedesign.

You can control the following operations through the interactive session:

1. Enable Data Generator/Checker—Enables the traffic generator and start sendingout data.

2. Disable Data Generator/Checker—Disables traffic generation.

3. Reset Source Core—Resets the source core and traffic generator.

4. Reset Sink Core—Resets the sink core and traffic checker.

5. Display Error Details—Displays the error statistics.

6. Toggle Burst Mode—Resets the source and sink MACs and toggles the trafficgenerator to generate a burst traffic stream.

7. Toggle CRC Error Insertion—Turns CRC error injection off or on.

2.5.1 Design Setup

The design example targets the Stratix 10 Transceiver Signal Integrity DevelopmentKit.




2.6 Signals

Figure 12. Top-level Signals for Stratix 10 SerialLite III Streaming Standard ClockingMode Design Example

Stratix 10 SerialLite III Streaming Standard Clock Design Example

mgmt_clk

mgmt_reset_n

pll_ref_clk

rx [n]

snk_core_reset_n

src_core_reset_n

sink_link_up_n

src_link_up_n

rx_activity_n

tx_activity_n

tx [n]

Table 6. Design Example Interface Signals

Signal Direction Width Description

Clock and Reset Signal

mgmt_clk Input 1 Input clock for:• Avalon-MM PHY management

interface for SerialLite III StreamingIP core

• Demo management module• Demo control module• Transceiver reset controller

pll_ref_clk Input 1 This reference clock is used by the ClockData Recovery (CDR) unit in thetransceiver. It serves as a reference forthe CDR to recover the clock from theserial line. The frequency of this clockmust match the frequency you select inthe IP parameter editor. It should also

continued...




match the frequency of the tx_pll_ref_clkreference clock for the TX PLL at theSource variant.

mgmt_reset_n Input 1 Design example asychrounous masterreset. Assert this reset signal to reset theoverall design example system.This is an active low signal.

snk_core_reset_n Output 1 Demo management module asserts thissignal to reset traffic checker module.

src_core_reset_n Output 1 Demo management module asserts thissignal to reset traffic generator module.

Data Signal

rx[n] Input Based on Numberof Lanes value

This vector carries the transmittedstreaming data from the core.N represents the number of lanes.

tx[n] Output Based on Numberof Lanes value

This vector carries the transmittedstreaming data to the core.N represents the number of lanes.

Status Signal

rx_activity_n Output 1 This single bit signal indicates that thedata is valid.

tx_activity_n Output 1 This single bit signal indicates that thedata is valid.

snk_link_up_n Output 1 The core asserts this signal to indicatethat the core initialization is completeand is ready to receive user data.

src_link_up_n Output 1 The core asserts this signal to indicatethat the core initialization is completeand is ready to transmit user data.



3 Detailed Description for Stratix 10 SerialLite IIIStreaming Advanced Clocking Mode

This design example demonstrate the functionalities of data streaming using advancedclocking mode.

To generate the design example, select the Advanced Clocking Mode 6x12.5G presets.By default, the design examples are generated as duplex core.

3.1 Features

Features for Advanced Clocking Mode 6x12.5G design example includes:


• Support duplex transmission modes







• Stratix 10 GX Transceiver Signal Integrity Development Kit for hardware testing


The design example consist of various components. The following block diagram showthe design components and the top level connections of the design example.

3 Detailed Description for Stratix 10 SerialLite III Streaming Advanced Clocking Mode






Figure 13. Design Example for Duplex Core in Advanced Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker

Duplex AdvancedClocking Variation


Duplex

mgmt_reset_n




ATX PLL




Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

pll_ref_clk

fPLL

Synchronizer

rx_activity_n

snk_link_up_n

src_link_up_n

tx_activity_nsrc_core_reset_n

snk_core_reset_n

TX Serial Clock

source_user_clock




• Source and sink user clock—fPLL

• ATX PLL


• Traffic checker

• Demo control

• Demo management



3.3.1.2 User Clock

The fPLL generates a user clock for sourcing and sinking data into the SerialLite IIIStreaming IP core.








3.3.2 Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the designexample. This is an asynchronous and active-low signal. Asserting this signal resetsthe demo control module and the SerialLite III Streaming IP core. The trafficgenerator and traffic checker modules get reset through the demo management andthe reset synchronizer.

The following diagrams show the reset scheme implemented in the design example.



Figure 15. Reset Scheme for Stratix 10 SerialLite III Streaming Duplex Core inAdvanced Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker

Duplex Advanced Clocking Variation


Duplex

mgmt_reset_n

ATX PLL


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

source_reset

user_clock_reset

sink_reset

fPLL

Synchronizer

phy_mgmt_clk_resetsource_user_clock_reset

user_clock_reset

snk_core_reset

src_core_reset

user_clock_reset


demo_mgmt_clk_reset

pll_lockedpll_locked


The following diagram show the clocking scheme for the design example.



Figure 16. Clocking Scheme for Stratix 10 SerialLite III Streaming Duplex Core inAdvanced Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker

Duplex AdvancedClocking Variation


Duplex

ATX PLL

mgmt_clk

demo_mgmt_clk


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

pll_ref_clk

fPLL

Synchronizer

tx_serial_clk

phy_mgmt_clk

xcvr_pll_ref_clk

pll_refclk0

user_clock

user_clock

user_clock

clk_clk

clk_clk

clk_clk

3.4 Simulation

The simulation test cases demonstrate continuous streaming of 2000 sample data for6 lanes with 12.5Gbps transceiver data rate from traffic generator to the SerialLite IIIStreaming source core and externally loopback to the sink core in advanced clockingmode.







3.4.1 Testbench

The generated example testbench is dynamic and has the same configuration as theIP . When you choose the duplex direction, the parameter editor generates an externaltransceiver ATX PLL for use in the Stratix 10 testbench. Therefore, Intel recommendsthat you generate the Stratix 10 simulation testbench for designs using the duplexdirection.



Note: The Stratix 10 example testbench includes the external transceiver PLL; the IP coredoes not include the transceiver PLL for these devices.

Figure 17. SerialLite III Streaming Example Testbench (Duplex) for Stratix 10 Devices

Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

NativePHY IP

Duplex -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Loopback


SinkApplication











3.5.1 Design Setup

The design example targets the Stratix 10 Transceiver Signal Integrity DevelopmentKit.




3.6 Signals

Figure 18. Top-level Signals for Stratix 10 SerialLite III Streaming Advanced ClockingMode Design Example

Stratix 10 SerialLite III Streaming Advanced Clock Design Example

mgmt_clk

mgmt_reset_n

pll_ref_clk

rx [n]

snk_core_reset_n

src_core_reset_n

sink_link_up_n

src_link_up_n

rx_activity_n

tx_activity_n

tx [n]







pll_ref_clk Input 1 This reference clock is used by the ClockData Recovery (CDR) unit in thetransceiver. It serves as a reference forthe CDR to recover the clock from theserial line. The frequency of this clockmust match the frequency you select inthe IP parameter editor. It should also

continued...




match the frequency of the tx_pll_ref_clkreference clock for the TX PLL at theSource variant.




Data Signal





Status Signal







4 Detailed Description for Arria 10 SerialLite IIIStreaming Standard Clocking Mode Design Example

This design example demonstrate the functionalities of data streaming using standardclocking mode.

To generate the design example, select the following presets:

• Standard Clocking Mode 2x10G

• Standard Clocking Mode 6x12.5G

By default, the design examples are generated as duplex core. To generate the designexamples in simplex core, select Simplex for the Direction parameter.

4.1 Features

Features for Standard Clocking Mode 2x10G design example includes:

• Support 2 lanes with 10Gpbs transceiver data rate

• Support simplex and duplex transmission modes



Features for Standard Clocking Mode 6x12.5G design example includes:









• Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing


The design examples consist of various components. The following block diagramshow the design components and the top level connections of the design examples.

4 Detailed Description for Arria 10 SerialLite III Streaming Standard Clocking Mode DesignExample






Figure 19. Design Example for Simplex Core in Standard Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker

Simplex Standard Clocking Variation


Sink


Source

mgmt_reset_n




ATX PLL


PLL Power Down



Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

pll_ref_clk

xcvr_pll_ref_clk

tx_serial_clk

phy_mgmt_clk

phy_mgmt_clk

xcvr_pll_ref_clk

rx_activitiy_n

snk_core_reset_n

demo_mgmt_clk

Demo Control Qsys Subsystem

snk_link_up

src_core_reset_n

src_link_up

tx_activitiy_n

Figure 20. Design Example for Duplex Core in Standard Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker


mgmt_reset_n




ATX PLL


PLL Power Down



Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

pll_ref_clktx_serial_clk

phy_mgmt_clk

xcvr_pll_ref_clk

rx_activitiy_n

snk_core_reset_n

demo_mgmt_clk


snk_link_up

src_core_reset_n

src_link_up

tx_activitiy_n

SerialLite III

StreamingDuplex






• ATX PLL


• Traffic checker

• Demo control

• Demo management

• Nios II processor code


The SerialLite III Streaming IP core in this variant can either accepts data from thetraffic generator and format it for transmission or receive data from the link, strips theheaders, and presents it to the traffic checker for analysis. The core is generated withthe parameter settings you select using the parameter editor in the Quartus Primesoftware.

4.3.1.2 ATX PLL

The ATX PLL generates transmit transceiver clock to the SerialLite III Streaming IPcore.



























4.3.2 Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the designexample. This is an asynchronous and active-low signal. Asserting this signal resetsthe demo control module and the SerialLite III Streaming IP core. The trafficgenerator and traffic checker modules get reset through the demo management andthe SerialLite III Streaming IP core.



The following diagrams show the reset scheme implemented in the design examples.

Figure 22. Reset Scheme for Arria 10 SerialLite III Streaming Simplex Core in StandardClocking Mode

DemoManagement

TrafficGenerator

TrafficChecker



Sink


Source

mgmt_reset_n


ATX PLL


PLL Power Down


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

source reset user_clock_reset

sink reset user_clock_reset

src_core_reset_n

sink_core_reset_n

core_reset

core_reset

phy_mgmt_clk_reset

phy_mgmt_clk_reset


source_user_clock_reset


Figure 23. Reset Scheme for Arria 10 SerialLite III Streaming Duplex Core in StandardClocking Mode

DemoManagement

TrafficGenerator

TrafficChecker

mgmt_reset_n


ATX PLL


PLL Power Down


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

source resetuser_clock_reset

sink reset user_clock_reset

SerialLite III

StreamingDuplex


phy_mgmt_clk_reset

core_reset

src_core_reset_n

sink_core_reset_n



source_user_clock_reset




The following diagrams show the clocking scheme for the design examples.

Figure 24. Clocking Scheme for Arria 10 SerialLite III Streaming Simplex Core inStandard Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker



Sink


Source


ATX PLL


mgmt_clk

demo_mgmt_clk


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

user_clock

pll_ref_clk

xcvr_pll_ref_clk

xcvr_pll_ref_clk

tx_serial_clk


clk_clk

phy_mgmt_clk

phy_mgmt_clk

sink_user_clock

source_user_clock



Figure 25. Clocking Scheme for Arria 10 SerialLite III Streaming Duplex Core inStandard Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker


SerialLite III

Streaming Duplex


ATX PLL


mgmt_clk

demo_mgmt_clk


Export

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM

ExportAvalon Master

Reset Controller

user_clock

user_clock

pll_ref_clk

xcvr_pll_ref_clk

tx_serial_clk


clk_clk

phy_mgmt_clk

sink_user_clock

source_user_clock

clock

4.4 Simulation

The simulation test cases demonstrate continuous streaming of 2000 sample data forall lanes from traffic generator to the SerialLite III Streaming source core andexternally loopback to the sink core in standard clocking mode.







4.4.1 Testbench

If your design targets Arria 10 devices, the generated example testbench is dynamicand has the same configuration as the IP. When you choose the sink or duplexdirection, the parameter editor generates an external transceiver ATX PLL for use inthe Arria 10 testbench. Therefore, Intel recommends that you generate the Arria 10simulation testbench for designs using the sink or duplex direction.



Figure 26. SerialLite III Streaming Example Testbench (Duplex) for Arria 10 Devices

Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

NativePHY IP

Duplex -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Loopback


SinkApplication

SourceClock

Generator

SinkClock

Generator

Figure 27. SerialLite III Streaming Example Testbench (Simplex) for Arria 10 Devices

Device Under Test (Sink)Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

SourceClock

Generator

SinkClock

Generator

NativePHY IP

TX -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Device Under Test (Source)Test Environment

NativePHY IP

RX -Interlaken

Mode

Loopback

SinkApplication













4.5.1 Design Setup

The design example targets the Arria 10 Transceiver Signal Integrity Development Kit.


You must use correct pin constraints when using the core in simplex mode or whenusing more than one reconfiguration controller. The synthesized design typicallyincludes a reconfiguration interface for at least three channels because three channelsshare an Avalon-MM slave interface, which connects to the Transceiver ReconfigurationController IP core. Conversely, you cannot connect three channels that share anAvalon-MM interface to different Transceiver Reconfiguration Controller IP cores or youwill receive a Fitter error.

Related Links

Altera Transceiver PHY IP Core User GuideMore information about the Interlaken PHY IP core.



http://www.altera.com/literature/ug/xcvr_user_guide.pdf

4.6 Signals

Figure 28. Top-level Signals for Arria 10 SerialLite III Streaming Standard ClockingMode Design Example

Arria 10 SerialLite III Streaming Standard Clock Design Example

mgmt_clk

mgmt_reset_n

pll_ref_clk

rx [n]

snk_core_reset_n

src_core_reset_n

sink_link_up_n

src_link_up_n

rx_activity_n

tx_activity_n

tx [n]







pll_ref_clk Input 1 This reference clock is used by the ClockData Recovery (CDR) unit in thetransceiver. It serves as a reference forthe CDR to recover the clock from theserial line. The frequency of this clockmust match the frequency you select inthe IP parameter editor. It should alsomatch the frequency of the tx_pll_ref_clkreference clock for the TX PLL at theSource variant.

continued...







Data Signal





Status Signal







5 Arria 10 SerialLite III Streaming Advanced ClockingMode Design Example

This design example demonstrate the functionalities of data streaming using advancedclocking mode.

To generate the design example, select the following presets:

• Advanced Clocking Mode 2x10G

• Advanced Clocking Mode 6x12.5G

By default, the design examples are generated as duplex core. To generate the designexamples in simplex core, select Simplex for the Direction parameter.

5.1 Features

Features for Advanced Clocking Mode 2x10G design example includes:

• Support 2 lanes with 10Gpbs transceiver data rate




Features for Advanced Clocking Mode 6x12.5G design example includes:









• Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing


The design examples consist of various components. The following block diagramshow the design components and the top-level connections of the design examples.

5 Arria 10 SerialLite III Streaming Advanced Clocking Mode Design Example






Figure 29. Design Example for Simplex Core in Advanced Clocking Mode

JTAGinterface

DemoManagement

TrafficGenerator

TrafficChecker

Simplex Advanced Clocking Variation

I/O PLL

SerialLite III Streaming Link TX

SerialLite III Streaming Link RX

ATX PLLSource User Clock PLL Ref Clock

Source User Clock

TX Serial Clock

Sink User Clock

mgmt_reset_n


PLL Power Down



UARTAvalon Master

Export Reset Controller

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

Synchronizer


Source


Sink rx_activity_n

src_core_reset_n

snk_core_reset_n

snk_link_up_n

src_link_up_n

tx_activity_n

JTAG



Figure 30. Design Example for Duplex Core in Advanced Clocking Mode

JTAGinterface

DemoManagement

TrafficGenerator

TrafficChecker


I/O PLL

SerialLite III Streaming Link TX

SerialLite III Streaming Link RX

ATX PLLSource User Clock PLL Ref Clock

Source User Clock

TX Serial Clock

mgmt_reset_n


PLL Power Down



Avalon MasterExport Reset Controller

Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

Synchronizer

SerialLite III

Streaming

Duplex

rx_activity_n

src_core_reset_n

snk_core_reset_n

snk_link_up_n

src_link_up_n

tx_activity_n

UARTJTAG




• ATX PLL

• Source user clock—I/O PLL


• Traffic checker

• Demo control

• Demo management

• Nios II processor code





5.3.1.2 Source User Clock - I/O PLL

The I/O PLL generates a user clock for sourcing data into the SerialLite III StreamingIP core when configured in Advanced Clocking Mode.

5.3.1.3 ATX PLL

The ATX PLL generates transmit transceiver clock to the SerialLite III Streaming IPcore.



























5.3.2 Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the designexample. This is an asynchronous and active-low signal. Asserting this signal resetsthe demo control module and the SerialLite III Streaming IP core. The trafficgenerator and traffic checker modules get reset through the demo management andthe SerialLite III Streaming IP core.

The following diagrams show the reset scheme implemented in the design examples.



Figure 32. Reset Scheme for Arria 10 SerialLite III Streaming Simplex Core in AdvancedClocking Mode

DemoManagement

TrafficGenerator

TrafficChecker


I/O PLL ATX PLL

mgmt_reset_n


PLL Power Down



Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

source reset

user_clock_reset

sink resetuser_clock_reset

Synchronizer


Source


Sink

snk_core_reset_n

src_core_reset_n


source_user_clock_resetuser_clock_reset

core_reset

phy_mgmt_clk_reset

core_reset

phy_mgmt_clk_reset

rst

reset



Figure 33. Reset Scheme for Arria 10 SerialLite III Streaming Duplex Core in AdvancedClocking Mode

DemoManagement

TrafficGenerator

TrafficChecker


I/O PLL ATX PLL

mgmt_reset_n


PLL Power Down



Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

source reset

user_clock_reset

sink resetuser_clock_reset

Synchronizer


Duplex

snk_core_reset_n

src_core_reset_n


source_user_clock_resetuser_clock_reset

phy_mgmt_clk_reset

rst

reset


The following diagrams show the clocking scheme for the design examples.



Figure 34. Clocking Scheme for Arria 10 SerialLite III Streaming Simplex Core inAdvanced Clocking Mode

DemoManagement

TrafficGenerator

TrafficChecker


I/O PLL ATX PLL

user_clockpll_ref_clk

source_user_clock

tx_serial_clk

user_clock


phy_mgmt_clk

demo_mgmt_clk



Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

Synchronizer

phy_mgmt_clk

xcvr_pll_ref_clk

sink_user_clock

user_clock

clk

pll_refclk0


Sink


Source

xcvr_pll_ref_clk

phy_mgmt_clk



Figure 35. Clocking Scheme for Arria 10 SerialLite III Streaming Duplex Core inAdvanced Clocking Mode


DuplexDemo

Management

TrafficGenerator

TrafficChecker


I/O PLL ATX PLL

user_clock_txpll_ref_clk

source_user_clock

tx_serial_clk

user_clock


phy_mgmt_clk

demo_mgmt_clk



Avalon Interconnect

IntervalTimer

NIOS IICPU

RAM


ExportAvalon Master

Synchronizer

phy_mgmt_clk

xcvr_pll_ref_clk

sink_user_clock

user_clock

clk

pll_refclk0

5.4 Simulation

The simulation test cases demonstrate continuous streaming of 2000 sample data forall lanes from traffic generator to the SerialLite III Streaming source core andexternally loopback to the sink core in advanced clocking mode.









5.4.1 Testbench

If your design targets Arria 10 devices, the generated example testbench is dynamicand has the same configuration as the IP. When you choose the sink or duplexdirection, the parameter editor generates an external transceiver ATX PLL for use inthe Arria 10 testbench. Therefore, Intel recommends that you generate the Arria 10simulation testbench for designs using the sink or duplex direction.

Note: The Arria 10 example testbench includes the external transceiver PLL; the IP coredoes not include the transceiver PLL for these devices.

Figure 36. SerialLite III Streaming Example Testbench (Duplex) for Arria 10 Devices

Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

NativePHY IP

Duplex -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Loopback


SinkApplication

SourceClock

Generator

SinkClock

Generator

Figure 37. SerialLite III Streaming Example Testbench (Simplex) for Arria 10 Devices

Device Under Test (Sink)Testbench

TrafficGenerator

TrafficChecker

SourceApplication

SourceAdaptation

SinkAdaptation

SinkAlignment

SourceClock

Generator

SinkClock

Generator

NativePHY IP

TX -Interlaken

Mode

TransceiverTX PLL

SkewInsertion

Device Under Test (Source)Test Environment

NativePHY IP

RX -Interlaken

Mode

Loopback

SinkApplication













5.5.1 Design Setup

The design example targets the Arria 10 Transceiver Signal Integrity Development Kit.


You must use correct pin constraints when using the core in simplex mode or whenusing more than one reconfiguration controller. The synthesized design typicallyincludes a reconfiguration interface for at least three channels because three channelsshare an Avalon-MM slave interface, which connects to the Transceiver ReconfigurationController IP core. Conversely, you cannot connect three channels that share anAvalon-MM interface to different Transceiver Reconfiguration Controller IP cores or youwill receive a Fitter error.

Related Links

Altera Transceiver PHY IP Core User GuideMore information about the Interlaken PHY IP core.



http://www.altera.com/literature/ug/xcvr_user_guide.pdf

5.6 Signals

Figure 38. Top-level Signals for Arria 10 SerialLite III Streaming Standard ClockingMode Design Example

Arria 10 SerialLite III Streaming Advanced Clock Design Example

mgmt_clk

mgmt_reset_n

pll_ref_clk

rx [n]

snk_core_reset_n

src_core_reset_n

sink_link_up_n

src_link_up_n

rx_activity_n

tx_activity_n

tx [n]







pll_ref_clk Input 1 This reference clock is used by the ClockData Recovery (CDR) unit in thetransceiver. It serves as a reference forthe CDR to recover the clock from theserial line. The frequency of this clockmust match the frequency you select inthe IP parameter editor. It should alsomatch the frequency of the tx_pll_ref_clkreference clock for the TX PLL at theSource variant.

continued...







Data Signal





Status Signal







A SerialLite III Streaming IP Core Design Example UserGuide Document Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version User Guide

16.0 SerialLite III Streaming IP Core Design Example User Guide Document Archives

A SerialLite III Streaming IP Core Design Example User Guide Document Archives



https://www.altera.com/en_US/pdfs/literature/ug/archives/ug-design-ex-slite3-streaming.pdf




B SerialLite III Streaming IP Core Design Example UserGuide Document Revision History

Date Version Changes

October 2016 2016.10.28 • Added Stratix 10 device support.• Restructured document.

May 2016 2016.05.02 Initial release.

B SerialLite III Streaming IP Core Design Example User Guide Document Revision History






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