SEQUOIA

Physical & Timing Verification of Subwavelength-Scale Designs

using Physical Simulation

Robert Pack (formerly of Cadence Berkeley Labs) Valery Axelrad, Andrei Shibkov, Victor Boksha

(Sequoia Design Integration, Inc.) Judy Huckabay, Rachid Salik, Wolf Staud

(Cadence Design Systems, Inc.) Ruoping Wang, Warren Grobman (Motorola Inc.)

SEQUOIA

Outline

IntroductionIntroductionProblem StatementProblem StatementOPE Impact on Device PerformanceOPE Impact on Device PerformanceOPE and RET effectsOPE and RET effectsTiming AnalysisTiming AnalysisMulti-partioning of critical devicesMulti-partioning of critical devicesSummarySummary

SEQUOIA

Introduction DPI closure is key for successful <130DPI closure is key for successful <130nmnm designs designs Current state-of-art EDA tools insufficient

insufficient in predicting performance insufficient in predicting yield/reliability

Timing , SI, Race Conditions, Power… +/- %100

These factors are responsible for costly fabrication yieldre-spins – >%30 ! . Failure Costs are high!

Residual design-to-silicon distortions

Design and verification must account for increased process and device physics entanglement

Novel verification approach unique new adjunct to DFM and MSO flows

SEQUOIA

Problem statement ExcessiveExcessive Re-spins Re-spins

Number of Silicon Spins in Current IC/ASIC Designs

53%

28%

15%

3% 2%0%

15%

30%

45%

60%

First Silicon 2 3 4 5 or More

Perc

ent o

f Tea

ms

Spins of Silicon

n=329Number of Silicon Spins in Current IC/ASIC Designs

53%

28%

15%

3% 2%0%

15%

30%

45%

60%

First Silicon 2 3 4 5 or More

Perc

ent o

f Tea

ms

Spins of Silicon

n=329

Percent of Total Flaws Fixed inIC/ASIC Designs Having Two or More Silicon Spins

3%

3%

4%

5%

5%

6%

7%

9%

14%

43%

0% 10% 20% 30% 40% 50%

Power

Clocking

IR Drops

Other Flaws

Mixed-Signal Interface

Race Condition

Yield

Noise

Slow Path

Logical or Functional

Percent of FlawsSource: Collett International Research 2000

Percent of Total Flaws Fixed inIC/ASIC Designs Having Two or More Silicon Spins

3%

3%

4%

5%

5%

6%

7%

9%

14%

43%

0% 10% 20% 30% 40% 50%

Power

Clocking

IR Drops

Other Flaws

Mixed-Signal Interface

Race Condition

Yield

Noise

Slow Path

Logical or Functional

Percent of FlawsSource: Collett International Research 2000

Large % of flaws Large % of flaws

due to SI and Powerdue to SI and Power

Note: Feature-limited yield assumes the feature failure rate improves by approximately 50% each generation

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield

Note: Feature-limited yield assumes the feature failure rate improves by approximately 50% each generation

Note: Feature-limited yield assumes the feature failure rate improves by approximately 50% each generation

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm

Technology Node

Product Yield

Traditional defect-limited yield

Feature-limited yield

Note: Feature-limited yield assumes the feature failure rate improves by approximately 50% each generation

Parametric and Catastrophic Yield Parametric and Catastrophic Yield LossLoss Feature LimitedFeature Limited Reliability IssueReliability Issue

Proximity EffectsProximity Effects DeviceDevice LITHOGRAHICLITHOGRAHIC

Mitigation: OPC/PSMMitigation: OPC/PSM

Design Tools lack abilityDesign Tools lack ability

to capture complex physical effectsto capture complex physical effects

Source: Kibarian/PDF Solutions & Collet

SEQUOIA

“Silicon Verification” must be performed before committing a SubWavelength design to silicon.

Design

PASS !

Layout - DRC

Layout - LVS

Layout - Timing

PhysicalVerification

Layout

Silicon - DRC XX

Silicon - LVS XX

Silicon - Timing XX

Silicon LevelVerification

Compares silicon to layout

FAIL!

FAIL!

SEQUOIA

DistributedG ate length

DV t, I leakage

Devices from silicon-level layout havedifferent deviceproperties than fromdrawn layout.

Parasitics fromsilicon-level layoutare d ifferent fromthose extracted fromdrawn layout

DC p

DL eff

Contact pullback canresult in h igh resistanceor opens

D istributedG ate length

DV t, I leakage

Devices from silicon-level layout havedifferent deviceproperties than fromdrawn layout.

Parasitics fromsilicon-level layoutare d ifferent fromthose extracted fromdrawn layout

DC p

DL eff

Contact pullback canresult in h igh resistanceor opens

Specific Problem: Silicon-Level Verification

Industry focusing on Interconnects

- OPE Impact on Device Performance

SEQUOIA

Verification of Process Proximity Effects - through physical simulation

OPE distortion affects transistor performance and matching

OPE distortion affects parasitics extraction accuracy

OPE is the major deterministic OPE is the major deterministic source of device variabilitysource of device variability electrical impact of image electrical impact of image

qualityquality gate length variationgate length variation line end pullbackline end pullback

Complicates performance estimation / bin sort yield

DistributedG ate length

DV t, I leakage

Devices from silicon-level layout havedifferent deviceproperties than fromdrawn layout.

Parasitics fromsilicon-level layoutare d ifferent fromthose extracted fromdrawn layout

DC p

DL eff

Contact pullback canresult in h igh resistanceor opens

D istributedG ate length

DV t, I leakage

Devices from silicon-level layout havedifferent deviceproperties than fromdrawn layout.

Parasitics fromsilicon-level layoutare d ifferent fromthose extracted fromdrawn layout

DC p

DL eff

Contact pullback canresult in h igh resistanceor opens

SEQUOIA

OPE is the major deterministic source of device variability

VdsLeakage/ Shorts

Heat

OPE impacts

• device performance characteristics

• Vth

• Idsat

• Ioff

• Power (leakage)

• Yield/Reliability

SEQUOIA

Additional Complexity

SEQUOIA

Experimental Simulation Conditions 248248nmnm NA=0.7 NA=0.7 Source:Source:

Binary and OPCBinary and OPC Pillbox; Sigma=0.6Pillbox; Sigma=0.6

altPSMaltPSM Binary: Sigma=0.6Binary: Sigma=0.6 PS: Sigma=0.35PS: Sigma=0.35

OPC Style: Aggressive Simulation-Based OPCOPC Style: Aggressive Simulation-Based OPC PSM Style: NTI Double Exposure altPSMPSM Style: NTI Double Exposure altPSM NOTNOT A Motorola process A Motorola process Not lithographically refined or RET optimizedNot lithographically refined or RET optimized

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Experimental Structure

32-bit Adder scaled to 15032-bit Adder scaled to 150nmnm4285 MOSFETs / CMOS technology4285 MOSFETs / CMOS technologyLithography simulation performed full-Lithography simulation performed full-

structurestructure

K-T/Finle -Prolith

SEQUOIA

Defocus EffectBIM – 0.1um steps

BIM 0-Def

0.2-Def

0.2-Def

0.1-Def

0.1-Def

0.4-Def

0.4-Def

0.3-Def

0.3-Def

SEQUOIA

RET EffectsBIM,BIM+OPC,PSM+OPC

BIM, 0-Def

BIM, 0.3-Def BIM+OPC, 0.3-Def PSM+OPC, 0.3-Def

BIM+OPC, 0.4-Def PSM+OPC, 0.4-DefBIM, 0.4-Def

SEQUOIA

Timing Results

0.00E+00

2.00E-10

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

Net27 Net28 Net29 Net30 Net31

Ideal

psm_Defocus_1

psm_Defocus_2

psm_Defocus_3

psm_Defocus_4

0.00E+00

2.00E-10

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

1.60E-09

Net27 Net28 Net29 Net30 Net31

Ideal

Bin_Defocus_1

Bin_Defocus_2

Bin_Defocus_3

Bin_Defocus_4

0.00E+00

2.00E-10

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

Net27 Net28 Net29 Net30 Net31

Ideal

psm_Defocus_1

psm_Defocus_2

psm_Defocus_3

psm_Defocus_4

0.00E+00

2.00E-10

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

Net27 Net28 Net29 Net30 Net31

Ideal

psm_Defocus_1

psm_Defocus_2

psm_Defocus_3

psm_Defocus_4

0.00E+00

2.00E-10

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

1.60E-09

Net27 Net28 Net29 Net30 Net31

Ideal

Bin_Defocus_1

Bin_Defocus_2

Bin_Defocus_3

Bin_Defocus_4

•BIM

• First Technique – (Rachid’s gate averaging)

• Primarily a catastrophic Yield issue

• Leakage from line end shortening not considered

• Some transistors are outside of the model bounds

SPICE Results

SEQUOIA

Electrical Analysis of Proximity Effects

Active devices Active devices (MOSFETs) (MOSFETs) responsible for circuit responsible for circuit variabilityvariability

Root cause of Root cause of variability in sub-variability in sub-130nm mosfets is 130nm mosfets is MOSFET geometry MOSFET geometry (CD control)(CD control)

Geometry is the result Geometry is the result of mostly deterministic of mostly deterministic effects and effects and predictablepredictable

Line-end pullback causes MOSFET leakage -> Yield Problem

SEQUOIA

Impact of Process Variation

Process variation causes Process variation causes image degradationimage degradation

Defocus process window Defocus process window is important for is important for manufacturabilitymanufacturability

Shown is the aerial Shown is the aerial image of the poly layer at image of the poly layer at increasing defocusincreasing defocus

Gate length variation and Gate length variation and line-end pullback cause line-end pullback cause MOSFET parameter MOSFET parameter variation and failurevariation and failure

Defocus degrades image

No defocus

0.2um defocus

SEQUOIA

Electrical Impact of Proximity Effects

Proximity effects cause Proximity effects cause distortion depending on distortion depending on shape and environment shape and environment of featuresof features

Short poly segments Short poly segments (small mosfet W) print (small mosfet W) print differently from long onesdifferently from long ones

Proximity of other gates Proximity of other gates impacts gate shape and impacts gate shape and electrical performanceelectrical performance

Context of a mosfet must Context of a mosfet must be considered when be considered when predicting its propertiespredicting its properties

Defocus degrades image

0.15um defocus

0.2um defocus

SEQUOIA

MOSFET Variability and Yield

Defocus causes the Defocus causes the gate length gate length distribution to widen distribution to widen and shift to shorter and shift to shorter gatesgates

Circuit failure Circuit failure results from strong results from strong MOSFET MOSFET parameter variationparameter variation

In extreme cases In extreme cases Source/Drain shorts Source/Drain shorts (=very short gates) (=very short gates) cause functional cause functional failure failure

MOSFET Gate Lengths

MOSFET Idsat

0.1um defocus

0 defocus

0.1um defocus

0 defocus

SEQUOIA

Failure Outside Process Window

Failure is observed Failure is observed as zero-length as zero-length MOSFET by the MOSFET by the verification toolverification tool

SPICE timing SPICE timing analysis confirms analysis confirms circuit failure in this circuit failure in this casecase

Statistical analysis of Statistical analysis of MOSFET distribution MOSFET distribution across process across process window can be used window can be used to predict to predict manufacturability manufacturability

MOSFET Gate Lengths

0.2um defocus

Zero-length gates: Failures

SEQUOIA

Conclusions Current state-of-art EDA design and verification tools have

insufficient predictive performance capability in the Nanometer Era – Timing , SI, Race Conditions… +/- %100

These factors are also responsible in great part for costly fabrication re-spins – >%30 ! . Failure Costs are high!

Residual design-to-silicon distortions are a fact of life and must be accounted for in Nanometer Era

Design and verification tools must account for increased process and device physics entanglement. Verification must consider the impact of process proximity and process variation on circuit performance

Continuation of historical cycle, impact however is greater now than ever before

A novel verification methodology is proposed as a unique new adjunct to DFM and MSO flows to reduce costly re-spins and improve inherent design quality and manufacturability.

Catch Potential Re-Spin Failures Before Mask and Silicon !

SEQUOIA

Acknowledgements

Thank you Chris and Ed at KLA-Tencor/Finle for RC Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for ‘Gold-Standard’ confirmation and Pack use of Prolith for ‘Gold-Standard’ confirmation and future workfuture work

Thank you Vinod and Fabio at Numerical Technologies Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and for RC Pack use of IC Workbench for confirmation and future workfuture work

SEQUOIA

Additional Supportive Materials

SEQUOIA

‘‘Naive’ Simulation-based OPC Naive’ Simulation-based OPC Can make ‘pretty pictures’ on silicon but impact the real process Can make ‘pretty pictures’ on silicon but impact the real process

windowwindow At some level of k1, the context of the circuit and the device At some level of k1, the context of the circuit and the device

must be considered carefullymust be considered carefully Many digital circuits are very forgiving of some levels of distortion.. Many digital circuits are very forgiving of some levels of distortion..

but unforgiving of othersbut unforgiving of others Analog circuits/devices have their own special considerationAnalog circuits/devices have their own special consideration

Increased design-process integration care must be taken … it’s Increased design-process integration care must be taken … it’s not just about not just about makingmaking ‘pretty pictures’ on silicon ‘pretty pictures’ on silicon

Judicious and minimal usage of OPCJudicious and minimal usage of OPC Optimization target must be performance & Yield across Optimization target must be performance & Yield across

Process-window.Process-window.

SEQUOIA

Important issues for Designers, EDA, Maskmakers, lithographers, device designers, manufacturing…

Entanglement of traditionally separable entities.Entanglement of traditionally separable entities. The determination of which features are The determination of which features are

dimensionally and visually good enough must be dimensionally and visually good enough must be done on the basis of the feature function and IC done on the basis of the feature function and IC operational and manufacturing requirements.operational and manufacturing requirements.

Visual metrics are no longer sufficientVisual metrics are no longer sufficient This era require new tools, new standards, new This era require new tools, new standards, new

infrastructure….. infrastructure….. For EDA…It’s not just about wire RLC and For EDA…It’s not just about wire RLC and

parasitics parasitics

SEQUOIA

Acknowledgements

Thank you Chris and Ed at KLA-Tencor/Finle for RC Thank you Chris and Ed at KLA-Tencor/Finle for RC Pack use of Prolith for ‘Gold-Standard’ confirmation and Pack use of Prolith for ‘Gold-Standard’ confirmation and future workfuture work

Thank you Vinod and Fabio at Numerical Technologies Thank you Vinod and Fabio at Numerical Technologies for RC Pack use of IC Workbench for confirmation and for RC Pack use of IC Workbench for confirmation and future workfuture work