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Seminar on High-Speed Seminar on High-Speed Asynchronous PipelinesAsynchronous Pipelines

Montek SinghMontek Singh

Thursdays 10-11, SN325Thursdays 10-11, SN325

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Lecture 1: IntroductionLecture 1: Introduction

What is asynchronous design? Why do we What is asynchronous design? Why do we want to want to study it?study it?

What is pipelining? How can it be used to What is pipelining? How can it be used to

design design really fast hardware?really fast hardware?

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Introduction: Clocked Digital Introduction: Clocked Digital DesignDesignMost current digital systems are Most current digital systems are synchronous:synchronous:

Clock:Clock: a global signal that paces operation of all a global signal that paces operation of all componentscomponents

clockclock

Benefit of clocking: Benefit of clocking: enables discrete-time enables discrete-time representationrepresentation all components operate exactly once per clock all components operate exactly once per clock

ticktick component outputs need to be ready by next component outputs need to be ready by next

clock tickclock tickallows “glitchy” or incorrect outputs between clock ticksallows “glitchy” or incorrect outputs between clock ticks

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Microelectronics TrendsMicroelectronics TrendsCurrent and Future Trends: Current and Future Trends: Significant Significant

ChallengesChallenges

Large-Scale “Systems-on-a-Chip” (SoC)Large-Scale “Systems-on-a-Chip” (SoC)100 Million ~ 1 Billion transistors/chip100 Million ~ 1 Billion transistors/chip

Very High SpeedsVery High Speedsmultiple GigaHertz clock ratesmultiple GigaHertz clock rates

Explosive Growth in Consumer ElectronicsExplosive Growth in Consumer Electronicsdemand for ever-increasing functionality …demand for ever-increasing functionality …… … with very low power consumption (limited battery life)with very low power consumption (limited battery life)

Higher Portability/Modularity/ReusabilityHigher Portability/Modularity/Reusability““plug ’n play” components, robust interfacesplug ’n play” components, robust interfaces

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Challenges to Clocked DesignChallenges to Clocked DesignBreakdown of Single-Clock Paradigm:Breakdown of Single-Clock Paradigm:

Chip will be partitioned intoChip will be partitioned into multiple timing multiple timing

domainsdomains

Increasing Difficulties with Clocked Design:Increasing Difficulties with Clocked Design: Clock distribution: will require Clock distribution: will require significantsignificant designer designer

efforteffort

Performance bottleneck: a single slow componentPerformance bottleneck: a single slow component

Clock burns large fraction of chip powerClock burns large fraction of chip power

Fixed clock rate: poor match forFixed clock rate: poor match fordesigning designing reusable componentsreusable components interfacing with interfacing with mixed-timing environmentsmixed-timing environments

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What is Asynchronous Design?What is Asynchronous Design? Digital design with Digital design with no centralized clockno centralized clock Synchronization using local Synchronization using local “handshaking”“handshaking”

Synchronous SystemSynchronous System

(Centralized Control)(Centralized Control)

Asynchronous SystemAsynchronous System

(Distributed Control)(Distributed Control)

handshakinghandshakinginterfaceinterface

clockclock

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Why Asynchronous Design?Why Asynchronous Design? Higher PerformanceHigher Performance

May obtain “average-case” operation (not “worst-May obtain “average-case” operation (not “worst-case”)case”)

Avoids overheads of multi-GHz clock distributionAvoids overheads of multi-GHz clock distribution

Lower PowerLower Power No clock power expendedNo clock power expended Inactive components consume negligible powerInactive components consume negligible power

Better Electromagnetic CompatibilityBetter Electromagnetic Compatibility Smooth radiation spectra: Smooth radiation spectra: no clock spikesno clock spikes Much less interference with sensitive receivers Much less interference with sensitive receivers [e.g., [e.g.,

Philips pagers]Philips pagers]

Greater Flexibility/ModularityGreater Flexibility/Modularity Naturally adapt to varied environmentsNaturally adapt to varied environments Supports reusable componentsSupports reusable components

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Challenges of Asynchronous Challenges of Asynchronous DesignDesign

communication must be hazard-free!communication must be hazard-free! special design challenge =special design challenge = “hazard-free synthesis”“hazard-free synthesis”

Testability Issues:Testability Issues: absence of clock means no “single-stepping”absence of clock means no “single-stepping”

Lack of Commercial CAD Tools:Lack of Commercial CAD Tools: chicken-and-egg problemchicken-and-egg problem

Hazards: Hazards: potential “glitches” on wirepotential “glitches” on wire

clean signalsclean signals

hazardous signals

clockclock tick tick

no problemno problemfor for clockclockededsystemssystems

no problemno problemfor for clockclockededsystemssystems

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Asynchronous Design: Past & Asynchronous Design: Past & PresentPresentAsync Design: Async Design: In existence for 50 years, but … In existence for 50 years, but …

… … many recent technical advances:many recent technical advances: Hazard-Free Circuit Design:Hazard-Free Circuit Design:

several practical techniques for controllers several practical techniques for controllers [Stanford/Columbia][Stanford/Columbia]

Design for Testability:Design for Testability:several test solutions, e.g. Philips Researchseveral test solutions, e.g. Philips Research

Maturing Computer-Aided-Design (“CAD”) Tools:Maturing Computer-Aided-Design (“CAD”) Tools:software tools for automated design software tools for automated design

[Philips,Columbia,Manchester][Philips,Columbia,Manchester]

Successful Fabricated Chips:Successful Fabricated Chips:embedded processors, high-speed pipelines, consumer embedded processors, high-speed pipelines, consumer

electronics…electronics…

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Recent Commercial InterestRecent Commercial InterestSeveral commercial asynchronous chips:Several commercial asynchronous chips:

Philips: Philips: asynchronous 80c51 microcontrollersasynchronous 80c51 microcontrollersused in commercial pagers [1998] and cell phones [2000]used in commercial pagers [1998] and cell phones [2000]

Univ. of Manchester: Univ. of Manchester: async ARM processor [2000]async ARM processor [2000] Motorola: Motorola: async divider in PowerPC chip [2000]async divider in PowerPC chip [2000] HAL: HAL: async floating-point dividerasync floating-point divider

in HAL-I and II processors [early 1990’s]in HAL-I and II processors [early 1990’s]

Recent experimental chips:Recent experimental chips: IBM, Sun and Intel:IBM, Sun and Intel:

fast pipelines, arbiters, instruction-length decoder…fast pipelines, arbiters, instruction-length decoder… IBM/Columbia Univ.: IBM/Columbia Univ.: asynchronous digital FIR filterasynchronous digital FIR filter

Several recent startups:Several recent startups: Theseus Logic, ADD, AmuCo…Theseus Logic, ADD, AmuCo…

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Seminar FocusSeminar FocusOverall Goal:Overall Goal:

Asynchronous Design for Asynchronous Design for Very High-SpeedVery High-Speed SystemsSystems

Focus:Focus: High-Throughput PipelinesHigh-Throughput Pipelines

Motivation:Motivation: Pipelining is at the heart of nearly allPipelining is at the heart of nearly all high-performance digital systemshigh-performance digital systems

Additional Benefits:Additional Benefits: Low powerLow power Interfacing with mixed systemsInterfacing with mixed systems Modular and scalable designModular and scalable design

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A “coarse-grain” pipeline (e.g. simple processor)A “coarse-grain” pipeline (e.g. simple processor)

A “fine-grain” pipeline (e.g. pipelined adder)A “fine-grain” pipeline (e.g. pipelined adder)

fetchfetch decodedecode executeexecute

Background: PipeliningBackground: PipeliningWhat is Pipelining?: What is Pipelining?: Breaking up a complex Breaking up a complex

operation on a stream of data into simpler operation on a stream of data into simpler sequential operationssequential operations

++ Throughput: Throughput: significantly increasedsignificantly increased–– Latency:Latency: somewhat degradedsomewhat degraded

Storage elementsStorage elements(latches/registers)(latches/registers)

Throughput = #data items Throughput = #data items processed/secondprocessed/second

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Seminar Focus (contd.)Seminar Focus (contd.)Particular Focus:Particular Focus: Extremely fine-grain pipelines Extremely fine-grain pipelines

““gate-level”gate-level” pipelining = use narrowest possible stages pipelining = use narrowest possible stages

each stage consists of only a each stage consists of only a single levelsingle level of logic gates of logic gates

some of the fastest existing digital pipelines to datesome of the fastest existing digital pipelines to date

Application areas:Application areas: multimedia hardware (graphics accelerators, video DSP’s, multimedia hardware (graphics accelerators, video DSP’s,

…)…)naturally pipelined systems, throughput is criticalnaturally pipelined systems, throughput is critical

input is often “bursty”input is often “bursty”

optical networkingoptical networkingserializing/deserializing FIFO’sserializing/deserializing FIFO’s

genomic string matching?genomic string matching?KMP style string matching: KMP style string matching: variablevariable skip lengths skip lengths

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Homework ProblemHomework ProblemAliceAlice and and BobBob live on opposite sides of a wide river: live on opposite sides of a wide river:

AliceAlice is supposed to send a message (say, a “Yes”/”No”) is supposed to send a message (say, a “Yes”/”No”) across to across to Bob Bob around midnight. Both have flashlights, around midnight. Both have flashlights, but neither owns a watch. What should they do?but neither owns a watch. What should they do?

Suggest several strategies, and discuss pros and cons of Suggest several strategies, and discuss pros and cons of each.each.

AliceAlice

BobBob