Semiconductor Technology & Manufacturing Status,Challenges, and Solutions - A New Paradigm in the Making

C. R. Helms

International SEMATECHAustin, Texas

Present Address: University of Texas at DallasP.O. Box 830688, EC32

Dallas, Texas 75083-0688

Abstract. The phenomenal growth of the semiconductor industry has been made possible by our ability to delivermore functionality at a lower and lower cost, with a reduction in cost per function of approximately 25% per year.Technology advancements have also enabled higher performance, lower operating voltages, and associated lowerpower consumption. Dimensional shrinks based on 248 nm lithography led the revolution in recent years. However,with the fundamental limit for optical lithography at about l/3rd the wavelength, the limits for 193 nm and 157 nmlithography are about 65 nm and 50 nm respectively. With EUV and most other NGL technologies 7 years in the futurethe limit for the remainder of the decade is about 50 nm. Technology challenges, whether they are lithographic innature or based on needed new materials with advanced properties, are summarized in this paper along withsuggestions for potential solutions for the remainder of the decade. Even if we meet the technology challenges,continued revenue growth and profitability will become more and more challenging. The need for larger and largertechnology R&D budgets may make it difficult for the current number of semiconductor manufactures and equipmentand materials suppliers to remain profitable. The solution to this conundrum is now clear - partnerships andcollaboration. Meeting this challenge of creative cooperation with existing and new partnerships is the new paradigmthat is discussed here in some in detail.

INTRODUCTION

Growth in revenue and continued and improvedprofitability is a benchmark for any industry, leading tohigh valuations with significant multiples. We haveseen enormous revenue growth in the semiconductorindustry with a compounded annual growth rate(CAGR) of 17% over 30 years in the 60's, 70's, and80's. This growth was comprised of two components,growth in unit shipments and growth in average sellingprice (ASP). Unit shipments increased at a CAGRgreater than 10%, with ASP's increasing at a rategreater than 5% during this period. At the end of the80's the industry had become a major force in theglobal economy with revenues of $50B on shipmentsof 120B units.

The 90's saw some major shifts in the industry.DRAM's, which had been the critical driver fortechnology advancement and revenue growth, werereplaced by the microprocessor. Various pricing

pressures also led to stagnation in the growth of ASP'sthat peaked in late '95. On the technology sideimprovements in manufacturing productivity alsobegan to saturate leading to a wafer size change from150mm to 200mm and an increase in the shrink ratefrom a 30% reduction every 3 years to a 30% reductionevery 2 years. Significant improvements inlithography enabled this revolution, with the move tothe 248 nm wavelength and a move from steppers toscanners late in the decade.

Given the technical and business challenges,exacerbated by the poor global economy in 2001 and2002, some argue that the heyday of semiconductors isover and that the industry needs to focus on a situationwhere minimal unit growth will continue to becompounded by falling ASP's, leading to a relativelyflat revenue picture. There is little question that the17% CAGR seen over 3 decades cannot not besustained indefinitely. Indeed, the semiconductorindustry is beginning to show signs that it is enteringinto a more mature phase.

CP683, Characterization and Metrology for VLSI Technology: 2003 International Conference,edited by D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, R. P. Khosla, and E. M. Secula

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How well each company or institution responds tothese business and technical challenges will determinesuccess or failure. Speed of technology developmentand introduction at the lowest possible cost will be acritical differentiator. Both of these factors are drivingbusiness and technical leaders to enter into partnershipsand alliances that would have been unthinkable even afew years ago. Those who embrace this new paradigmwill be successful and be able to ride the wave ofrevenue growth I believe we will continue to seethrough the end of the decade.

The first topic of discussion here will be therevenue picture of the semiconductor industry and whathistory can tell us about the future. Industry roadmapswill be our next topic, but with a slightly differentfocus than we normally think of from the InternationalTechnology Roadmap for Semiconductors (ITRS) [1].The discussion of roadmaps naturally leads to thediscussion of technology challenges, the R&D cost toovercome these challenges, and finally the move toR&D partnerships.

SEMICONDUCTOR REVENUEHISTORY & EXTRAPOLATION

This topic has been discussed in numerous forumsover the years. A critical strategic question forbusiness leaders is how fast will the semiconductorindustry mature and thus, what level of revenue growthis likely. Given that such phases for other industriessuch as steel, autos, electrical power generation anddistribution, telephone communication, etc. can takemany decades, I would argue that although we may bein the early stages of this maturation, we have a longway to go at very healthy growth rates. To see theevidence for this statement, let's first look at the long-term picture for revenue growth shown in Fig. 1. Atfirst glance the revenue curve appears linear on thisgraph. Indeed for the 70's well into the 80's there is alinear CAGR of 17%. However, if that line wereextrapolated we would find it crossing $500B by 2005.Even the wildest optimist would not predict $500B in2005! Furthermore, it is not difficult to see how somebelieve that the revenue picture has been flat and maycontinue in the same vein. If we look at the revenuepicture since 1995, discounting 2000, one can easilydraw that conclusion.

1000Models Based on Growth of

- Auto Industry 1900 - 2000

1970 1975 1980 1985 1990

Year1995 2000 2005 2010

FIGURE 1. Total semiconductor industry revenue from 1970 to 2002 is plotted as the solid diamonds. A model based on thematuration of industries such as autos is shown as the line, with a cyclical component as the gray diamonds.

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However, that analysis is clearly somewhat artificialand it is difficult to understand how the CAGR of awhole industry would change from around 15% upthrough the mid 90's to zero all in one year. Thematuration cycle for most industries is many decades.

We are beginning to see a maturation for thesemiconductor industry, which is evident if we inspectFig. 1 carefully. The line drawn through the data is amodel based on saturation in growth not unlike whatother industries experienced in the last century (i.e.autos). The "model" indicates that the growth rate wasindeed 17% on average in the 70's, 16% in the 80's,14% in the 90's and projects to be 10% on average forthis first decade of the new millennium. The cyclicalnature of this growth industry is also apparent, with aperiodicity of 5 years. For example local peaks (orinflections) occur in 1974, 1980, 1984, 1990, 1995, and2000, approximately every 5 years. If we extrapolateto 2005, near-term growth rates should reach or evenexceed 20% per year. A word of caution is appropriatein that these models are based solely on historicalanalysis and extrapolations and could be impacted bymajor economic forces external to the semiconductorindustry itself. I note, however, that there are a numberof predictions in a similar range [2].

From the above discussion I draw threeconclusions. First, we are clearly seeing thebeginnings of maturation of growth of thesemiconductor industry. Second, this maturation willtake place relatively slowly leading to expectedaverage revenue growth rates around 10% per yearthrough the end of the decade as a likely scenario.Third, the cyclical nature of the industry should lead torevenue growth averaged over the next 3 years ofaround 20% per year as we move from a local bottomin late-2001/early-2002 to another top in 2005. We canonly hope that the next downturn predicted for thelatter half of the decade will not be quite so rapid (andquite so deep) as the one we are currently experiencing.

Revenue growth has been driven historically bydeeper penetration of markets by continuing pricereductions on the one hand and by the development ofwhole new classes of products enabled by lower costs,better performance, high memory capacities, and lowerpower consumption. In the next section I will discussprojections of these success factors based primarily onthe ITRS, with additional reference to projectedproduct requirements.

REALIZING THE RIGHT ROADMAP

The semiconductor industry is probably the mostadvanced in history in establishing technologyrequirements and schedules through a global,

formalized technology roadmap, the InternationalTechnology Roadmap for Semiconductors (ITRS). Itis useful, however, to expand the discussion all the wayup the value chain to semiconductor products and endequipment. A roadmap hierarchy, including thesefactors is shown in Fig. 2. From the perspective of theintegrated device maker (IDM) or fables ssemiconductor house the end equipment markets theychoose to serve and the products that they will sell intothese end markets are, by far, the most importantconsiderations. The hierarchy continues down throughmodules that will be needed for each chip, the highlevel specifications associated with the modules andoverall chip, the architecture to be used, the materialsand structures needed to support the architecture, andfinally the processes and tools needed to deliver thematerials and structures. Working our way down thehierarchy drives the requirements level-by-level,leading to solutions as we move back up the hierarchy.Out of the 7 levels shown in the Figure, the ITRS dealsprimarily with the bottom four. It is important torealize that an IDM that can meet or beat therequirements associated with the top 4 levels ofhierarchy will win independent of the details of thetechnology solutions provided. This is where much ofthe competitive advantage for IDMs lies today.

In the context of an organization like InternationalSEMATECH or the equipment and materials suppliers,"realizing the roadmap" normally applies to the lowertwo categories of the hierarchy. A focus on the bottomof the value chain in this manner can, however, lead tosignificant risk. If a solution is found higher up thevalue chain, the there may be no need for a lower levelrequirement, let alone solution. The best example ofthis occurring in recent years is for low-K interconnectdielectrics. The 1997 ITRS indicated aREQUIREMENT for interconnect structures this year(2003) with effective dielectric constants in the rangeof from 1.5 to 2.0. Indeed the use of such effectivedielectric constants in mainstream technologies is yearsaway (possibly not even in this decade). If this were atrue requirement, we would not be shipping 130nmproduct today let alone 90/1 OOnm class products thisyear. So, when we look at lower level roadmaps weneed to realize that there is a possibility that abreakthrough at a higher level may mitigate the needfor a specific requirement or solution at the lower level.

Although the top levels of the roadmap hierarchyshown in Fig. 2 are beyond the scope of this paper afew comments are appropriate as paradigm shifts at thehigher levels do have a major impact. The mostsignificant change that we see is the move to moreintegration, either in package or on-chip.

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Requirements

End Equipment (PCs, DVDs, Hand-helds, Wireless)

Products (|iPU, DRAM, DSP, Baseband)

Modules (Logic, Memory, Analog)

Specifications (VDD, Freq., Pwr.,Cost, Lifetime)

Layout/Architecture (Random,Gate Array, Logic-Based,

Memory-Based)___Materials/Structures

(Cu,LowK,SOI,1/2 Pitch)

\Processes/Tools/(193nm,CMP),

Solutions

FIGURE 2. Roadmap hierarchy for the semiconductor industry, from end equipment at the top of the value chain to processesand tools at the bottom. The ITRS focuses mainly on the bottom four segments of the value chain shown here.

The integration of processor cores with on-chipSRAM (and flash) has been a common practice for anumber of years. Logic with embedded DRAM,even given all the process complexities is alsoappearing in mainstream products. Stacked die are aserious contender for applications that need powerfulprocessing on the one hand and significant capacityfor fast DRAM. More and more analog functionalityis also appearing in hand-held and wireless chips andsome believe that a true system-on-a-chip (SoC) willarrive soon (single chip phone, radio, etc.). Themove to SOI, Si-Ge, and alternate memorytechnologies such as embedded MR AM, FeRAM,and other alternate memories may accelerate thismove toward SoC's.

With this in mind, we will however limit thediscussion here to the bottom four categories of theroadmap hierarchy, noting that cost - bothmanufacturing and R&D cost - is a natural part ofthis discussion. A critical part of the roadmaps and,indeed, a critical driver for many of theimprovements delineated in any roadmap is related tocost reductions that have historically been necessaryto open new markets and drive further penetration inexisting markets. If we combine the potential forrevenue growth and the cost associated with thisrevenue growth we have almost the totality of the

financial model for a chip maker. Thus, in manyways, the cost roadmap may be the most critical ofall. Manufacturing cost (per chip, per function, andper unit area) and R&D cost are the two dominantfactors that must be considered. The former must beintegrated over the life of the facilities and equipmentused and also must comprehend fluctuations infactory loading that will lead to an average utilizationwell below 100%. The $3+B cost of a new 300mmfactory has now limited the number of companiesthat can afford to be independent devicemanufacturers down to the 5 - 1 0 range (>$5B insemiconductor revenues). We will discusstechnology R&D cost later. However, this may beeven a more serious limitation for firms that seek tobe tier-1 leading edge producers [3].

The model developed at InternationalSEMATECH to assess manufacturing cost beaks theproblem into two fundamental componentsfunctionality per unit area and cost per unit area [4].Furthermore if we assume that functionality is relatedto the number of transistors, then it is easy to analyzethe cost per function by comprehending the cost perunit area and transistors per unit area and dividingone by the other. Again caution is necessary here. Ifmore functionality can be delivered with the samenumber of transistors, this simple analysis will beflawed. Thus any reduction in the number of

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components for a particular application enabled bySoC or system-in-package (SIP) concepts willgenerate significantly improved functionality per chipor per unit area without the need for either increasedtransistor density or reduction in manufacturing costper wafer or per unit area.

Another example is the move from processorswith embedded SRAM to chips with processors plusembedded DRAM. Typical SRAM cells contain 6transistors (6T cell); if that number can be reducedwithout a significant cost sacrifice, the cost perfunction will obviously drop. One approach is toreplace much of the SRAM with embedded DRAM;unfortunately the process integration challenges herehave not provided the ability to use this technique formany mainstream applications, since lower yieldsand longer development cycle-times mitigate the costsaving.

Until about 1995 a good part of the improvementin cost per function was driven by improvements infab and process productivity through yieldimprovements and overall improvement in equipmentproductivity. Two other important factors werewafer size changes that occurred about every 10years and shrinks that provided a 2x improvement intransistor density every 3 years. The improvementobtained by a combination of these factors wasbetween 20 and 30% per year in cost per transistor.In the mid-90's, however, the low hanging fruit forglobal yield improvements and equipment andoverall fab productivity had been harvested.Furthermore, the move to 200mm wafers was wellunderway, but improvements possible from the move

to an even larger wafer size were a number of yearsoff. Thus, the year-by-year rate of cost per functiondecrease had fallen and was in the low 20% per yearrange.

As we approached the mid-90's the industry waslosing one of its historical growth advantages, the25+% per year cost per function reduction. Torestore the productivity curve to this trend, theindustry accelerated the shrink roadmap from a 3-year cycle to a 2-year cycle. Many argue that this hasnot yielded to benefits promised; however, in myview, the benefits are clear. We can see this bylooking at a cost comparison analysis shown inFigure 3.

We start with the premise that a 25% per yearreduction in cost per function is the target and seek tounderstand how the various factors will lead to thisnumber. The advantage of the 2-year roadmap cyclein terms of manufacturing cost is obvious since therate of increase in functions (transistors) per unit areagoes from 25% per year for the 3-year cycle to 40%per year with the 3-year cycle! All of this benefit isnot realized however, since there will be differentialmanufacturing cost increases between the 2-year and3-year cycles. International SEMATECH studiessuggest that the manufacturing cost at constant wafersize has increased at about 4% per year for a 3-yearcycle (since about 1990) and increases to 8% year forthe 2-year cycle. In the 70's and 80's themanufacturing cost per unit area had actually beendecreasing due to significant improvements in yield,yield ramps, and overall fab productivity advances.

Productivity Factors 2-Year Cycle 3-Year Cycle

Required Annual Manufacturing Cost perFunction Decrease 25% per Year 25% per Year

Annual Transistor per Unit Area Increase

Nominal Annual Manufactruing Cost per UnitArea Increase - Constant Wafer SizeAverage Annual Reduction for Wafer SizeConversion Every 10 Years

40% per Year

8% per Year

4% per Year

25% per Year

4% per Year

4% per Year

Predicted Annual Manufacturing Cost perFunction Decrease

27% per Year 21% per Year

FIGURE 3. Comparison of cost factors between a 70% every 2 years and 70% shrink every 3 years.

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As discussed above, however, the industry hasmatured to the point where these factors no longerprovide the benefits of the early years. Finally, wecan put the complete cost picture together bycomprehending the long term, average benefits of awafer size change every 10 years, which are found tobe about 4% per year.

This analysis shows that the 3-year cycle can beexpected to generate a cost reduction of 21% per yearcompared to the 27% per year cost per functionreduction of the 2-year cycle. Figure 4 shows thebenefits of both the move to the 2-year roadmapcycle as well as the wafer size change for cost pertransistor for leading edge logic products from 1995to the present and projected out to 2005. Thediamonds are results from analysis of data availableand extrapolations into the future for the lowest costnode (and wafer size) for any given year for volumeproduction. The trend-lines show a slope that isabout 20% per year from 1995 through 1998 anddrops to 27% per year from 1998 to 2005. Thebreakpoint in 1998 is due almost completely to themove to the 2-year roadmap cycle (the 0.25|Lim nodewas the first node to be developed in 2 years). The300 mm wafer size is projected to be the lowest cost

manufacturing solution in 2004 for 130 nmtechnology. This projection, made in 2001, isconsistent with recent information from the leadingedge chip-makes with 300 mm factories [5]. Thus,the need for both the 2-year roadmap cycle as well asa wafer size change every 10 years is well establishedif we are to continue to achieve a 25% per yearmanufacturing cost per function.

Unfortunately manufacturing cost is not the onlyissue. The increased rate of research anddevelopment needed to support the acceleratedroadmap cycle and its associated cost can be amitigating factor. The technical challenges faced byour R&D communities will be discussed next; theR&D cost situation will be discussed later in thepaper.

TECHNOLOGY CHALLENGES

The discussion to this point has focused on theneed to shrink transistor dimensions at an ever-increasing rate which was 11% per year for most ofour history (3-year shrink cycle) and is now 16% peryear (2-year shrink cycle).

CO

3UL

COoO

20% per YearReduction

Leading Edge LogicProducts

27% per YearReduction

0.13 urn300mm

1995 1997 1999 2001Years

2003 2005

FIGURE 4. Cost per transistor is shown on a relative scale for leading edge logic products. The black diamonds are the resultsof the model calculation, validated by industrial average data. The large diamonds indicate a cross-over year where the latesttechnology has matured to the point of being lowest cost (i.e. 0.25 micron technology became a lower cost technology than 0.35micron technology in 1999). The gray diamonds are an extrapolation. Note that the year when 300 mm manufacturing ispredicted to be lowest cost is 2004. A break point in 1998 due to the move to 2-year shrink cycles is indicated.

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This has been accomplished over the last decade,even though the critical level exposure wavelengthhas remained at 248nm. This >3x improvement inresolution has been enabled by a 50% increase in thenumerical aperture of the exposure tools, processcontrol advancements, and numerous resolutionenhancement techniques (RET's), includingaggressive phase shift mask technologies, with areduction in the Kl factor by nearly a factor of 2.Thus what was once thought as an insurmountablebarrier - critical dimensions less than the wavelength- was broken in 1995. The year 2002 saw the l/2wavelength barrier also broken. The history andprojections are shown in Figure 5. However, giventhat the industry has a history of breaking barriersonce thought to be impenetrable, the ultimate limit asa fraction of the lithography wavelength is not clear.The l/2 and l/3rd wavelength regions are, however,indicated in the Figure.

The reduction in critical dimension as a fractionof wavelength, especially given the difficulty driving193 nm technology into the mainstream until mid-lastyear, and potential delays for 157 nm, are providingpressure for more aggressive RET's and mask

technology. Thus, masks - availability, cost, andcycletime - are considered the #1 technical challengefaced by the industry today and in the near future [1].

Mask and the other top technology challenges forthe next few years are listed in order of perceivedimportance and difficulty:1. Mask availability, cost, and cycletime.2. Post-193 nm exposure tools and infrastructure.3. Compatible materials and processes to enable

continued improvements in transistorperformance and power consumption.

4. Design methodologies and interconnect materialsand processes to enable continued improvementsin circuit complexity, wiring density, andperformance.

5. New materials, processes, and structures toenable the move to more on-chip integration at alow cost. (i.e. low cost embedded memory).As just discussed the advances in mask

technology needed are significant indeed,exacerbated by the delay in mainstream applicationof 193 nm technology and the risk of additionaldelays in the availability of post-193 nm exposuresystems and infrastructure.

800

400

300mO 200

100

Year2014

FIGURE 5. 2-year node dimensions are plotted as a function of time as diamonds; the trend-line is also shown. The dark line isan indication of the availability of lithography wavelengths in the past, with projections for the future. Regions where the criticaldimension falls below l/2 and l/3rd of the wavelength are indicated.

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This is driving not only mask challenges but alsochanges in design methodology and architecture thatmay be necessary to achieve the needed increases inperformance and functions per unit area. Given therelatively constant field size and magnification factor,the increased feature density, improvement inresolution of features on the mask, and improvedtolerances are providing a significant technicalchallenge. Coupled with the desire to have cycletimesthat are measured in hours, the task is daunting indeed.The use of significant optical proximity correction(OPC) and more recently attenuated and alternatingphase shift has also increased the complexity. Thereare significant issues across the entirety of mask-making infrastructure including pattern generation(mask writers), mask inspection, and mask repair. Fornon-classical technologies (i.e. EPL and EUV)fundamental materials issues are also on the criticalpath. The introduction of phase shifters in mainstreamtechnology has led to the requirement to projectfeatures that may be < 1A of the wavelength (even ifthey are not resolved directly).

All of these issues have led to poor yield, difficultyin achieving first-pass success, long cycletimes, andassociated high costs. 130 nm-class technology maskcosts have ranged up to over $1M and are on the orderof $500K today. There are projections that the costscould continue to escalate, doubling every generation(per 30% reduction in linear dimension). Thus aproduction mask set for 90nm-class technology couldreach $2M this year dropping to $1M in 2005; a set for65nm-class technology would be $4M in 2005,dropping to $2M in 2007, and so on.

The mask cost is, of course, important for alltechnologies. However, for large volume products thatmay require thousands or tens of thousands of wafersthe overall impact is significantly reduced. For a $1Mmask set and a 10,000 wafer run, the cost associatedwith the mask set is $100 per wafer. This may not bedesirable, but it is not a total showstopper. Thus forlarge volume microprocessors, DRAMs, and chips forconsumer products, the mask cost can beaccommodated. For product runs that consume fewerwafers, the mask cost alone may drive to other lowercost approaches. Some of the tradeoffs are illustratedin Figure 6. The fabrication cost per unit areaincluding one full mask set is plotted vs. the number ofwafers in the run (see the Fig. caption for assumptions).The cost cross-over for the assumptions used is about500 wafers between the advanced technology solution(solid black line) and the solution based on theprevious node technology (and thus lower mask cost).Note this comprehends only the manufacturing cost forone mask set; any additional masks for prototypes, etcwill move the cross-over to larger run sizes.

The cost for another solution, based on a gate arrayis also shown. This analysis assumes that a gate arraywith appropriate functionality can be designed usingthe advanced technology with only a 30% area penalty(and no important performance penalty), with only10% of the cost of the mask set associated with theparticular custom product. In this case the cross-overis at about 1500 wafers and it always provides a lowercost than the full custom solution using the previousnode technology. Recent development and productannouncements seem to indicate that this strategy isgaining momentum for smaller wafer runs.

The rapid technological advancement that isneeded in pattern generation, mask inspection, maskrepair, and handling of large databases is also leadingto economic challenges for those firms that choose toservice this segment. The limited revenues available tothese equipment and software suppliers is beginning tofall short of what is required to pay for the associatedR&D cost to generate an appropriate return.

Is there a solution? We believe that the answer isyes. Mask cost (and cycletime) can be mitigated byyield improvement. And the financial issues associatedwith R&D at the mask maker as well as R&D at theirsuppliers can also be mitigated by strategicpartnerships and consortial activity. As I will discussbelow, however, firms must be willing to trade whatwould once be considered valuable intellectualproperty for reduced R&D cost and accelerateddevelopment cycles.

The challenges for masks relate directly to theoverall lithography problem. Looking back at Fig. 5,1am not projecting large scale use of 157nm until 2006or EUV until 2010. These projections are morepessimistic than other published reports but areconsistent with the development cycle for 193nmwhere I do not put large scale use until sometime lastyear (2002). Mask challenges are clearly a major partof the barriers to adoption of these technologies.However, there are other significant challenges as wellrelated to exposure tool materials and otherinfrastructure issues.

The final technology challenge from the list aboveis the need for new materials with improved propertiesto respond, in turn, to the need for improvedperformance, power consumption, and smallerdimensions. This need for new materials is increasingevery year. We have seen a move to tungsten for firstlevel metal and local interconnect, titanium and cobaltsilicide for contacts, copper interconnects, lowerdielectric constant materials for interconnect andbarriers, and nitrogen-containing dielectrics for higherdielectric constant applications. SOI substrates and

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$100,000

05

S*-»> $10,000'5O"UJoa.

oO

$1,00010 100 1000 10000

Advanced Technology Equivalent Wafers

FIGURE 6. Example cost per wafer is shown vs. the number of wafers per mask. The black solid line refers to a technologywith a $1700 cost per wafer w/o the mask set and a cost for the mask set of $1M. The black line with the large dashes refers tothe same product run at the previous node with a $1400 cost per wafer and $500K cost per mask set (twice as many wafers areneeded; the plot is shown in equivalent advanced technology wafers to comprehend the additional factor of 2). The gray dashedline refers to a product run with the advanced technology using a "gate array" approach assuming comparable functionality witha 30% area penalty and only 10% of the cost of the mask set custom for a particular product.

strained silicon and Si-Ge will be in the mainstream inthe near future.

One of the most significant challenges is the needfor a MOS dielectric stack with sufficiently smalleffective oxide thickness and parasitics on the onehand, but sufficiently low leakage currents on theother. Nitroxides will suffice for the 90nm node, but areplacement is highly desirable for the 65nm node,with production in 2005 [6].

In summary, we see the technical challenges of the90nm node being solved with 193nm lithography,significant use of phase shift mask technology,nitroxide gate insulators with cobalt silicide contacts,and Cu interconnect with nominal low K dielectrics.The 65nm node will be a significant challenge,especially if we expect to see significant productionvolumes in 2005. 157nm lithography will likely not beat the maturity level needed and the new materialssolutions for both front end and back end may also belagging. The technical challenges for the remainder ofthe decade will be no less daunting, especially forlithography. Breakthrough solutions such as electronprojection lithography, immersion lithography orperhaps nano-imprint technology show some promise,but the time window is closing. A significant level of

R&D resources will also be needed to deliver thesetechnologies. That is the topic of discussion for thenext section.

CHIP-MAKER R&D COST: THE RISEOF R&D PARTNERSHIPS

Even with improved productivity and co-locatedtechnology R&D and leading edge manufacturingfacilities, R&D costs are increasing at a significantrate. The factors are numerous, but the two dominantfactors in the recent past are the move to the 2-yearroadmap cycle and the acceleration in the introductionof new materials and lithography wavelengths. Themove of R&D to the 300mm wafer size is also adding asignificant cost as facilities are converted or built forthis purpose.

It is fairly easy to estimate the impact of the moveto the 2-year roadmap cycle. Assuming that the R&Deffort per node is comparable, the number of nodes thatare in active development increases by simplemathematics by 50%; thus the differential R&D costwill be 50% higher! For a large volume producer the

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improved manufacturing cost may well offset theincreased R&D expenditures, but there will clearly be achip-maker size (depending on product mix) belowwhich the additional R&D expense cannot be justified.

The actual technology R&D cost for a leadingedge chip-maker is a complex function of whatsegments of the market it serves. However, estimatesplace the baseline for silicon technology R&D at$150M per year in 1997, $250M in 1999, and $350Min 2001. This increase has been over 20% per year. Apart of this increase is due to the move to a 2-yearroadmap cycle. This has clearly added 5% to 10% peryear to these increases. However, the need to moveR&D to 300mm over the next few years will applycontinuing pressure, so the 20% increase per year mayproject through a good part of the decade. Thus,targets for 2003 and 2005 of $500M and $750M peryear are not out of the question.

Unfortunately, for an integrated devicemanufacturer, technology R&D is not even thedominant R&D cost, and may account for only l/3rd ofthe total. This places the revenues needed to supportleading edge silicon technology R&D in the $5B to$10B range, similar to that needed to support the moveto 300mm manufacturing. This, in turn, limits thenumber of firms capable of a completely independentR&D operation from 5 to 10. R&D partnerships andstrategic alliances are one way to reduce this costburden.

The concept of strategic alliances and partnershipsto mitigate cost and provide a more coherent voice todrive the industry agenda is a concept that has beenpracticed for 20 years are so. The most well knownearly programs were the formation of theSemiconductor Research Corporation (SRC) andSEMATECH in the mid-80's. One of the best knownprograms centered at an individual company was thememory partnership at IBM, including Infineon (thenSiemens) and Toshiba.

However, the high cost of both manufacturing andR&D has made the participation in such partnershipsan economic necessity for many companies that are notin the $5B to $10B revenue club. InternationalSEMATECH in the US, Selete in Japan, and IMEC andCEA Leti in Europe all have multi-company programshoused in a central facility. There are numerousacademic programs and both federal and stategovernments are supporting R&D as well.

The biggest paradigm shift we see is thewillingness of competitors to trade what had been thepotential for valuable intellectual property for thepotential of lower cost R&D and also possiblyaccelerated development cycletimes. In thesemiconductor industry three large programs have beenannounced recently: one centered at

STMicroelectronics in Crolles, one centered at IBM inNew York, and one managed by Dupont Photomask inDresden. The first involves Motorola, Philips, andTSMC, and includes participation by CEA Leti; thesecond involves Infineon and AMD, with possibleparticipation of SUNY Albany; and the mask programinvolves AMD and Infineon. Thus we are seeing amajor strategy shift to R&D partnerships and alliancesto reduce cost and accelerate development cycletimes.As 300mm manufacturing matures it is conceivablethese R&D partnerships will also develop intopartnerships for volume manufacturing.

SUMMARY

In this paper I have tried to provide a snapshot ofthe silicon manufacturing segment of thesemiconductor industry from both a technical as wellas business prospective. Indeed, both are intimatelytied together. Probably the most significant claim Imake here is that with the exception of the top five toten integrated semiconductor companies and the largestfoundries, no one company will likely find a businessmodel to support leading edge silicon technology R&Dor the large 300mm factories needed for appropriatemanufacturing economies of scale. The two choicesfrom a business perspective are mergers andacquisitions to increase market share and revenues orinclusive partnerships and alliances. There arenumerous examples of both over the last year or so.

The technical challenges that are driving the largeinvestment in R&D relate to both the drive for smallerfeature lithography as well as new materials to deliverthe performance, lower power consumption, and higherdensities. The top near term challenges are masks andmask cost, maturation of 157nm lithography, and loweffective oxide thickness gate stacks, employing highK gate insulators.

REFERENCES

1. 2003 International Roadmap for Semiconductors,Semiconductor Industry Association (2002).

2. J. Feldham, as reported in the EE Times, 3/10/03(United Business Media)

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