Apr 11, 2023 1

Nabil Chouba

http://nabil.chouba.googlepages.com

Semiconductor overview

Apr 11, 2023 2

1947 : Point Contact Transistor 

BELL LABS : Bardenn, Brattain & Shockley

The Beginning

* William Shockley : 1956 Nobel Prize in Physics

Apr 11, 2023 3

Integrated Circuit from 1960 to 2010

1961 First planer IC"flip-flop"

2010 IBM POWER7 transistors: 1.2 B

Invented by Robert Noyce, Fairchild

*integrated circuit Invented by Jack Kilby, Texas Instruments

*cmos45, 5 GHz, cache, Dual DDR3 memory controllers Level 1 & 2 caches remain SRAM ,32MB eDRAM on-chip Level 3

Apr 11, 2023 4

Processor Evolution 1979 MOTOROLA 68000

the Most Powerful µp16-Bit 40k transistors

1971 Intel 4004 The First µp 4-Bit

2,25k transistors,24mm2

1976 Zilog Z80

the Most Popular µp 8-bit4,5k transistors

1993 Intel Pentium 32 bit3.1M transistors

2003 AMD Opteron 64 bit233M transistors

2008 AMD Barcelona Quad-Core 128 bit 463M transistors ,283 mm2

Apr 11, 2023 5

Moore's Law : 1960

-Number of transistors on integrated circuit : Doubling every two years.-RAM storage capacity & Power consumption : Doubling every 18 months.

*Gordon Moore

Apr 11, 2023 6

Transistor Scaling i4004

Apr 11, 2023 7

Financier Impact of Moore Law

*Price of Megabit in CMOS

Apr 11, 2023 8

Human Brain In 2010, the semiconductor industryManufactured roughly 1 billion transistors for every human on the planet;

Apr 11, 2023 9

CMOS technology

• Complementary Metal Oxide Semiconductor • Patented in 1967 by Frank Wanlass at Fairchild• Based on use of complementary and symmetrical

pairs of p-type and n-type MOSFETs transistor• + high noise immunity • + low static power consumption. • + high density

Apr 11, 2023 10

NMOS Transistor Basics

1. Cut-off Region: no channel exists (iD = 0) for all values of VD. (VGS < Vt) 2. Triode Region: The NMOS transistor is active and not “pinched off.” This means the value of VDS affects the value of iD (VGS > Vt and VDS ≤ VGS – Vt). 3. Saturation Region: The channel is “pinched off” because increases in VD have no affect on iD (VGS > Vt and VDS > VGS – Vt)

Apr 11, 2023 11

Saturation Region

Technology fixed parameters :μeff : is the charge-carrier effective mobility,Cox : is the gate oxide capacitance per unit aream : is the Body effectVt : is the threshold voltage

Fixed by designer : W : is the gate widthL : is the gate length (Lmin fixed by the Technology )Vgs ( = Vdd)

Apr 11, 2023 12

NMOS & PMOS Transistor

complementary and symmetrical pairs of p-type and n-type MOSFETs transistor

Apr 11, 2023 13

CMOS NAND Gate (back-end)

Transistor LevelSchematic Level Layout Level

=0

= 1 =

Apr 11, 2023 14

ASIC FLOW(front-end)

Schematic Block

VHDL files

Netlist

Design

Synthesis

Apr 11, 2023 15

Semiconductor Manufacturing

Sand Silicium

Wafer

Die

PackagingChip

Ingots

Apr 11, 2023 16

Manufacture/Making Ingots

Czochralski process

Apr 11, 2023 17

Wafer

• A wafer is a thin slice of semiconductor material

• High purity 99.999999 % crystalline silicon

• Wafer sizes is 100, 150, 200, 300mm diameter.

Apr 11, 2023 18

Lithography Process

Apr 11, 2023 19

StepperCosting several hundred to several thousand million yen ASML, Ultratech, Nikon, Canon

- Early days of lithography used 456 nm wavelength light. - Lithography today is using 193 nm wavelength light.

Apr 11, 2023 20

Interconnect Layer

Apr 11, 2023 21

Design Tor Test

Every chip are tested Teradyne tester

Design For Test (DFT)Test cost 50% of the chipScan-Chain - ATPGBIST : Built In Self Test

Apr 11, 2023 22

Defect on ASIC

Defect increase as cmos technology shrinks

Defect on metal 1 wire

malfunction of wirebonding machine

Num

ber of defect

Transistor shrink

Burnt part During test.

Apr 11, 2023 23

TEST Cost

Fabrication capital versus test capital.

Apr 11, 2023 24

Chip Failure

Bathtub curve.

Apr 11, 2023 25

Power Dissipation

Thermal dissipation

Traditional Power saving :-Lower the clock frequency (Fclk)-Lower the load capacity (Cl)-Lower the rail voltage (Vdd)

Dynamic Power : Cl Vdd2 Ptrans Fclk

Static Power : leakage gate thickness

New Power saving technique :-Power gating, Clock gating-Voltage & frequency scaling-Multi-voltage, Multi-threshold logic

Apr 11, 2023 26

TOP 10 from 1978 to 2008

Apr 11, 2023 27

Application Specific Integrated Circuit

ASIC

Semi-specific specific

Programmable FPGA Sea of gate Standard cell Full Custom SOC

Image sensor

MEMS

Apr 11, 2023 28

MEMS (MicroElectroMechanical Systems)

Main Application : - Accelerometers in consumer electronics devices : - Nintendo Wii, 3D (3-axis accelerometers ) - Cell phones (Apple IPhone ) - Number of Digital Cameras - Park the hard disk head when free-fall is detected.- Pressure, Temperature, Oxygen and speed sensors- Ink jet printerhead- Microphones for phones (70%, Reach one billion by 2011)

Apr 11, 2023 29

Apr 11, 2023 30

CMOS Image Sensors• Electrons produced is a function of the

wavelength and the intensity of light striking the semiconductor

• Transferred to a metering register (CCD sensors)

• Measure voltage or charge, through an analog-to-digital converter,

• Forms a digital electronic representation of the scene imaged

Apr 11, 2023 31

Image Sensors(example)

- 352 x 288 image array- 60 frames per secondimage capture

- Advanced algorithms to : cancel Fixed Pattern Noise (FPN), Eliminate smearing, reduce blooming.

- Programmable I2C : control, gamma, gain, white balance, color matrix, windowing, and image output in either 4-, 8- or 16 bit digital formats

Apr 11, 2023 32

Full Custom• no libraries available

+ highest performance and smallest die size

- disadvantages of increased design time, complexity, design expense, and highest risk.

• Application analog/digital/sensors

Apr 11, 2023 33

Sea ofgates array

• Only the interconnect is customized• Only some (the top few) mask layers are

customized the interconnect

• The interconnect uses predefined spaces between rows of base cells• Manufacturing lead time is between two days and two weeks.

Apr 11, 2023 34

Advantages :=> mixed system possible ( analog/digital)=> internal flexibility=> high density

Disadvantages :=> middle cost=> technology transistors / standard cell imposed and fixed => complex to master the technology

Sea of Gate or masked gate array (MGA)

Apr 11, 2023 35

Standard cell• All mask layers are customized transistors and interconnect• Custom blocks can be embedded• Manufacturing lead time is about eight weeks.• use a design kit (from the ASIC vendor)

• involves a complex library development process: cell layout • behavioral model • Verilog/VHDL model • timing model • test strategy • characterization • circuit extraction • process control monitors (PCMs) or drop-ins • cell schematic • cell icon • layout versus schematic (LVS) check • cell icon • logic synthesis • retargeting • wire-load model • routing model • phantom

Apr 11, 2023 36

Advantages :=> complete control of time parameters and electrical=> mixed system possible ( analog/digital/memes )=> flexibility=> very high density=> Low Power, high speed techniques

Disadvantages :=> High cost ($20M and up for chips designed at 90nm)

=> hard and complex to master the technology => few companies (low competition)=> High volume Product

ASIC Standard Cell

Apr 11, 2023 37

FPGA

Ken Chapman (Xilinx UK) 2003

.

Programmable Interconnect

• FPGA = Field Programmable Gate Array

• FPGAs contain the same basic resources– Slices (grouped into CLBs = Configurable Logic Blocs)

• Contain combinatorial logic and register resources

– IOBs (Input Output Blocs)• Interface between the FPGA and the outside world

– Programmable interconnect

– Other resources• Memory

• Multipliers

• Digital Clock Managers

• Global clock buffers

• Boundary scan logic

Apr 11, 2023 38

Advantages: => Technology easy to master => Reduced development time => Reprogrammable for some (ideal for prototyping) => Low cost

Disadvantages: => Non-optimized performance => Internal architecture completely frozen => Only digital (with some exceptions)

FPGAField Programmable Gate Array

Apr 11, 2023 39

1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000

FPGAs

ASICs

CPLDs

SPLDs

Microprocessors

SRAMs & DRAMs

ICs (General)

Transistors

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Technology Timeline

Apr 11, 2023 40

FPGA Vs ASIC

FPGASea of

gate

Standard

CellFull

Custom

Development time days/weeks Weeks /months Weeks /months months /years

Modification timeminutes/

hoursminutes/hours Weeks /months Weeks /months

Masks designs none interconnection interconnection All

Masks manufactories

none interconnection All All

Density Very low low moderate /high high

speed moderate moderate moderate/high high

cost low moderate high Very high

Apr 11, 2023 41

FPGA Vs ASIC• total product cost = fixed product cost + variable product cost *products sold

• The total production costs verify the relations:   FPGA = $ 21,800 + ($ 39. Volume produced)   Mga = $ 86,000 + ($ 10. Volume produced)   Standard Cell = $ 146,000 + ($ 8. Volume produced)

• Then we can calculate the following break-even volumes: FPGA/MGA ~ 2000 parts FPGA/CBIC ~ 4000 parts MGA/CBIC ~ 20,000 parts

Apr 11, 2023 42

Examples of fixed costs:

training cost for a new electronic design automation (EDA) system hardware and software cost • productivity • production test and design for test • programming costs for an FPGA • nonrecurring-engineering (NRE) • test vectors and test-program development cost • pass (turn or spin) • profit model represents the profit flow during the product lifetime • product velocity • second source

Apr 11, 2023 43

A break-even analysis for an FPGA, a masked gate

array (MGA) and a custom cell-based ASIC (CBIC).

Cost parts

Number of parts or volume

$1.000.000

$100.000

$10.00010 100 1000 10.000 100.000

break-evenFPGA / CBIC

break-evenFPGA / MGA

break-evenMGA / CBIC

CBIC

MGA

FPGA

FPGA Vs ASIC

Apr 11, 2023 44

ASICs comprise three separate regions, each with its own complexity, performance and

cost characteristics.

FPGA Vs ASIC

Apr 11, 2023 45

Staggering Chip Design Costs• $1000M designs

• Huge financial risk per design

•IC vendors becoming application solution providers

- Intel paid 1-2B to develop Atom,

- Microsoft spend 3-4B to develop Windows mobile.

Apr 11, 2023 46

Software-Differentiated Hardware

Apr 11, 2023 47

FPGA (review)

Ken Chapman (Xilinx UK) 2003

.

Programmable Interconnect

• FPGA = Field Programmable Gate Array

• FPGAs contain the same basic resources– Slices (grouped into CLBs = Configurable Logic Blocs)

• Contain combinatorial logic and register resources

– IOBs (Input Output Blocs)• Interface between the FPGA and the outside world

– Programmable interconnect

– Other resources• Memory

• Multipliers

• Digital Clock Managers

• Global clock buffers

• Boundary scan logic

Apr 11, 2023 48

Market Forecast

15%

FPGA provide the customizability of an ASIC without theneed to design and fab new devices for each platform.

Xilinx has more software engineers than hardware engineers; at Altera, the mix is roughly 50-50.

Apr 11, 2023 49

The Configurable Logic Blocks (CLBs)

-Constitute the main logic resource for implementing synchronous as well as combinatorial circuits.-Provide logic, arithmetic, and ROM functions- Programmable as either a D-type flip-flop

Apr 11, 2023 50

FPGA interconnect

Logic Block

Switch Block

Wire Segment Programmable Switch

a

cb

ed f

a=0 b=0 c=1 d=0 e=1 f=0

0 0 1 0 1 0

ce

Programmable FPGA Memory

RAM/ROM

Apr 11, 2023 51

FPGA interconnect

Apr 11, 2023

Spartan-3/3E Family

Smallest Device - XC3S50 - XC3S100E

192 CLB240 CLB 4 BRAM (18 KB each) 4 Multipliers

Largest device - XC3S5000 - XC3S1600E

8320 CLB3688 CLB

104 BRAM (18 KB each)36 BRAM

104 Multipliers36 Multipliers

Apr 11, 2023 53

Spartan-3 Product MatrixSystem Gates 50K 200K 400K 1000K 1500K 2000K 4000K 5000K

Logic Cells 1 728 4 320 8 064 17 280 29 952 46 080 62 208 74 880

Dedicated Multipliers 4 12 16 24 32 40 96 104

Block RAM Blocks 4 12 16 24 32 40 96 104

Block RAM Bits 72K 216K 288K 432K 576K 720K 1,728K 1,872K

Distributed RAM Bits 12K 30K 56K 120K 208K 320K 432K 520K

DCMs 2 4 4 4 4 4 4 4

I/O Standards 23 23 23 23 23 23 23 23

3V standard support yes yes yes yes yes yes yes yes

Max Single Ended I/O 124 173 264 391 487 565 712 784

VQ100 63 63

TQ144 97 97 97

PQ208 124 141 141

FT256 173 173 173

FG320 221 221 221

FG456 264 333 333 333

FG676 391 487 489

FG900 565 633 633

FG1156 712 784

Apr 11, 2023 54

Spartan-3 : Global Clock Network

- Clock generation and management

- Eight Global Clock inputs calledGCLK0 - GCLK7

- Eight Global Clock Multiplexers : BUFGMUX that accept signals from Global Clock inputs and route them to the internal clock network as well as DCMs.

Apr 11, 2023 55

Spartan-3 : Digital Clock Manager (DCM)

-Flexible, complete control overclock frequency, phase shift and skew

-DCM employs a Delay-Locked Loop (DLL)

- Feedback to maintain clock signal characteristics with ahigh degree of precision despite normal variations in operatingtemperature and voltage.

Apr 11, 2023 56

Spartan-3 : RAM BlockEmbedded RAM block

-Single port

-Ture dual port ( port A and B : Independent Access)

Write EnableClock Enable

Set/ResetClock

Data Output Bus

Parity Data Output

Address BusData Input Bus

Parity Data Input

Apr 11, 2023 57

Embedded RAM Operation

Apr 11, 2023 58

Spartan-3 : Dedicated Multipliers

-Embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product.

- The input buses to the multiplier accept data in two’s-complementform (either 18-bit signed or 17-bit unsigned).

Apr 11, 2023 59

uP

RAM

I/O

etc.

Main FPGA fabric

Microprocessorcore, special RAM,

peripherals andI/O, etc.

The “Stripe”

Additional cores in FPGA

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Apr 11, 2023 60

Additional cores in virtexFPGA

Virtex-5Q FPGA Family Members

Virtex-II

Apr 11, 2023 61

Mixed-signal FPGA – Actel

- Fusion Family -

Include analog blocks :

-Integrated A/D Converter (ADC), with 32 MUX inputs and Analog I/O PLL/OSC

-Analog Quad core (analog multiplexer, prescaler circuit, Current Monitor Block, Gate Driver, Temperature Monitor )

-Charge Pumps-Flash Memory block-Dual Port SRAM Block-Sleep/Standby Low-Power Modes

Apr 11, 2023 62

1) Functional Verification Duopoly - Synopsys Vera and Cadence SpecMan "e"

2) Formal Verification Alternatives - Jasper, Mentor 0-In, Synopsys Magellan, Cadence IFV, Real Intent

3) RTL Simulation Triopoloy - Mentor ModelSim, Cadence NC-Sim, Synopsys VCS

4) RTL Synthesis Monopoly - Synopsys Design Compiler Alternatives - Cadence RTL Compiler, Magma BlastRTL, OAsys

5) Equivalence Checking Duopoly - Cadence Verplex and Synopsys Formality

EDA Tools

Apr 11, 2023 63

EDA Tools

6) Test/ATPG/Scan/BIST Duopoly - Mentor FastScan/DFT Advisor and Synopsys TetraMax Alternatives: LogicVision

7) Floorplanning Semi-monopoly - Cadence First Encounter Alternatives: Magma Hydra, Synopsys Jupiter, Atoptech Apogee

8) Place and Route Triopoloy - Synopsys ICC, Magma Talus, Cadence Encounter Alternatives - Atoptech, Mentor Sierra

9) RC Extraction Duopoly - Synopsys Star-RCXT and Cadence Fire&Ice Alternatives - Mentor Calibre-xRC, Magma QuartzRC, Sequence Columbus

Apr 11, 2023 64

EDA Tools

10) IR Analysis Semi-monopoly - Apache Redhawk Alternatives - Cadence VoltageStorm

11) DRC/LVS Monopoly - Mentor Calibre Alternatives - Synopsys Hercules, Magma Quartz

12) Static Timing Monopoly - Synopsys PrimeTime Alternatives - Cadence ETS, Extreme GoldTime, Incentia TimeCraft, CLK-DA Amber, Magma QuartzTime

13) Signal Integrity Duopoly - Synopsys PT-SI and Cadence CeltIC Alternatives - Extreme GoldTime, Incentia TimeCraft, CLK-DA Amber

Apr 11, 2023 65

16) FPGA Duopoly - Mentor Exemplar and Synopsys Synplicity Alternatives - tools from Xilinx and Altera

14) SPICE Alternatives - Synopsys HSIM/HSPICE, Cadence Spectre, Magma FineSim, Mentor, Nascentric, Berkeley

15) Full Custom Monopoly - Cadence Virtuoso Alternatives - SpringSoft Laker, Magma Titan, Synopsys Orion

17) Emulators/Acceletors Monopoly - Cadence Palladium Alternatives - Mentor Veloce, EVE, Dini, Synopsys HAPS

EDA Tools