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Appendix F

Selected Solutions

F.3 Chapter 3 Solutions 

3.1

N-Type P-Type

Gate=1 closed open

Gate=0 open closed

3.3 There can be 16 different two input logic functions.

3.5

A B C OUT

0 0 0 10 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

3.7 There is short circuit (path from Power to Ground) when either A = 1 and B = 0

or A = 0 and B = 1.

3.9

A B NOT(NOT(A) OR NOT(B))

0 0 0

0 1 0

1 0 0

1 1 1

AND gate has the same truth table.

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F.3. CHAPTER 3 SOLUTIONS   2

3.11 a. Three input And-Gate

Three input OR-Gate

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F.3. CHAPTER 3 SOLUTIONS   3

b. (1) A = 1, B = 0, C = 0.

AND Gate

OR Gate

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F.3. CHAPTER 3 SOLUTIONS   4

b. (2) A = 0, B = 0, C = 0

AND Gate

OR Gate

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F.3. CHAPTER 3 SOLUTIONS   5

b. (3) A = 1, B = 1, C = 1

AND Gate

OR Gate

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F.3. CHAPTER 3 SOLUTIONS   6

3.13 A five input decoder will have 32 output lines.

3.15

Cin  1 1 1 0A 0 1 1 1

B 1 0 1 1

S 0 0 1 0

Cout  1 1 1 1

A = 7, B = 11, A + B = 18.

In the above calculation, the result (S) is 2 !! This is because 18 is too large a number to berepresented in 4 bits. Hence there is an overflow - Cout[3] = 1.

3.17 (a) The truth table will have 16 rows. Here is the truth table for Z = XOR (A, B, C, D). Any

circuit with at least seven input combinations generating 1s at the output will work.

A B C D Z

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 11 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Z = XOR (A,B,C,D)

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F.3. CHAPTER 3 SOLUTIONS   7

(b)

3.19 Figure 3.36 is a simple combinational circuit. The output value depends ONLY on the inputvalues as they currently exist. Figure 3.37 is an R-S Latch. This is an example of a logic circuit

that can store information. That is, if A, B are both 1, the value of D depends on which of the

two (A or B) was 0 most recently.

3.21 2 * 214 = 215 = 32768 nibbles

ABC

D

Z

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F.3. CHAPTER 3 SOLUTIONS   8

3.23

A B C Z

0 0 0 0

0 0 1 0

0 1 0 00 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

3.25 (a) 3 gate delays

3.25 (b) 3 gate delays

3.25 (c) 3*4 = 12 gate delays

3.25 (d) 3*32 = 96 gate delays

3.27(a) When S=0, Z = A

3.27(b) When S=1, Z retains its previous value.

3.27(c) Yes; the circuit is a storage element.

3.29 No. The original value cannot be recovered once a new value is written into a register.

3.31. 8 * (2^3) = 64 bytes

3.33.(a) To read the 4th memory location, A[1,0] = 11, WE = 0

3.33.(b) A total of 6 address lines are required for a memory with 60 locations. Theaddressability of the memory will remain unchanged.

3.33.(c) A program counter of width 6 can address 2^6 = 64 locations. So without changing thewidth of the program counter, 64-60 = 4 more locations can be added to the memory.

3.35 Total bits of storage = 2^22 * 3 = 12582912

3.37 There are a total of four possible states in this lock. Any other state can be expressed as one

of states A, B, C or D. For example, the state performed one correct followed by one incorrectoperation is nothing but state A as the incorrect operation reset the lock.

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F.3. CHAPTER 3 SOLUTIONS   9

3.39 No. An arc is needed between the two states.(a) Game in Progress:

Texas * Oklahoma

Fouls:4 Fouls: 4

73 68First Half

7:38Shot Clock : 14

(b) Texas Win:Texas * Oklahoma

Fouls:10 Fouls: 10

85 70

Second Half0:00

Shot Clock : 0

(c) Oklahoma Win:

Texas * Oklahoma

Fouls:10 Fouls: 1081 90

First Half

7:38

Shot Clock : 0

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F.3. CHAPTER 3 SOLUTIONS   10

3.41

No

coins

5

10 

15 

30 

20 

25 

35+

ch

35+

ch

35+

ch 35+

ch

35

N

N

N

N

N

N

Q

D

D

D

D

N

D/Q

Q

QQ

D

D

Q

Q

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F.3. CHAPTER 3 SOLUTIONS   11

3.43a)

S1 S0 X D1 D0 Z

0 0 0 0 0 0

0 0 1 0 0 00 1 0 0 0 1

0 1 1 1 0 1

1 0 0 1 1 1

1 0 1 1 1 1

1 1 0 1 0 1

1 1 1 1 0 1

b)

0/1

0/1

0

1

00 01

11 10

0/1