security sphere: radio frequency subsampling receiver
TRANSCRIPT
Security Sphere: Radio Frequency Subsampling
Receiver
by
Jelena Madic
MASSACHUSETTS INSTITUTEOF TECHNOLOGY
JUL 3 12002
LIBRARIES
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degrees of
Bachelor of Science in Electrical Science and Engineering
and Master of Engineering in Electrical Engineering and Computer Science
at the Massachusetts Institute of Technology
June, 2002
Copyright 2001 Massachusetts Institute of Technology. All rights reserved.
AuthorDepartment of Electrical Engineering and Computer Science
May 10, 2002
Certified byProfessor Charles G. Sodini
Professor of Electrical Engineering and Computer ScienceThesis Supervisor
Accepted byArthur C. Smith
Chairman, Department Committee on Graduate Theses
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Security Sphere: Radio Frequency Subsampling Receiverby
Jelena Madic
Submitted to theDepartment of Electrical Engineering and Computer Science
June 2001
In Partial Fulfillment of the Requirements for the Degree ofBachelor of Science in Electrical Science and Engineering
and Master of Engineering in Electrical Engineering and Computer Science
Abstract
The main goal of this thesis project was the design and implementation of a RadioFrequency Subsampling Receiver that can demodulate the 2.5Mb/s GFSK/GMSKmodulated signal at 1.89GHz carrier frequency using commercially availablecomponents. This receiver has a single analog IF stage that downconverts the carrierfrequency to 140MHz. The wideband signal is further subsampled and transferred intothe digital domain using high speed, high performance, wide dynamic range analog-to-digital converter AD6644. The digitized signal is then separated into in-phase (I) andquadrature (Q) components with a frequency translator using a numerically controlledoscillator. Digital samples of I and Q run at the frequency equal to the sampling clockfrequency of 60MHz. Currently available DSPs are not fast enough to perform all theother subsequent functions on data running at sample rates this high. Thus, following thefrequency translator are high-speed decimating filters that reduce the sample rate to allowfor proper data processing, and FIR low-pass filter. The low-pass FIR filter rejectsunwanted signals and their images. Demodulation is performed in software. As a resultthis receiver is very flexible since software allows for easy changes without a need toreplace hardware. In addition some problems like DC offsets, mismatch and noiseproblems are eliminated.
Thesis Supervisor: Professor Charles G. SodiniTitle: Professor of Electrical Engineering and Computer Science
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Acknowledgements
I wish to thank all people who helped me to bring this thesis project to successful
completion.
Specifically, I would like to express my gratitude to Professor Dr. Charles Sodini
for his guidance and support not only while I was doing my M.Eng. project but also while
he was my undergraduate advisor at MIT. His invaluable suggestions and his visionary
mind where a crucial factor in the successful completion of my thesis project. I am also
grateful for all the career advices I received from Dr. Sodini throughout my stay at MIT.
Sam Lefian is a person with a wealth of practical knowledge that he was always
willing to share with me. He is also a very warm and friendly person that was there to
offer an advice when I most needed it. Often his encouragement and advice were the
source of hope after long nights I spent trying to make things work. The numerous useful
discussions I had with him influenced decisions related to my career in general.
My thesis partners Oluwamuyiwa Olubuyide and Matthew Yarosz provided me
with technical advice throughout the project. They were always ready to listen to
complaints or excitements related to my work. I learned from them in many ways.
Ketan Patel's thesis provided me with a very useful base on practical radio
frequency receiver design.
I thank to Manish Bhardwaj for many brainstorming sessions, technical assistance
and friendship.
I also thank to Dan McMahill for finding time to discuss his project with me
during his last and busiest year at MIT.
Analog Device's University Program made valuable contribution to this project
by donating several evaluation boards and components. National Semiconductor
Corporation, SAWTEK and Connor-Winfield also contributed to this project with their
valuable component donations.
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Table of Contents
Introduction ....................................................................................................................... 15
1.1 Receiver Specifications ......................................................................................... 16
1.2 Thesis Overview .................................................................................................... 18
Radio Frequency Receiver Architectures ....................................................................... 19
2.1 Perform ance V ariables ......................................................................................... 21
2.1.1 Bit Error Rate................................................................................................... 21
2.1.2 Signal-To-N oise Ratio..................................................................................... 22
2.1.3 N oise Figure and N oise Factor ....................................................................... 22
2.1.4 Cascaded N oise Figure .................................................................................... 23
2.1.5 Sensitivity ......................................................................................................... 23
2.1.6 Linearity...............................................................................................................25
2.1.7 Effects of N onlinearity .................................................................................... 26
2.1.8 Interm odulation ............................................................................................... 27
2.1.9 Cascaded N onlinear Stages ............................................................................. 30
2.1.10 D ynam ic Range ............................................................................................. 30
2.1.11 Selectivity...................................................................................................... 31
2.2 Receiver A rchitectures ......................................................................................... 31
2.2.1 Superheterodyne Receivers ................................................................................. 32
2.2.2 H om odyne Receivers....................................................................................... 33
2.2.3 D igital Receivers ............................................................................................. 34
Subsam pling Radio Frequency D esign ......................................................................... 37
3.1 Subsam pling ........................................................................................................ 37
3.1.1 Sensitivity to Sam pling Clock Jitter ................................................................ 42
3.2 Subsam pling Receiver Architecture .................................................................... 46
3.2.1 N um m erically Controlled Oscillator ................................................................ 47
3.2.2 D ecim ating Low -pass Filters........................................................................... 47
3.2.3 D em odulator.................................................................................................... 50
3.2.3.1 A nalog M odulation.................................................................................... 50
3.2.3.2 D igital M odulation .................................................................................... 51
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Im plem entation of the Subsam pling Receiver................................................................ 61
4.1 Frequency Planning and Com ponent Selection.................................................... 62
4.2 Printed Circuit Board Layout D esign .................................................................... 70
Testing and Results............................................................................................................73
5.1 A nalog RF Board Testing .................................................................................... 73
5.2 Testing of the A D C................................................................................................ 75
5.3 Testing of the Functions Implemented in Digital Domain ................................... 76
Conclusion ......................................................................................................................... 83
6.1. Sum m ary..................................................................................................................83
6.2. Future W ork.............................................................................................................84
References ......................................................................................................................... 85
A ppendix A : Schem atics and Board Layout ................................................................. 87
A ppendix B : LM X 2330L D ual Frequency Synthesizer .................................................. 101
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List of Figures
1.1: T he Security Sphere ............................................................................................... 16
1.2: Subsampling receiver block diagram .................................................................... 17
2.1: Fundamental single IF receiver functions. ............................................................ 20
2.2: D ual-IF receiver block diagram .............................................................................. 20
2.3: Graphical representation of the 1-dB compression point ...................................... 27
2.4: Degradation of the input signal due to intermodulation between two interferers ...... 28
2.5: G raphical interpretation of the IIP3...................................................................... 28
2.6: Problem of im age in receivers................................................................................ 32
3.1: The effect of Nyquist sampling, f., = 4f ............................................................. 38
3.2: The effect of destructive aliasing, f, < 2fa ........................................................... 39
3.3: Frequency domain effects of sampling..................................................................40
3.4: Successful example of subsampling ...................................................................... 42
3.5: Error caused by clock jitter when subsampling.................................................... 46
3.6: An example frequency response for N=4, M=1, R=7, and f, = 1/8 ..................... 49
3.7: GMSK time domain waveforms........................................................................... 57
3.8: Q uadrature m odulation......................................................................................... 58
4.1: Subsampling receiver block diagram used in this thesis project...........................61
4.2: Transfer characteristics of the band select filter DFC21R89PO20 HHE .............. 63
4.3: Functional block diagram for AM50-0004 LNA ................................................. 64
4.4: Schematic of the application circuit for IAM-91563 mixer ................................. 65
4.5: Transfer characteristics for SAWTEK-854909 bandpass filter.............................66
4.6: SNR as a function of rms jitter for different analog input frequencies ................. 67
4.7: Functional block diagram for AD6620..................................................................68
4.8: Basic AD6620 Evaluation Board block diagram ................................................. 69
5.1: GMSK modulated signal at the input of the SAW filter ................... 74
5.2: GMSK modulated signal at the output of the SAW filter .................. 74
5.3: L O output of the SA W filter......................................................................................75
5.4: AD6620 composite filter specifications ............................................................... 76
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5.5: Composite frequency response of the AD6620 CIC2 , CIC5 and RCF filter stages
u sed in th is project.............................................................................................................77
5.6: For 00 data pattern the phase of the GMSK modulated signal has a constant negative
slope as it constantly decreases ...................................................................................... 78
5.7: For 11 data pattern the phase of the GMSK modulated signal has a constant positive
slope as it constantly increases ...................................................................................... 79
5.8: Demodulated phase for 01 data pattern ................................................................. 80
5.9: Demodulated phase for 0011 data pattern ............................................................. 80
5.10: Demodulated phase for 1111 1011 0010 0000 data pattern ................................. 81
5.11: Demodulated phase for 0011 00110000 1111 0000 1111 0101 0101 data pattern 81
A -1: R eceiver front end ............................................................................................... 88
A-2: Receiver front end (continued).............................................................................89
A-3: AD6644 circuit schematics ................................................................................. 90
A-4: Dual frequency synthesizer circuit (part I)...........................................................91
A-5: Dual frequency synthesizer circuit (part II) ........................................................ 92
A-6: Dual frequency synthesizer circuit (part III)........................................................93
A-7: Programmer for the LO Synthesizer LMX 2330L ............................................... 94
A-8: Top copper, top silk, board.................................................................................. 95
A-9: Top silk, top paste, power2-3.3V and 5VA, board ............................................... 96
A-10: Bottom copper, bottom silk, board.........................................................................97
A-11: Top silk, top paste, 5V, board ............................................................................. 98
B-1: Symplified block diagram of LMX2330L..............................................................100
B-2: The timing diagram for Data, Clock and Enable input signals .............. 104
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List of Tables
3.1: The occupied RF bandwidth for GMSK as a fraction of the data rate containing a
given percentage of power............................................................................................ 56
T.1: Counter selection via control bits.............................................................................102
T.2: Reference divider (R) serial format ......................................................................... 102
T.3: 15-Bit Programmable Reference Divider Ratio (R counter) ................................... 102
T .4 : D ivider (N ) serial form at.........................................................................................103
T.5: 7-Bit Swallow Counter Divide Ratio (A counter) ................................................... 103
T.6: 1 1-Bit Programmable Counter Divide Ratio (B counter)........................................103
T.7: Synthesizer Programmable Modes ......................................................................... 104
T.8: Mode Select Truth Table ........................................................................................ 104
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I dedicate this thesis to my parents, my brother, and Sasa
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Chapter 1
Introduction
The demand for wireless and low power video surveillance devices is constantly
increasing in recent years as the cost, performance, size and power dissipation of their
integral components improves. The main advantages of these devices are their portability
and versatility. For example, they can be used in security systems installed in banks,
grocery stores, prisons, and homes or for traffic surveillance.
The motivation behind the Security Sphere project was to develop such a video
surveillance device that meets today's market standards using advanced technology
developed at MIT. This includes CMOS Differential Passive Pixel Image (DPPI) sensor
chip used to replace standard digital camera and the phase locked loop (PLL) frequency
synthesizer chip. Since the DPPI sensor chip is implemented in a standard CMOS
process, its important advantages are lower power dissipation, smaller area and cost. The
phase locked loop (PLL) frequency synthesizer chip is used in the radio frequency
transmitter architecture. It employs a technique for in service automatic calibration whose
purpose is to achieve high data rates [1]. This technique is used to maintain accurate
matching between the digital precompensation filter and the analog PLL transfer function
across process and temperature variations.
The Security Sphere, shown in Figure 1.1, contains four imager cameras mounted
on the bottom half of a 16-cm radius sphere. This set up allows 180-degree panoramic
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view of the camera surroundings. Images collected by the cameras are first processed
through an intelligent motion detection algorithm. The algorithm is designed to
distinguish between human and non-human motion. The data are next compressed in real
time and sent through the wireless channel at 2.5Mbps data rate on a 1.89GHz carrier to a
display unit. The wireless channel consists of an ultra low power transmitter and a
subsampling receiver.
Important advantages this receiver has over its analog counterparts are a single
downconversion stage and thus reduced number of analog components and an algorithm
to demodulate a high data rate GMSK modulated signal in a digital domain. The aim of
this thesis project was to design and implement such a subsampling receiver.
mera
2.5Mb/s, 1.89GHz
MIT Transmitter] RFSubsampling
Vid-O ReceiverCompression
PE Motn 30 ps DecompressionDe ection
Camera cm
Figure 1.1: The Security Sphere.
1.1 Receiver Specifications
A block diagram of the subsampling receiver is shown in Figure 1.2. It is designed to
receive and demodulate data sent by the MIT radio frequency (RF) transmitter. The key
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features of this transmitter relevant for the receiver design are Gaussian Frequency Shift
Keying (GFSK) or Gaussian Minimum Shift Keying (GMSK) modulation at data rate of
2.5Mbps, and RF output carrier center frequency in the 1.89GHz range. In addition the
receiver is designed to meet DECT standard which requires at least -82dBm of receiver
sensitivity. To improve the performance of this receiver compared to fully analog
receivers and to minimize the number of analog components, demodulation is
implemented in digital domain. Frequency downconversion from 1.89GHz to 140MHz is
performed in one IF stage. After the first frequency downconversion and bandselect
filtering, wideband carrier signal is transferred into the digital domain using the
subsampling technique. The subsampling technique allows sampling of very high
frequency signals at a rate lower than the Nyqust rate.
ANALOG IF STAGE DIGITAL UNIT
DIGITAL
RF LOWPASS& DSPAMP ~TRANS- OV xDCMTN (EO)AMP LATOR FILTERS DMD
CLOCK OSCILLATOR
RF BOARD DIGITAL BOARDS
Figure 1.2: Subsampling receiver block diagram
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1.2 Thesis Overview
This thesis consists of six chapters and two appendices. Chapter 2 presents a brief
discussion of basic concepts in RF design and a review of conventional receiver
architectures and topologies that are the subject of the mainstream research today.
Chapter 3 describes proposed subsampling receiver architecture in more detail and
reviews some basic communications topics useful for this thesis work. Implementation of
the proposed system and printed circuit board design are discussed in Chapter 4. Chapter
5 presents experimental results from the prototype. Chapter 6 summarizes the project and
suggests areas for future work.
Appendix A provides schematics, board layout details, and a bill of materials. Appendix
B explains the LMX2330L dual frequency synthesizer chip used in this project.
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Chapter 2
Radio Frequency Receiver Architectures
The purpose of a radio frequency (RF) receiver is to gather relevant information from the
energy of the electromagnetic waves present in the surrounding medium. To accomplish
this goal, the receiver must do several fundamental functions. It needs to transform the
energy in the medium to an electrical form and select and amplify a desired weak signal
from much stronger interfering signals and noise. It also needs to reject undesired signals
and extract modulated information with minimum probability of error [2]. Because most
of the analog and digital components cannot operate at high RF frequencies, it is
necessary to downconvert the carrier frequency of the received signal. Illustration of
performance of these receiver functions in the case of amplitude-modulated signals is
presented in Figure 2.1.
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(a) Time domain representation.
(b) Frequency domain representation.
A A A A A
f f f f f
Input Amplification Frequency Channel DemodulationDownconversion Select
Filtering
Figure 2.1: Fundamental single IF receiver functions. (a) Time domain. (b) Frequency
domain.
An example of a typical analog dual IF receiver is shown in block diagram of
Figure 2.2 [3].
Tael c Reject Fiter Soe Flft er _ Select FilterD m du a r
Figure 2.2: Dual-IF receiver block diagram.
Its basic parts are band select filter, low noise amplifier (LNA), image reject filter, two
mixers used for downconverting the carrier frequency, second channel select filter,
amplifier, and a demodulator. Mixers reduce carrier frequency to a value called
intermediate frequency (IF). They operate on a pair of signals in a way that produces two
signals with frequencies equal to the sum and the difference of the input signals'
frequencies. Their function can be represented with the following expression:
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(A cOs ORF) A2 COsLOtO) A 2 [cos(WRF - WLO )t + COS(WRF + COLO )t [2]. (2.1)
For this reason, mixers are sometimes called multipliers. The lower frequency component
of the output is of interest to us, whereas the higher frequency component is useless and
is filtered out with the channel select filter.
2.1 Performance Variables
Receiver performance quality is determined from the quality of the output signal usually
defined in terms of signal-to-noise ratio (SNR) or bit error rate (BER). In general, we
want to maximize SNR and minimize BER. Other important parameters that characterize
receiver performance are noise figure, sensitivity, linearity, dynamic range, and
selectivity. They all have to be studied carefully for a designer to be able to understand
major receiver design tradeoffs and to be able make a proper selection of receiver
configuration.
2.1.1 Bit Error Rate
Communication accuracy of a digital wireless system is analyzed by monitoring a bit
error rate (BER), which is defined as the rate at which errors are expected to occur as a
fraction of the total number of bits of information. Mathematically, bit error rate is
defined as number of errors divided by number of bits sent. If the quality of the signal is
maximized, then signal range and transmitter power are optimized as well. Detectors
ability to "make" a decision in the presence of the noise in a receiver is relayed by its bit
error rate.
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2.1.2 Signal-To-Noise Ratio
Signal-to-noise ratio (SNR) is a measure of signal strength relative to noise. The ratio is
usually measured in decibels (dB). If the incoming signal strength in microvolts is Vs, and
the rms noise level, also in microvolts, is Vn, then the signal-to-noise ratio, SNR, in
decibels is given by the formula
SNR = 20 log o(Vs/Vn) (2.2)
2.1.3 Noise Figure and Noise Factor
Noise factor (F) is the amount of noise that receiver contributes within a given noise
bandwidth [3]. It is commonly given as
Total available output noise power
Portion of output noise caused by the source
Noise factor can also be expressed in terms of signal-to-noise ratios at the input (SNRin)
and at the output (SNRU,)
SNRinF = [3]. (2.4)
SNROUt
Thus, noise factor can also be defined as a measure of how much SNR degrades due to
noise added by the receiver.
Noise Figure (NF) is defined as noise factor expressed in decibels:
NF = 10logF. (2.5)
Note that in literature NF is sometimes used to denote noise factor and F noise figure. For
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/2.3 )
all practical purposes, there is no need to distinguish these two terms and they can be
used interchangeably. The lower the noise figure, the better the receiver performance.
2.1.4 Cascaded Noise Figure
In an n-stage system, like a receiver built using commercial components, to qualify
receiver sensitivity, it is important to calculate the noise figure for a cascade of stages.
This noise figure can be expressed in terms of the noise factor and gain of each stage.
Cascaded noise factor is given by the Friis equation
F2-1 Ffl-1Fo = I+ (F, - 1) + +.2 - + , (2.6)
Api Ap1... Ap~m - >
where Fi) is the noise factor and AP(i) is unloaded voltage gain of the i-th stage [3].
Noise figure can then be found using equation (2.3). Friis equation tells us that the higher
the gain of the stage is, the lower the noise of the following stage is. Thus, the first stages
are the major contributors of noise and it is desirable to minimize the noise factor and
maximize the gain of those stages. This is the reason why the low noise amplifiers are
located at the first stage to amplify the signals with minimum increase of noise. It is also
useful to mention that Friis equation assumes that input and output impedances of each of
the n stages are perfectly matched, which is usually not true in reality. Therefore, noise
figure of a real system is higher than its calculated value using Friis expression.
2.1.5 Sensitivity
Sensitivity is the minimum strength of input RF signal that a receiver can detect with
acceptable value for the output SNR ratio [3]. When received carrier is modulated by a
digital baseband signal, the output SNR directly affects detected BER. Therefore,
sensitivity can also be defined as the minimum signal level a receiver can detect that
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results in a given BER. The expression for sensitivity can be derived from equation (2.2)
for noise figure [3].
NF =SNRinSNRout
Psig/PRS
SNROUt(2.7)
where, Psig is the input signal power and PRS the source resistance noise power, per unit
bandwidth. Thus, the total input signal power is expressed as
Psig tot = PRS -NF -SNRor -B , (2.8)
where B is the channel bandwidth. Minimum input signal power is found by replacing
SNRout with minimum acceptable value for the output SNR. Converting quantities in
equation (2.6) in decibels, we get
Pin, min dBm = PRS I dBmIHz + NF | dB +1 logB.
Assuming conjugate matching at the input
PRS = kT = -174dBm/Hz
at room temperature. It follows that
Pin min = (-l74dBm / Hz + NF + 10log B) + SNR min
(2.9)
(2.8)
(2.9)
The three terms inside the brackets represent the total integrated noise of the system that
is also called the noise floor.
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2.1.6 Linearity
Linearity is an important concept as it helps us understand how nonlinear effects limit the
upper end of a receiver dynamic range. For a device to remain linear, the output signal
must be equal to the input signal times the gain of the device. In addition, the principle of
superposition must hold. In other words, if the output of a system can be expressed as a
linear combination of individual input responses, the system is said to be linear.
Mathematically this looks as follows. If the two inputs x, (t) and x2 (t) are applied to a
system with a system functionf, then
x, (t) -f > y (t), and x 2 y2 (t) . (2.10)
For superposition to hold
ax1 (t) +bx 2 (t) -f->ay, (t) +by 2(). (2.11)
In real devices, for large enough input signals, the linearity condition is not satisfied. The
output starts to level off and gain starts to decrease. To explain these effects further, we
will simplify our analysis by looking at memoryless, time-variant systems whose
response in the nonlinear range can be approximated with a polynomial [3]:
x(t) f y(t)~ax(t)+a2x2 (t) + a 3x3 (t) . (2.12)
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2.1.7 Effects of Nonlinearity
Gain compression
If the input to a nonlinear system is of the form x(t)= A cos a, (2.12) becomes
2 2 3 CO3
y(t) = a, A cos ax + a 2A cos2 ax +aA cos t (2.13)
a9 A2 a3 A3=aAcosax+ 2 (1+cos2ax)+ 3 (3cosal+cos3ax) (2.14)
2 4
_a 2A2 K 3a3A3 5 a2A2 a3A3
= + ajA+ cosax+ cos2ax+ cos3ox. (2.15)2 y1 4), 2 4
The term in (2.15) with the same frequency as the input signal is called fundamental and
the ones with frequencies equal to the multiple of the input frequency are called
harmonics. The amplitude of n, harmonic is proportional to A". For small input levels,
the small-signal gain of the system from the system represented by (2.15) is oc. Thus, if
the input signal has high amplitude, harmonics will become more dominant in the
response. As a consequence, the system gain begins to vary. With the emergence of
harmonics the gain becomes approximately a, + 3a 3A2 /4. Because active devices can
provide only a limited amount of power that will be distributed among both the
fundamental and the harmonics, the system gain will decrease consequently. Ideally we
would like all the power to be delivered to the fundamental. The input signal power at
which the small-signal gain of a device has decreased by ] dB is called 1-dB compression
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point (Figure 2.3) [3]. This point can be used to determine the upper limit of the dynamic
range if intermodulation effects are not that severe.
P .(dB)
1 dB
10pin
P1d (B
GAIN(dB) I .. .......
jPinP 1.dS 08)
Figure 2.3: Graphical representation of the 1-dB compression point.
Another effect of nonlinearity is the addition of a DC term to the output of a device,
which affects biasing of the next stage.
2.1.8 Intermodulation
If a two-tone interfering signal with frequencies w0 and W2 is applied to a nonlinear
system, it will produce frequency components that are not harmonics of the input signals.
This effect is called intermodulation (IM). The frequency of the intermodulation products
can be expressed in terms of input frequencies as
w= a, + ba 2, (2.16)
where a and b are integers. Thus, IM products can fall in the band of interest and corrupt
it. To understand this effect better, we will further explain it mathematically. Assume the
input signal is of the form x(t) = A, cos C91t + A2 cos a)2t . If we substitute x(t) into equation
(2.12) and perform a few algebraic manipulations, we get
y(t) = a ](A, cos, t + A2 cos 0 2t)+ a 2 (A, cosco t + A2 cos C0t 2
+a(A Cosco t + A2 cos 2t)3 (2.17)
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= a 2 AA 2 cos(C 1 + w 2 )t+a 2AA 2 cos(W1 - 2 )t
3aA 2 A2+ 3 2cos(24
2
+ C2)t + 3aA1 A 2 cos(2wo, - o2 )t4
(2.19)
(2.20)3a 3A A+ 3a 3A2 A-+ 2cos(2w 2 +wc1)t + 'cos(2w 2 -w1))t4 4
+ DC terms and harmonics that are excluded for simplicity.
Equation (2.18) shows second-order and equations (2.19) and (2.20) third-order IM
terms that come from the second and third-order terms in equation (2.12), respectively. It
turns out that third-order terms with frequencies 2a), - 0 2 and 2o) - C0, can be the most
destructive when C0, , w2 and the band of interest are near each other. This is illustrated
in Figure 2.4 [3.]
INTERFERERS
t DESIREDSIGNAL
NONLINEARAMPLIFIER
vWut
2 0)12)2 I )m
Figure 2.4: Degradation of the input signal due to intermodulation between two
interferers.
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(2.18)
An important characteristic of intermodulation distortion is that for nh-order IM product
its output power changes by n decibels for each decibel change in the output power of its
two-tone fundamental. This is under assumption that A, = A2 . For example, we can see
from (2.17) and (2.18) that third order IM (IM3) product increases proportionally to A3
and fundamental to A. The point at which the power levels of IM3 product and
fundamental are the same at the input and at the output is called third intercept point
(IP3). This is illustrated in Figure 2.5 [5].
OUTPUTPOWER(dBm)
Intertept
FundamentalComponent
Intermodulalloo
iIP INPUT POWER(dBm)
Figure 2.5: Graphical interpretation of the 11P3.
under the assumption that a higher-order nonlinear IM terms are negligible and the gain
of the system is relatively constant and equal to ol. The input power level at which the
two lines in the graph cross is called the input IP3 (11P3) and the output power level
(01P3). Either 11P3 (usually mixers) or 0IP3 (other components of the receiver) are used
to measure IM. The higher IIP3 and 01P3 are, the wider the linear range of a device is.
IP3 is an important measure of linearity especially in devices like active filters where
other tests often fail to reveal nonlinearity.
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2.1.9 Cascaded Nonlinear Stages
In a cascade of nonlinear devices, such as a receiver, it is important to know the
equivalent cascaded value of IIP3 in terms of the IP3 and gain of individual stages. One
can expect IIP3 to be lower if the gain in the first stages of the chain is higher. This is
because higher gain results in higher signal levels and lower useful linear range for the
following stages. Mathematically this can be seen from the expression [3]
1 1 G12 G1
2G22 2+ G 2 + 22 .+ (2.21)
AIP3.total A P3 1 2 AII 3,2 AIP 3.3 2y
where A js,, is the IIP3 in volts and G, is the small-signal gain of the nth stage. Although
lower gain in early stages improves IIP3, it also decreases the overall noise figure of the
system, as concluded earlier. Proper design decisions have to be done to come to the most
optimal solution.
2.1.10 Dynamic Range
Dynamic range is defined in general as the ratio of the maximum tolerable to the
minimum acceptable input levels. In RF systems the upper limit is determined by
intermodulation and gain compression phenomena and lower limit by sensitivity.
Dynamic range defined this way is called spurious-free dynamic range (SFDR) [3]. If
SFDR is expressed in decibels it becomes equal to the difference between the input
power level in a two-tone test that produces third-order intermodulation product equal to
the noise floor and minimum acceptable power of the input signal. Minimum acceptable
input power for a system Pin,,n was already found in (2.9). The power level Pi,,,nax for
which intermodulation levels equal the noise floor are given by
n m 2 PP +noise -floor
nmx =3"- (2.22)
30
Thus, mathematically SFDR can be expressed as
SFDR =IP -P (2.23)
2P 3 F + SNR(2.24)3
=2(P -) SNR, , (2.25)3
where PjI3 is the input power level corresponding to the input-third order intercept point.
2.1.11 Selectivity
Selectivity is a measure of how well a receiver can reject unwanted signals and image
frequency. This is usually determined by appropriate use of channel select and image
reject filters. Detailed description of these and other measures of performance can be
found in the literature [2], [3], [4].
2.2 Receiver Architectures
Many receiver architectures have been developed in the past: superheterodyne,
homodyne, tuned radio frequency (TRF) receivers, regenerative and superregenerative,
compressive (microscan), instantaneous frequency measurement (IFM), and many other
[2]. However, the most popular among these are superheterodyne and homodyne
receivers. Selecting the most appropriate configuration is not a simple task and depends
on many factors, some of which are the previously discussed performance measures, but
also complexity, cost, power dissipation, and in IC design the number of external
components.
31
2.2.1 Superheterodyne Receivers
The superheterodyne receiver architecture is the most popular architecture. The basic
block diagram of a dual-IF (two downconversion stages) superheterodyne structure has
been shown in Figure 2.2. These types of receivers typically consist of two or three
downconversion stages to provide the necessary sensitivity and selectivity. They are
different from homodyne receivers because their final IF frequency is non-zero. The
advantage of this architecture is that the DC-offset problems are avoided. Selecting the
value of the final IF frequency is a hard step as it carries a lot of tradeoffs of which the
most important one is between image rejection and channel selectivity.
The problem of the image frequency arises because mixers or analog multipliers do not
distinguish polarity of the difference between two frequencies. In other words, the
product of mixing cos(ORF -COLO )t will have the same value as cos(OLO - WRF )t
Therefore, two input frequencies, desired and interfering signal, equally distant from CLO
will be translated to the same frequency by a mixer. The interferer translated into the
band of interest is called the image. For example, if the received signal of interest is
centered around ORF = (WLO - CIF), then what we call "image" is located around
COW = (2c0L0 - WRF (CLO + (oF). Figure 2.6 illustrates the problem of image [3].
Desired ImageBand
AAae(RF im
(t)IF () IF
0LO 0
COSWLOt
Figure 2.6: Problem of image in receivers.
32
The image power can be so much higher than the power of the desired signal, that it is
necessary to utilize proper image rejection techniques. The most common way to reject
unwanted interferers is to place an image-reject filter before the mixer. For better
rejection IF frequency must be selected to be high. However, high IF requires high Q of
the channel select filter following the mixer. This is why traditionally in receivers there
are two or even three downconversion stages. The first IF frequencies are selected to be
high for good image rejection, while the final IF frequency is low to enable better channel
selectivity.
2.2.2 Homodyne Receivers
Homodyne receivers are also popularly called direct-conversion or zero-IF receivers.
Their major difference from heterodyne receivers is that their final IF frequency is zero.
In other words, RF frequency is directly downconverted to baseband. To achieve this,
local oscillator frequency must be equal to the RF signal frequency. For phase and
frequency-modulated input signals, the spectrum is double-sided. When such a signal is
brought to zero-IF with a single mixer, the two sides of the spectrum overlap producing a
single-phase output. As a consequence, LO with quadrature outputs (Figure 1.2) must be
used to avoid the loss of information. This structure produces I (in-phase) and Q(quadrature) outputs 90 degrees out of phase with each other.
In zero-IF receivers the image problem previously discussed in heterodyne receivers is
eliminated. Thus, there is no need for the image reject filter. Furthermore, the channel-
select filter becomes a low-pass filter that is more flexible and easier to implement than
bandpass filters. These architectural advantages that result in cost reduction of homodyne
receivers add to their increasing popularity.
An important disadvantage of zero-IF frequency is that 1/f noise and DC offset at the
output of a mixer can now directly corrupt the spectrum of a desired signal. The most
severe DC offset is created in the process of "self-mixing". Self-mixing arises when LO
signal leaks through the LO port to the mixer input. The leakage signal mixed with the
33
LO signal translates directly to DC. DC offsets produced this way are almost impossible
to remove because they are time-varying and thus difficult to distinguish from the actual
signal. In addition, since leakage from the local oscillator through the antenna is more
significant in homodyne receivers, it can cause interference in other receivers using the
same wireless standard. Mismatches between the amplitudes of the I and Q signals as
well as the errors in the 90-degree phase shift can also severely degrade the SNR of the
output signal [3].
2.2.3 Digital Receivers
Much progress has been made recently in the analog-to-digital converter (ADC) and
digital signal processing (DSP) technology, the most crucial factors to make digital
receiver architectures possible. Today's cutting edge ADCs can sample analog signals in
the range as high as hundreds of MHz, thus allowing IF sampling [6]. The second set of
mixing, filtering and demodulation can all be performed in the digital domain. All the
basic principles of the theory of operation of the analog architecture apply to digital
receivers. In addition, digital architectures are more flexible, smaller in size, cheaper,
more accurate, and some problems like DC offsets, mismatch and noise problems are
eliminated. Digital modulators and demodulators can be implemented completely in
software. Software allows for changes and advancements without having to replace the
hardware. Direct conversion of the RF signal at the antenna into the digital domain is still
not possible mainly because today's ADCs are not sensitive enough to extremely low
signals levels and high frequency of the RF signal is impossible to sample. Therefore, at
least one IF stage must be implemented in the analog domain. However, according to the
Nyquist sampling theorem the sampling rate of the ADC must be at least twice the
frequency of the carrier frequency requiring sampling rates on the order of several
hundred MHz. A converter running at these high rates consumes substantial amount of
power and usually has resolution and dynamic range that are too small to satisfy market
requirements for practical receivers. One solution to these problems is to sample at the
second IF, which adds more analog components into the system. A more progressive
34
method is to use a subsampling technique also used in this thesis project. This topic is
discussed more thoroughly in the next chapter.
35
36
Chapter 3
Subsampling Radio Frequency Design
3.1 Subsampling
When performing subsampling (undersampling, bandpass sampling, harmonic sampling,
or super-Nyquist) a high frequency carrier signal is sampled at a rate much lower than the
Nyquist frequency for the carrier signal. For example, a signal atfF=140MHz that has a
bandwidth of Af=4MHz is sampled using a high speed ADC at a sample rate of
f =60MHz. Three important observations can be made related to this example:
" The signal does not extend from DC.
" The sampling frequency is lower than the Nyquist frequency of 2fIF for the carrier
signal. Therefore, aliasing will occur.
* There is a possibility of losing critical information about the sampled signal in the
event aliased images of the carrier signal overlap.
According to Shannon's Information Theorem and Nyquist's Criteria, an analog signal
with a data bandwidth of Af must be sampled at a rate f, 2Af in order to avoid the loss
of information. This turns out not to be the only restriction that needs to be imposed on
the sampling frequency when the sample rate is lower than twice the signal carrier
frequency.
37
For signals that extend from DC to a frequency fa, where Af =2fa, if the Nyquist Criteria
is not obeyed, the signal data will be irrecoverably lost. As an illustration compare Figure
3.2 (Nyquist obeyed) to Figure 3.3 ( Nyquist not obeyed).
(a)
(b)
Figure 3.1: The effect of Nyquist sampling,fs=4fa. (a) Spectrum of the original signal. (b)
Spectrum of the sampling function. (c) Spectrum of the sampled signal.
38
(a)
(b)
(C)
Figure 3.2: The effect of destructive aliasing,f<2f,,.
(a) Spectrum of the original signal. (b) Spectrum of the sampling function. (c) Spectrum
of the sampled signal.
However, for signals that do not extend to DC, as in our example, from the beginning of
the section, the minimum required sampling rate is a function of the bandwidth of the
signal as well as of its position in the frequency spectrum. When subsampling the carrier
centered at fiF, even if fs < 2fIF, it is possible to recover all the relevant data stored in the
bandwidth around the carrier. To better understand the usefulness of subsampling and
how to make it work, it is necessary to review the basics of the sampling theorem.
A continuous-time signal xc(t) that undergoes periodic sampling is represented
with a sequence of samples x[n], where x[n]=x,(nT). T is the sampling period, and f, is
the sampling frequency, where fs=]/T The spectrum of the sampled signal x[n] can be
expressed as
X (f )= , 1 XT (f - nf) (3.1)T n=-
39
We see that the process of sampling creates replicas of the input signal spectrum spaced
atf, from-each other. An important fact to observe from Eq. 3.1 is that regardless of what
the sampling frequency is chosen to be, the sampling will cause either the actual signal or
an aliased component to fall between DC andf 3 /2 (Figure 3.4) [7].
CfAE I _ _ _ __ _ _
CASE 2
CASE
CASE 3
hA REPEATS:- ....
ff,
f" I jk
M=11; kAJJr Jf" f
flF
Figure 3.3: Frequency domain effects of sampling
In the case of Nyquist sampling, the image closest to baseband is located at the carrier
frequency fiF. However, in the case of subsampling (f, < 2fIF) aliasing will produce
replicas of the input signal closer to DC than in the case of Nyquist sampling. Some very
important conclusions can be derived from these observations:
0 Subsampling provides an alternative way for designing a mixer in digital domain. The
lowest frequency image is taken to be the desired downconverted signal. However,
care must be taken to select the sampling frequency properly to avoid destructive
interference between aliased images coming from positive and negative frequency
components of the input signal.
40
f.+f,.F
* Any signal that enters the sampler along with the desired signal will produce noise
that will fall between DC and f,12 that can corrupt the wanted signal. These noise
creating signals are almost inevitably produced in devices in the IF stage as a
consequence of their nonlinearity. Therefore, the unwanted signals must be
adequately filtered with an antialiasing bandpass filter before sampling is performed.
It is recommended to place a sharp transition surface acoustic wave (SAW) bandpass
filter prior to ADC, to eliminate part of that noise.
As previously emphasized, the selection of the proper sampling rate is essential to
preventing spectral overlapping of the aliased images and also to place these images at
the desired frequency location. The location of the spectral images of the sampled input
signal centered atfF is given by
f, = nf, fIF 1 (3.2)
where f1 is the desired image frequency, n is an integer, f, is the sampling rate, and fIF
is the ]IF carrier signal frequency. One should bear in mind that the IF carrier signal is
assumed to be sinusoidal and therefore has both positive and negative frequency
components at fIF and - fIF , respectively. Therefore, images of the input signal will be
created at both X (nf, + fIF ) and X (nf, - fIF). From this we see that if the center of the
IF signal frequency is equal to the multiple of the sampling frequency, these images will
exactly overlap each other, even if Nyquist's criteria is satisfied. We conclude that apart
from looking at the Nyquist's condition, one must consider Equation 3.2 to select the
sampling frequency that will not result in destructive aliasing.
One good example of subsampling in which the sample rate is chosen properly is
given in Figure 3.5. This is the same example presented at the beginning of this chapter.
41
f =60 MHz
\k-142 -140 -138 138 140 142 [MH
(a)
-180 -12) -60 6) 12) 180 [MHz)
(b)
N P N P N P N
40
18 22
80 100 140 16 [MHz]
(c)
Figure 3.4: Successful example of subsampling.
(a) Spectrum of the original signal. (b) Spectrum of the sampling function. (c) Spectrum
of the sampled signal.
It was found that sampling clock jitter noise can also alias into the sampled band
of interest and thus corrupt it. To minimize the jitter noise the sampling frequency should
be chosen to be as high as possible. The next section is devoted to the discussion of this
effect.
3.1.1 Sensitivity to Sampling Clock Jitter
When performing IF sampling, a clock signal is used to index the timing of sampling.
Ideally, the samples are taken at uniformly spaced intervals. In real implementations the
clock signal usually contains some jitter that will introduce an error to the data.
Therefore, one of the key concerns during IF sampling are aperture uncertainty and
aperture jitter. Aperture uncertainty is sample-to-sample variation in the encode process,
42
/\
and aperture jitter is the error effect of aperture uncertainty [8]. Aperture uncertainty has
one major effect, increase in system noise, and two minor effects, uncertainty in the
actual phase of the sampled signal and inter-symbol interference. The error signal
produced by aperture jitter and uncertainty increases in amplitude as the slew rates at the
input of the ADC increase. The slew rate shows how fast the signal is slewing through
the zero crossing of the input signal and it is expressed in volts. In a sine wave, the
maximum slew rate is at the zero crossing and it is defined by the first derivative of the
sine function evaluated at t=O.
v(t) = A sin( 2.ift)-v(t) = A2)7f cos( 2; ft) (3.3)dt
at the same point (t=O) the cosine function evaluates to 1 and
dv(t)= A2f =itter (3.4)
dt
The aperture uncertainty will produce error voltage that can be determined by multiplying
the input slew rate by the jitter.
Verror= Slew Rate x tjitter (3.5)
This equation shows that as analog input frequency increases, the error voltage increases
in direct proportion to the aperture uncertainty.
The ADC's SNR imposed by jittered sampling can be theoretically determined using the
following equation:
SNR= -2 0log[(2 }fIF tjitter rMs)] (3.6)
43
A more generalized equation is used to describe the effect of thermal noise and
differential nonlinearity.
SNR = -20log (2JfIFtijitterrms )2 < 2+e) + VnoerMS 2 2(3.7)
fIF = analog IF frequency.
tjitterrms = aperture uncertainty.
C= average DNL of converter (- 0.4 LSB).
Vnoiserms = thermal noise in LSBs.
N = number of converter bits.
We can measure aperture uncertainty by looking at SNR performance as a function of
analog input frequency. When FFT is done at sufficiently low analog frequency and when
thermal noise is rolled up into the quantization noise and jitter is neglected we arrive at:
-SNR
e=2NXlO 20 _ (3.8)
SNR = the low frequency SNR.
N = the number of converter bits.
. = average DNL (+thermal noise).
At high frequency, we can assume that jitter is a contributor to noise. Solving the general
equation for jitter brings us to:
(-SNR 22
1020 +
2NtjiterrMS = '' (3.9)
2Rf4F
44
SNR = the high frequency SNR.
N = is the number of converter bits.
F= average DNL (+thermal noise).
fiF = the IF analog input frequency.
The noise due to sampling clock jitter can greatly affect the SNR performance of the
ADC especially at high IF frequencies, given that the sampling frequency is held
constant. Let us define the ratio of the IF frequency and the sampling clock frequency as
the subsampling ratio m
fiFM fI. (3.10)
It can be shown that during the process of subsampling noise power of the sampling
circuit is multiplied by a factor of 2m and the clock phase noise power is amplified by m2
[3]. If a sinusoidal signal is sampled with a jittered clock, the resulting error of the clock
jitter spectrum can be distributed onto the sampled IF input. The ratio of the power
spectral density of the error signal to the power spectral density of the clock signal turns
out to be (fVF /f) exactly [9]. Therefore, to minimize this noise it is necessary to
maximize the sampling frequency or minimize the IF frequency, which usually has more
negative effects. Figure 3.6 illustrates how a desired signal can get corrupted by jitter in
the process of subsampling [9]. S. is the power spectral density of the error due to
jittered sampling. S, contains an infinite number of frequency components located at
frequencies dependant on the input signal carrier frequency (fVF) and the sampling
frequency (f,). The frequency component which is very close to the desired signal
frequency (fa) is shown in Figure 3.6. This frequency component has the most
destructive effect on the wanted signal.
45
(nC
0
M.
SE fn/f) 2 SC
Clock Spectrum, Sc
fadj fi
Frequency
Figure 3.5: Error caused by clock jitter when subsampling.
3.2 Subsampling Receiver Architecture
Using the subsampling technique, it is possible to design an RF receiver using only one
IF stage. After the first frequency downconversion and appropriate filtering, the
wideband carrier signal can be transferred into the digital domain using high speed, high
performance, wide dynamic range ADCs such as AD6640 or AD6644. We have seen that
subsampling has a very similar function to mixing and thus can be thought of as the
second downconversion. To prevent the loss of information, sampling frequency is
carefully chosen to avoid direct signal translation to baseband. Direct signal translation to
baseband would happen when the IF frequency is equal to the multiple of the sampling
46
s
frequency. A digital mixer with quadrature outputs is necessary to perform the final
conversion of the subsampled signal to baseband. This digital mixer consists of two
multipliers. With a complex numerically controlled oscillator (NCO) it makes a digital
frequency translator.
3.2.1 Numerically Controlled Oscillator
The NCO provides digital samples of sine and a cosine waves that are precisely 90
degrees out of phase. The sine and cosine digital samples run at the rate which is equal to
the ADC sampling clock frequency and the rate of the I and Q outputs of the frequency
translator. The precision of the digital frequency translator is so great that it allows
mixing down to baseband with no offsets. For wideband signals, sample rates can be as
high as several tens of MHz, which would require a lot of processing power in the DSP,
following the ADC. Unfortunately, currently available DSPs are not fast enough to
perform all the other subsequent functions like mixing, filtering and demodulation, for
data running at sample rates this high. Therefore, this data rate must be reduced first to
allow for proper data processing.
3.2.2 Decimating Low-pass Filters
Sample rate reduction or decimation is performed by so-called decimating low-pass
filters [10]. These filters usually consist of cascaded integrator-comb (CIC) filters, to
allow for an efficient decimation and interpolation. They are typically employed in
applications where the sample rate is much larger than the data bandwidth. CIC filters are
used for realizing large sample changes in digital systems. Their structure consists of an
integrator section operating at the highest sampling rate and a comb section operating at a
low sampling rate. The overall filter response is equal to the composite of all of these
filter responses.
47
The integrator section consists of N ideal digital integrator stages operating at high
sampling rate f. Each stage represents a single-pole filter with a unity feedback
coefficient. The transfer function for such an integrator is
1H , (Z)= _ 1, .(3.11)
The comb section consists of N comb stages and runs at the low sampling rate f, /R,
where R is an integer rate change factor or decimation rate. Each stage has a differential
delay of M samples per stage. The transfer function of a single comb stage referenced to
f, is
H c (z) =1z - Z-R . (3.12)
A CIC filter consists of an equal number of integrator and comb sections. The system
transfer function for the composite CIC filter consisting of N integrator and comb
sections is
N N Z~-RM )N = RM- - ]N
H(Z) = HN (z)HC (z) -I N -k (3.13)(1- Z ) k=O_
The frequency response can be obtained by evaluation of Equation 3.13 at
z = e j( 2,f /R) (3.14)
And is given by
f 31-2N
P(f )=sin ;TMf (3.15)sin R_ R _
48
Therefore, the response of the CIC stage is a low-pass filter whose characteristics are
defined by the decimation rate. The higher the decimation rate is, the smaller the
passband bandwidth is. An example of the frequency response from Eq. (3.15) is given in
Figure 3.8 for N=4, M=1, R=7, and f, =1/8. f, is a relative bandwidth and
f = 1- f, [10]. All frequencies are with respect to the low sampling rate.
z0
D-
zw
0-
40-
60-
80-
F-fc
PASS-BAND
1040 fc
2f(
ALIASING/IMAGINGBANDS
-*i2fc +- 2fci*II'I I
fA 1 2
FREQUENCY RELATIVE TOLOW SAMPLING RATE
3 3.5
Figure 3.6: An example frequency response for for N=4, M=1, R=7, andf, = 1/8.
It is a common practice to combine several CIC filters to implement higher decimation
rates. This is also done to achieve very narrow transition bandwidths and relax
requirements on individual filters. The total decimation factor is then equal to the product
of decimation factors of the individual stages. The output rate of the overall CIC filter
stage can be found from the equation
Folur f= anp _ ADC
=Mtotal
49
wherefsam1p_ADC is the frequency of the sampling clock in the ADC, and Mo,,i is the total
decimation factor of the CIC stage. The higher Mt,,L is, the smaller power consumption
in the subsequent stages is. I and Q data are processed in parallel within the CIC filters.
After coming out of this stage, the data are ready to be demodulated in a DSP.
3.2.3 Demodulator
Demodulation is performed with the goal to recover the original baseband signal sent
from a transmitter to a receiver with maximum SNR. The transmitted signal is a high-
frequency carrier modulated by the original baseband signal using some modulation
technique. Therefore, demodulation can be thought of as the inverse of modulation. To
make a proper demodulator, we have to have a thorough knowledge of the modulation
schemes used to modulate the signal. Modulation can be analog or digital.
3.2.3.1 Analog Modulation
Analog signals can be amplitude modulated (AM), phase modulated (PM), frequency
modulated (FM) onto a carrier, or modulated using combinations of these modulation
schemes. Modulated signal can be represented with the following equation:
x(t) = a(t) cos[alt + 0(t)] , (3.17)
where a(t) and 6(t) are parameters that can vary as functions of a baseband signal that
modulates the carrier. If we choose to modulate the amplitude of the carrier and keep the
phase constant we get amplitude-modulated AM waveform. In this case (3.17) becomes
XAAIWt) = A,1+ MxB(t)]cos Oxt , (3.18)
where m is called the "modulation index" and XBB(t) is the baseband signal. Modulation
index is defined as the ratio of the peak baseband signal amplitude to the peak carrier
50
amplitude and can take values between 0 and 1. However, AM is not a very popular
modulation scheme because information stored in the amplitude is more sensitive to noise
and requires from the power amplifier in the transmitter to be highly linear.
If a(t) is a constant Ac, and 0(t) is linearly proportional to the baseband signal, the carrier
is then phase modulated and given by
xpA(t) = ACcos[aOt +mxn(t)]. (3.19)
On the other hand, if dO/dt, which is equal to the angular frequency, is linearly
proportional to the baseband signal, then we have frequency modulation. The modulated
signal then becomes
xFM(t) Ac cos ct + m x 3B(t)dtj. (3.20)
Analog FM is more popular than analog PM because frequency modulation and
demodulation are more easily performed than phase modulation and demodulation [3].
3.2.3.2 Digital Modulation
If a carrier is modulated by a digital baseband signal, this is called digital modulation.
There are several advantages of using digital to analog modulation. The most important
ones are better sensitivity to noise and thus improved accuracy, and much higher channel
capacity [12]. In addition, large progress in very large-scale integration (VLSI) and DSP
technology have made digital modulation more economically attractive than analog
modulation. The equivalents of AM, PM, and FM modulations are called amplitude shift
keying (ASK), phase shift keying (PSK), and frequency shift keying (FSK). PSK and
FSK are more frequently in use than ASK for the same reasons FM and PM are more
frequently in use than AM.
51
Frequency shift Keying (FSK)
In digital frequency modulation schemes the frequency of the carrier changes to a number
of different values, depending on the baseband symbol that modulates the carrier. If FSK
results in a modulated waveform with phase discontinuities at the switching time, this is
called discontinuous FSK. Phase discontinuities are highly undesirable because they can
cause wide transmitted spectrum as well as spectral regrowth, if the envelope of the
signal is not constant. Envelope variation of a digitally modulated signals often happens
due to filtering and thus it is unavoidable. It is even more severe if phase steps are greater
and filter bandwidth smaller [3]. In case of envelope variation, it is possible to prevent
spectral regrowth if highly linear power amplifiers (PAs) are used in the transmitter. The
main disadvantage of this approach is that linear PAs are much less efficient than their
nonlinear counterparts and as such dissipate more power [3]. The expression representing
continuous phase FSK modulated signals is the same as in Eq. 3.20. However, in this
case XBB(t) takes discrete values since XBB(t) is a digital signal. For example, in binary
frequency shift keying (BFSK), frequency switches between 2 values corresponding to
baseband binary 1 or 0. By integrating m(t), which is a discontinuous function, we get a
smooth continuous waveform from which the phase function 6(t) is derived.
Phase Shift Keying (PSK)
In digital phase modulation schemes the phase of the carrier changes to a number of
different angles, depending on the baseband symbol that modulates the carrier. Binary
phase shift keying (BPSK) is considered the simplest PSK scheme in which 1 bit is sent
at a time. Carrier phase of 0 or 180 degrees is sent depending whether a bit 0 or 1 is sent.
BPSK modulated signal can be represented as either:
sBPSK(t) -C cos Ot 0 ! t T Tb (binary 1) (3.21)
52
or
SBI'SK(t) = Acos(w~ +fz) = -A, cosa W 0 t Tb (binary 0). (3.22)
In quadrature phase shift keying (QPSK) 2 bits are sent at the time and are represented by
four different phase angles. Using the same idea, 3 bits can be sent at a time and they can
be represented by eight phase angles (8-PSK) or even 4 bits (16-PSK). In the example
given for BPSK we can see that the phase of the carrier abruptly changes to a new value
in response to the change in the modulating baseband digital data. Discontinuities in
phase here have the same detrimental effects as in the discontinuous phase FSK.
It is possible to change the phase angle from one value to another in a continuous
fashion. In this way a constant amplitude can be achieved and a spectral re-growth can be
minimized if nonlinear amplifiers are used in the transmitter. It is desirable to use
nonlinear power amplifiers (PAs) as they exhibit higher efficiency and thus less power
dissipation than linear PAs. However, nonlinear PAs do not perserve the shape of I and Qsignals, which results in increase in the spectrum bandwidth. In addition, it was found
that envelope variation of I and Q signals due to filtering is stronger at abrupt phase
changes [3]. Thus, if continuous phase modulation schemes are used in combination with
nonlinear PAs, the effects of spectral re-growth can be minimized.
Continuous phase PSK modulation is equivalent to continuous phase FSK. This
can be concluded from the fact that frequency is a derivative of phase.
Minimum Shift Keying (MSK)
MSK is a binary digital modulation with a modulation index of 0.5. It can be considered
either a phase or a frequency modulation. During one bit period, phase changes smoothly
by 90 degrees. The phase advances by 90 degrees at the end of a bit period whenever the
data bit is 1. On the other hand, for each data bit of 0, the phase retards by 90 degrees at
53
the end of each bit period. Since the phase is continuous, the frequency or the derivative
of the phase is also changing. If the data bit is 1, the frequency is higher, and when the
data bit is 0, the frequency is lower. This is the reason MSK can be thought of as
frequency modulation. The MSK modulated signal is given by
X(t) =Ac cos cat + Jd(t) -2dt = Ac cosOkt +--( 1) t + soj. (3.23)
The change in frequency of the MSK modulated signal that results from the change in
data from 0 to 1 or vise versa, can be found as a function of the data rate fb=]/Tb. Tb is the
bit period. When the data bit is 1, the frequency will increase by the following amount
from the carrier frequency
Af+= A 1 A(p(t) 1 f 12 1 f(3.24)2ff At 21r T, 2ff 4
Similarly, it can be found that if the input bit is 0, the frequency will decrease by the
same amount from the carrier frequency
Af = fb. (3.25)4
Therefore, the peak-to-peak RF frequency difference is
Af = Af + - Af f= . (3.26)2
Because MSK can be thought of as frequency modulation, we can associate a modulation
index to the MSK modulated signals. The modulation index h in digital frequency
modulation has the same expression as the analog FM index of modulation 6 and is given
by
54
h = Af (3.27)fm,
where Af is the effective frequency difference found in Equation 3.26, and f, is the
modulation frequency of the data rate. Thus, for MSK h=0.5. A modulation index of 0.5
tells us the minimum frequency difference that allows two FSK signals to be coherently
orthogonal. In other words, this modulation index results from the minimum peak-to-peak
frequency difference that allows orthogonal detection. That is what the word minimum in
MSK corresponds to.
Gaussian-Filtered Minimum Shift Keying (GMSK)
GMSK is a type of MSK that utilizes a Gaussian pulse-shaping premodulation filter to
narrow the transmitted spectrum of MSK. In effect Gaussian filter smooths the phase of
the MSK signal and thus reduces the instantaneous frequency variations over time [11].
The result of doing this is significantly reduced sidelobe levels in the transmitted signal
spectrum. GMSK exhibits very little intersymbol interference (ISI). Gaussian
premodulation filter response is often specified in terms of its relative bandwidth or 3 dB-
bandwidth-bit duration product or BT
BT = (Filter _ Bandwidth) . (Bit _ Period) B -Te = - Bandwidth [12]. (3.28)fA Bit_ Rate
Values of BT ranging from 0.2 to 0.5 are common in practice. The occupied RF
bandwidth for GMSK as a fraction of the data rate containing a given percentage of
power can be found using Table 2.1 [12].
55
BT 90% 99% 99.9% 99.99%
0.2 GMSK 0.52 0.79 0.99 1.22
0.25 GMSK 0.57 0.86 1.09 1.37
0.5 GMSK 0.69 1.04 1.33 2.08
MSK 0.78 1.20 2.76 6.00
Table 3.1: The occupied RF bandwidth for GMSK as a fraction of the data rate
containing a given percentage of power.
The DECT standard employs a BT of 0.5 and this value was used in this thesis also.
Using Table 2.1 we can calculate that the occupied RF bandwidth for a 2.5Mbps signal,
with a BT of 0.5 containing 99.9% of signal power, is 1.33 -2.5Mbps = 3.325MHz.
Similarly, for a 10kbps signal with the same BT and signal power, the occupied
bandwidth is 1.33 -1Okbps = 13.3kHz .
We can write a GMSK modulated signal as
s(t) = A . cos[oRFt + y(t)], (3.29)
where, yp,(t) is the phase that contains all the information about the modulated data. The
time domain response of a GMSK modulated signal with BT=0.5 is shown in Figure 3.9
[12].
56
fRF = 80 MHz, fDATA = 10 MHz
2
RF0
-2
Phase-3
-4
Data -5
0 100 200 300 400 500 600
TIME (nsec)
700 800 900 1000
Figure 3.7: GMSK time domain waveforms.
Therefore, it is first necessary to recover the phase information of the received RF signal
to demodulate the data. To obtain a useful expression that will help us in this goal, it is
useful to know that GMSK is a type of quadrature modulation. A quadrature modulator
contains a serial-to-parallel (S/P) converter that separates consecutive bits of the serial
data stream. The separated bit stream that modulates the carrier represented by cos(CORFt
is called the "in-phase" or I component of the bit stream. The other bits that modulate
sin(WRFt) carrier are called the "quadrature" or Q data. Quadrature modulation I is
illustrated in Figure 3.10 [3].
57
A WA AA A A A
\ V V V V V V V
I
+ S(xt ( t)Converter sinWj t
Q 0
_JF1Lih
t
Figure 3.8: Quadrature modulation.
The output of the quadrature modulator can be represented in the following way
x(t)=ii cos(at) + Q sn = * *. 2 _ _ 2j
Reorganizing (3.30) we get
x(t) = -[(I - jQ) -e i(" + (I2
Let
I-jQ= I2 ± Q2 . j
and
I+ jQ= I2- + Q2 .e-',
where,
yp = tan'(Q /I).
+ jQ) -e-j'"".
58
BinaryBaseband
Data
BinaryBaseband
Data
Q
(3.30)
(3.31)
(3.32)
(3.33)
(3.34)
Equation (3.31) can now be rewritten as
'F 0 + -jORb'-px(t) = I2 +Q 2 Le jFtQ +e j (3.35)
Finally, we can express x(t) in the following form
x(t)= I 2 +Q2 .cos(aktt +y). (3.36)
This expression has the same form as the one in Eq. 3.29. It is obvious now that to
recover ((t) from the received modulated carrier signal, the best way is to recover I and
Q data and insert them in Eq. 3.34.
It would require the implementation of a feedback system using a phase-locked loop
(PLL) to recover the phase directly, which is a much harder task.
More details about modulation can be found in [3], [11], and [12].
59
60
Chapter 4
Implementation of the Subsampling Receiver
In the previous chapter major architectural issues of the subsampling receiver were
discussed. A block diagram of the receiver used in this thesis project is shown in Figure
4.1.
ANALOG IF STAGEI II I
DIGITAL UNIT
I I
C(kV E M N [D(D
NCO
CLOCK P M E0
RF BOARD DIGITAL BOARDS
I- -I-- 'I
Figure 4.1: Subsampling receiver block diagram used in this thesis project.
Starting from this block diagram, the next three major steps towards implementing the
receiver are: frequency planning, circuit implementation and selection of the optimum
61
M -1.
I
LI I
commercially available components, and RF printed circuit board (PCB) layout design.
They will be discussed in detail in the coming sections.
4.1 Frequency Planning and Component Selection
One of the major constrains of this thesis project is the requirement that the subsampling
receiver be implemented using discrete commercially available components. The
availability of these components affects the frequency planning a great deal. For this
reason these two steps towards receiver implementation are discussed together.
The low power transmitter, which is a part of the Security Sphere, is designed to perform
Gaussian Frequency Shift Keying (GFSK) or Gaussian Minimum Shift Keying (GMSK)
modulation at a data rate of 2.5Mbps. This data rate translates to 3.325MHz of
bandwidth, as explained in the previous chapter. The RF output carrier center frequency
of the transmitter is in the DECT (Digital European Cordless Transmission) band i.e.
between 1.88 and 1.90GHz. Thus, the components in the IF stage of the receiver up to
and including the mixer must operate in this frequency range. For the testing purposes,
the center frequency of the input RF signal is chosen to be 1.89GHz. In addition, the
receiver is designed to meet the DECT standard which requires at least -82dBm of
receiver sensitivity. This means that the cascaded noise figure and thus the gain of all
stages in the receiver front end must be such to result in at least this sensitivity.
The first element in the receive path is a band-select filter. It is necessary to filter the
input signal upon reception to reject unwanted signals and therefore improve the
sensitivity. Murata's DFC21R89PO20 HHE ceramic filter is chosen to perform this
function. It was marketed for the DECT frequency band. The center frequency of the
filter is at 1.89GHz and its bandwidth is 20MHz. It has a very small insertion loss of only
2dB max and a ripple of 0.5dB max. The transfer characteristics of this filter in the
frequency range of interest are shown in Figure 4.1. The curve in the figure that peaks at
1.89GHz is the attenuation curve and the other one represents the return loss.
62
2
6
8
0 0
0
0 -2
31
0 4
cc
03
1600.0 18C0.0 2000.0Frequency (MHz)
Figure 4.2: Transfer characteristics of the band select filter DFC2lR89PO20 HHE.
Upon reception the RF signal is very weak. After band-select filtering to eliminate part of
the noise, this signal has to be amplified with a low noise amplifier (LNA) to further
improve the signal-to-noise ratio. Because this subsampling receiver contains only one IF
stage, all the gain stages must be implemented before analog-to-digital conversion. To
meet the receiver sensitivity spec, it was decided to use two gain stages. One must occur
immediately after the first band-select filter to enable further processing of the input RF
signal. The real question is where to put the second gain stage. One can think of two
possibilities: before or after the mixer stage. There is one major disadvantage of placing
an amplifier after the mixer stage. Mixers are devices that produce a lot of noise. Phase
noise that enters mixers through their local oscillator input increases the overall noise
figure at the output even further. Placing an amplifier there would increase both the
signal level and the noise level leaving the SNR unchanged. However, the SNR would be
higher if the amplification occurred before the mixer. We conclude that it is best to place
63
the two LNAs in series with each other and prior to the mixer stage. These stages are
implemented using Macom's AM50-0004 LNA. It has a high dynamic range and operates
in the frequency range from 1400 to 2000MHz. It also has a high gain (-14dB at
1.89GHz and 5V supply voltage), low noise figure (-1.4dB at 1.89GHz and 5V supply
voltage), and high input IIP3 (-15dB at 1.89GHz and 5V supply voltage). The functional
block diagram for this chip is presented in Figure 4.2.
VDD
L2
C2
IN OUT
CClC1
.45,8
RI (See note 5)
Figure 4.3: Functional block diagram for AM50-0004 LNA.
Preceding the mixer stage another band-select filter is necessary to reject the noise
created by the LNAs. DFC21R89PO20 HHE ceramic filter is again selected to perform
this function.
IAM-91563 manufactured by Hewlett-Packard is used in the mixing stage. This is an
active mixer, which essentially means that it is an amplifier with a nonlinear transfer
function. A schematic of the application circuit used in this thesis project is shown in
Figure 4.3.
64
LOInput
RF C7 C5 VInput C1
0_ itL3 C6
Li = 0 RFC IF-,I L2 Output
MLIN C3 1-+-T =C2 C4
Figure 4.4: Schematic of the application circuit for IAM-91563 mixer.
LO (local oscillator) input is provided by the National Semiconductor's LMX2330L low
power frequency synthesizer. Although only one LO input was needed for this project, a
dual frequency synthesizer was used for testing purposes. This is explained in more detail
in the section about PCB layout design. Functional description and programming of the
frequency synthesizer chip is contained in the Appendix B of this thesis. The data sheet
for LMX2330L was the main source of information for this part. The circuitry used to
program this chip is described here, however.
LMX2330L requires three inputs that have to be provided by the external circuitry:
Clock, Data, and Load Enable. Programming words for the synthesizer are stored in
D2674A NMOS 64 Kbit (8Kb x 8) UV EPROM. Two synchronous 4-bit binary counters
74LS 163 provide inputs to the EPROM. The outputs of the EPROM are fed through two
MM74HC74A dual D-type flip-flops and one SN74F04N inverter chip for buffering
purposes. The schematic of this circuitry is provided in the Appendix A.
It was explained in the previous chapter that before subsampling the signal must be
appropriately bandlimited with a bandpass antialiasing filter. Selecting a SAW filter to
perform this function is one of the most important and difficult steps in receiver design.
Since the input RF signal in this project is allocated for DECT, it was desirable to adopt
the frequency planning commonly used in DECT. Another constraint for the selection of
65
the SAW filter is that the data bandwidth in this project is 3.325MHz. SAW filters at
110.592MHz produced for DECT standard have bandwidths smaller than 3.325MHz.
SAWTEK is the only manufacturer that provides filters of varying bandwidths. It
produces two standard families of filters centered at 70 and 140MHz. 140MHz family is
selected because image rejection is better at higher IF. Within this family a filter with the
bandwidth closest to the required spec is a 4MHz 854909 SAW filter. The transfer
characteristics for this filter are provided in Figure 4.4.
Horizontal: 2 MHz/DivVertical: 10 dB/Div
Figure 4.5: Transfer characteristics for SAWTEK-854909 bandpass filter.
The next component in the signal path and the most critical one for the subsampling
receiver performance is analog-to-digital converter. Special attention was paid to
selecting a high performance ADC. Analog Device's AD6644 is a 65MSPS (mega
samples per symbol) high dynamic range 14-bit ADC that can accept inputs with
frequencies up to 250MHz [13]. SNR for the high speed ADC is extremely sensitive to
the sampling clock timing jitter. This effect was described in the previous chapter and can
also be observed from the following expression derived explicitly for AD6644:
66
---- _ _ I --- -- ----
.. ...........
----- -- -------- ------ -4-
--- -- -------- ---- ----------- -------
SNR = -20 x log ( 2 E)1 +(2 Xz XfANALOG X tjRMS) 2 VNOISE _ RMS 2-1/2
= IF analog input frequency.
= rms jiter of the encode (rms sum of encode
source and internal encode circuitry).
= average DNL of the ADC (typically 0.41 LSB).
= number of bits in the ADC.
VNOISE RMS =V rms thermal noise referred to the analog input of the ADC (typically
2.5 LSB).
As the analog input frequency is increased, degradation of the SNR due to timing jitter is
even higher. This is illustrated in Figure 4.5 [13].
0.1 0.2 0.3JITTER - ps
0.4 0.5 0.6
Figure 4.6: SNR as a function of rms jitter for different analog input frequencies.
From this figure we can conclude that for analog input frequency of 140MHz sampling
clock jitter in the subpico-second range is necessary to obtain 60dBs of SNR.
67
where:
fANALOG
tJ RMS
N
80
75
70
65zMl
60
55
AIN =30MHz
-- AIN =70M Hz -
AIN =11OMHz
AIN =15OMHz
AIN=190MHz
0
Unfortunately, clock oscillators with such low jitter spec cannot be found. Connor-
Winfield is the leading company in producing high quality clock oscillators with low
jitter. S 15R8-60MHz TTL oscillator has only 5 ps rms jitter, which is the best jitter spec
that currently exists in industry.
AD6644 is specifically designed for software radio applications and is a part of the
Analog Device's SoftCellTM Multicarrier Transceiver Chip set. It interfaces well with
AD6620 digital decimating receiver. This chip implements the following stages in the
subsampling receiver described in Figure 4.1. in the previous chapter: digital frequency
translator and two cascaded integrator comb FIR filters. In addition it has a RAM
coefficient FIR (RCF) lowpass filter [14]. This is also the only commercially available
product that can perform these functions. Therefore, it was the obvious choice for this
thesis project. Because of the time constraints of the project, it was decided to use to
evaluation board for AD6620 rather than to implement another board that would also
include it.
A simple functional block diagram for AD6620 is shown in Figure 4.6.
Real, RAM Serial orDual Real, CC 2
', CIC 5 ' Coefficient Output Parallel
or Complex Q Filter Filter Filter maFo-mso-OuputsInputs
1cos-sin
ComplexNCO,1
Figure 4.7: Functional block diagram for AD6620.
The NCO has a 32-bit resolution. Following the NCO is the first cascaded integrator
comb FIR filter shown in Figure 4.6 as CIC 2 . It is a second order, fixed coefficient filter
and it can reduce the sample rate by a programmable factor that ranges between 2 and 16.
CIC' is the second integrator comb FIR filter with fixed coefficients. It is a fifth order
filter and it can further reduce the sample rate by a programmable factor that ranges
68
between 1 and 32. The overall response of these two stages is defined by user selected
decimation rate. The higher the decimation factor, the smaller the overall filter
bandwidth. The final stage of AD6620 is a sum-of-products FIR filter with
programmable 20-bit coefficients. The maximum number of taps this filter can handle is
256. Decimation rate for this stage is programmable from 1 to 32. The overall filter
frequency response of AD6620 is the composite of CIC2 , CIC 5 , and RCF. Basic block
diagram of the AD6620 Evaluation Board is shown in Figure 4.7 [14].
Lat
H ch
Sp L LcLe a a ae Tant scevd c c
D
PC Printer Port
Figure 4.8: Basic AD6620 Evaluation Board block diagram.
In addition to AD6620 evaluation board, two software programs are also utilized.
AD6620 Filter Design Software assists the user in designing a desired composite
response of the three filter stages that is optimized for use with the AD6620. Once the
filter design is finished, the files created in this process can be downloaded to the
AD6620 with the Control Software. This software also allows the user to select the NCO
frequency. This is the frequency of the desired signal image closest to DC. For example,
in case of 140MHz IF signal, after subsampling the image closest to DC will be located at
20MHz. More information about AD6620 and two software programs can be found in the
datasheet, application notes, and manuals for AD6620 [14], [15], [16].
69
4.2 Printed Circuit Board Layout Design
The electrical characteristics of the printed circuit board (PCB) used to connect the circuit
components in an RF frequency product have a crucial role on the performance of that
product. Special care was taken to minimize the receiver size, parasitic elements such as
parasitic inductors and capacitors, and noise. Other issues such as grounding, decoupling,
and transmission line impedance affecting successful RF PCB layout were also
considered. Manufacturer's recommended PCB configuration was followed when
supplied. PCAD 2000 layout program was used to draw the schematics and PCB layout
in this project.
One of the first considerations in the PCB design is how many routing layers and power
planes are required for best functionality. Based on the noise immunity of the
components used in this project, number of traces to be routed, and impedance control, it
was decided to implement a 5 layer board.
Special attention was used for proper use of micro-strip technology to implement outer
signal traces on the PCB that result in 50 Q impedance. In general, RF signals that run
over a ground plane form a micro-strip transmission line. The characteristic impedance of
the line is defined by its dimensions and must be properly terminated to prevent it from
behaving reactively. In this thesis project 50-ohm termination was used since the
components utilized were designed to be driven and to drive 50 Q impedance.
The LNA datasheet recommends an FR4 dielectric thickness of 0.008" yielding 50 Q line
width of 0.015" to be used in the PCB layout for the LNA. The recommended RF
70
metalization is 1 ounce copper. In other words, the thickness of copper used in PCB
fabrication should be 1 ounce
Since no other manufacturer specified any such preference, it was decided to use these
dimensions for the transmission lines. The PCB was manufactured with Advanced
Circuits company. They use FR4 fiberglass as dielectric material. It has a relative
permittivity of 4.8. The micro-strip calculator written by Dan McMahill [17] is used to
calculate the impedance of the transmission lines to be 46.4 Q, given their dimensions
and material used to implement them.
Much care was taken in increasing the isolation of the LMX2330 frequency synthesizer
to prevent the leakage of the LO signal into the other parts of the board, especially the
ones in the front end. Faraday shield consisting of a grounded conductor surrounding the
synthesizer circuitry is used to minimize parasitic capacitance that could potentially
couple the LO signal with the sensitive parts of the board. The RF synthesizer in the
LMX2330 dual synthesizer chip was used only. However, the external component layout
for the second synthesizer was constructed with different trace lengths and component
distribution for testing purposes.
Ground planes were used for isolation of most of the analog parts. The input and output
matching inductors in the SAW filter external matching networks were placed
perpendicular to each other to minimize any mutual inductance which would couple input
and output ports. This is done in addition to adding a ground plane because the high
insertion loss makes SAW components more sensitive to the effects of the RF
feedthrough than other RF components.
For matching purposes and to increase flexibility a shunt transmission line is added to the
input of the mixer. The dimensions of the metal tab are chosen to obtain a line with the
real part of the impedance approximately equal to 50 Q. The length of the line is
adjustable by moving the position of the shorting tab between the line and the ground
pad.
71
All the circuit schematics and PCB layouts are given in Appendix A.
72
Chapter 5
Testing and Results
Testing of the subsampling receiver proceeded in two stages: testing of the analog RF
board and testing of the ADC and the functions implemented in digital domain. The
functionality of the overall system was demonstrated by comparing the demodulated
GMSK time domain phase information to the theoretically predicted values for various
data patterns. More emphasis was placed on testing the subsampling function. 1.89 GHz
GMSK modulated signal used for testing was created by Rohde & Schwartz signal
generator. The generator has the frequency range between 300 kHz and 3.3 GHz.
5.1 Analog RF Board Testing
The functionality of the blocks up to the ADC was tested on the analog RF board. The
spectrum of the RF signal was measured at various test points using the HP 8563E
Spectrum Analyzer. No major loss was observed in the receive chain. Demonstration of
the functionality of the SAW filter was shown in Figures 5.1 and 5.2. LO output from the
synthesizer is shown in Figure 5.3.
73
ATTEN 1OdB
RL OdEBm
D
VAVG 8510 d B/
MKR -15.OOd~m
139.80MHz
CENTER 140.OOMHz
RBVw 3OOkHz >*VBVW 1OOkHz
SPAN 20.OOMHzSWP 50.Oms
Figure 5.1: GMSK modulated signal at the input of the SAW filter.
ATTEN ±OdB
RL Od~m
VAVG 100±0dB/
MI<R -S0.150dBm
140 . 40MHZ
VID AV#1_O
CENTER 140
RBEw 3OOkHz- OOMHz
XVS V 100kHz
SPAN 20.OOMHZ
SWP 50.O Ors
Figure 5.2: GMSK modulated signal at the output of the SAW filter.
74
VID AVG# 0
D
ATTEN 10dE
RL OdEm I 0d8/MKR -15.5OdBm
1.75020GHz
CEN ER!1.7 000 GH2
CENTER I . 75000GHz
REw 3OOkHz -V8W 100k Hz
SPAN 20 .OOMHz
SWP G 0. Oms
Figure 5.3: LO output from the synthesizer.
5.2 Testing of the ADC
One of the major issues in this part was selection of the sampling clock frequency. The
maximum sample rate AD6644 can handle is 65MHz. 60MHz was chosen since this was
the highest frequency clock with minimum jitter that doesn't result in destructive aliasing
of the sampled 140MHz IF signal commercially available. The Control Software can be
used to bypass AD6620 on the evaluation board. The bypass mode allows the AD6644
ADC data to be latched twice and captured by the on board FIFO shown in Figure 4.7.
This enables the data coming out of the ADC to be downloaded to the PC for processing.
The Control Software allows us to view the spectrum of the data coming out of the
AD6644. Once it was observed that the spectrum of the sampled data had a frequency
75
component located at 20MHz as predicted theoretically, the testing moved to the next
stage.
5.3 Testing of the Functions Implemented in
Digital Domain
AD6620 receive signal processor was programmed using the AD6620 Filter Design
Software. Filter specifications chosen for this project are given in Figure 5.4.
Figure 5.4: AD6620 composite filter specifications.
The passband of +/- 15kHz rather than +/- 13.3/2kHz was selected to provide some space
for testing with higher data rates than 10kbps with no observable negative effects on the
receiver performance for 10kbps input signal. The total decimation factor is chosen to be
256. This enables the final filter stage RCF (RAM Coefficient Filter) to calculate the
maximum number of taps AD6620 can provide, which is 256. The number of taps is
76
equal to the decimation rate for the single channel real mode for decimation factors less
than or equal to 256. This is because AD6644 ADC and AD6620 evaluation board use
the same clock of 60MHz. With 256 taps we get best performance out of the filters.
Once these filter specifications were given to the evaluation board software, the
performance of two possible filters was computed. The decimation rate was distributed
between the three stages by the software in each of them in the following two ways: Filter
I CIC 2 =8, CIC 5 =32, and RCF=1, and Filter II CIC2 =16, CIC 5=16, and RCF=l. Filter
II was chosen since it minimizes power consumption in the CIC5 and RCF filter stages.
The composite response of Filter II is given in Figure 5.5.
Composite Frequency Response (Hz)
10000 20000 30000 40000 500000-------------------
-20
-40
-60
-80
~ 100-
-140
Figure 5.5: Composite frequency response of the AD6620 CIC 2 , CIC5 and RCF filter
stages used in this project.
The input RF signal used for testing the overall functionality of the system was -50dBm
strong. The data rate of the modulation binary stream was chosen to be 10kbps.
Unfortunately AD6620 is not designed to handle signals modulated with high data rate
baseband streams in the Mb range. As mentioned previously, the number of taps is equal
77
to the decimation rate for the single channel real mode. For high data rate baseband
streams in the Mb range, decimation factor has to be small in order not to violate Nyquist
criteria. Small decimation factor results in small number of taps. With smaller number of
taps, the filter implemented by AD6620 will have worse characteristics. That is why the
idea of building a receiver that can handle 2.5Mbps data rates of the modulating signal
was abandoned.
The I and Q data were extracted from the AD6620 board using the Control Software and
then processed in Matlab using the theory presented in section 3.2.3.2 to obtain the phase
of the modulated signal.
The pattern of the modulating stream was initially chosen to be 00 and 11. As presented
in section 3.2.3.2 the phase of the GMSK modulated signal advances by 90 degrees at the
end of a bit period whenever the data bit is 1. Similarly it retards by 90 degrees at the end
of a bit period whenever the data bit is 0. Experimental data shown in Figure 5.6 and
Figure 5.7 agree with this theory. The phase goes between if and - )z.
data pattern = 00
200 400 600time
800 1000 1200
Figure 5.6: For 00 data pattern the phase of the GMSK modulated signal has a constant
negative slope as it constantly decreases.
78
3
2
1
-1
-2
-3
-4 L0
a)U)CU.C OHCL
data pattern = 114
31
2/
0-
-1
-2
-3
-4 ----0 200 400 600 800 1000 1200
time
Figure 5.7: For 11 data pattern the phase of the GMSK modulated signal has a constant
positive slope as it constantly increases.
The next step was to determine if phase indeed changes by 90 degrees when baseband
signal switches from 0 to 1 and vice versa. From Figures 5.8 and 5.9 we can see that it
changes by a little bit less than 90 degrees due to the constant phase offset that
continuously adds error. The phase offset is even higher for data patterns shown in
Figures 5.10 and 5.11.
79
2.5
2
c.
1.5
data pattern = 01
0.510 200 400 600 800 1000 12
time
Figure 5.8: Demodulated phase for 01 data pattern.
data pattern =0011 00112f
1.5
0.51
(DCD)
-
0
-0.5
-1
-1.51
0 200 400 600 800 1000time
1200
Figure 5.9: Demodulated phase for 0011 data pattern.
80
00
1
data pattern = 1111 1011 0010 0000
200 400 600time
800 1000
Figure 5.10: Demodulated phase for 1111 1011 0010 0000 data pattern.
data pattern = 0011 0011 0000 1111 0000 1111 0101 0101
3
2
0
-2
-3
0 200 400 600 800 1000time
1200
Figure 5.11: Demodulated phase for 0011 0011 0000 1111 0000 1111 0101 0101 data
pattern.
81
3
2
-10
-2
-3
-40 1200
MA-4
The phase offset in Figures 5.8 through 5.11 is data dependent as it has a different value
for different data patterns. It was determined that it comes as a consequence of the fact
that the spectrum of the sampled data after the NCO frequency downconversion to
baseband is not centered at 0 Hz exactly. The error that results from constant phase offset
in the system can be corrected by careful selection of the NCO frequency that will bring
the downconverted signal closer to baseband. An even better solution would be to utilize
a corrective feedback loop, which due to the time restrictions could not be implemented
in this thesis project. A less complicated solution would be to add code bits to average the
phase error to zero.
82
Chapter 6
Conclusion
6.1 Summary
The main focus of this thesis project was to explore the subsampling technique and use it
to design and implement a radio frequency receiver with discrete commercially available
components. Subsampling allows digitization of the received signal at the first IF, thus,
eliminating the second analog IF stage. Digital architectures are more flexible, smaller in
size, cheaper, more accurate, and some problems like DC offsets, mismatch and noise
problems are eliminated. Digital demodulator is implemented in software. Software
allows for changes and advancements in demodulation scheme without any need to
replace the hardware.
The functionality of the receiver was demonstrated with -50dBm GMSK modulated
signal at 1.89GHz center frequency. The data rate of the modulation binary stream was
chosen to be 10kbps. Since AD6620 is not designed to handle signals modulated with
high data rate baseband streams in the Mb range, the idea of using 2.5Mbps stream to
modulate the RF carrier had to be abandoned. The major problem observed was a
constant phase offset that continuously adds error to the demodulated phase. It was
shown that this offset is data dependent.
83
6.2 Future Work
Some of the future efforts related to this work would be to perform the demodulation in
real time in a DSP software and also to correct the data dependent phase offset. The next
version of the demodulator should also be able to extract data bits from the phase. One of
the better ways to correct the phase offset would be to implement a feedback loop. An
even better solution would be to add code bits to average the phase error to zero. Another
step further would be to integrate all functions implemented in a digital domain on a
single chip. This will allow for flexibility that would enable optimizations previously
constrained by using discrete commercially available components.
84
References
[1] D. R. McMahill, Automatic Calibration of Modulated Fractional-N Frequency
Synthesizers. Ph.D. Dissertation, Massachusetts Institute of Technology, June 2001.
[2] R. C. Dixon, Radio Receiver Design. Marcel Dekker Inc, 1998.
[3] B. Razavi, RF Microelectronics. Prentice Hall, 1998.
[4] H. W. Ott, Noise Reduction Techniques in Electronic Systems, 2 ed., John Wiley &
Sons, Singapore, 1989.
[5] K. B. Patel, Ultra Low-Power Wireless Sensor Demonstration System: Design of a
Wireless Base Station. Master's Thesis, Massachusetts Institute of Technology, February
2000.
[6] B. Brannon, AN-502 Application Note: Designing a Superheterodyne Receiver Using
an IF Sampling Diversity Chipset, Analog Devices.
http://www.analog.conlibrary/applicationNotes/RFComms/IF/AN502.pdf.
[7] W. Kester, Section 5: Undersampling Applications. Analog Devices,
http://www.analog.contechnology/amplifiersLinear/training/pdf/Section5.pdf.
[8] B. Brannon, AN-501 Application Note: Aperture Uncertainty and ADC System
Performance, Analog Devices.
[9] D. H. Shen, Architecture and Design of a Monolithic Radio Frequency Receiver.
Ph.D. Dissertation, Stanford University, March 1997.
[10] E. B. Hogenauer, An Economical Class of Digital Filters for Decimation and
Interpolation. IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.
ASSP-29, No. 2, April 1981.
[11] T. S. Rappaport, Wireless Communications. Prentice Hall, 1996.
85
[12] L. E. Larson, RF and Microwave Circuit Design for Wireless Communications.
Artech House Mobile Communications, 1997.
[13] Analog Devices' AD6644 Datasheet, Rev. 0, 14-Bit, 40 MSPS/65 MSPS A/D
Converter. http://www.analog.com/productSelection/pdf/AD6644 0.pdf, 2000.
[14] Analog Devices' AD6620 Datasheet, Rev. A, 67 MSPS Digital Receive Signal
Processor. http://www.analog.com/productSelection/pdf/AD6620 a.pdf, 2001.
[15] AD6620 Evaluation Board Manual, from Analog Devices, Rev 2.10, 27 April 2000.
[16] Application Notes: Designing Filters with the AD6620, Analog Devices,
Greensboro, NC.
[17] Daniel R. McMahill: Micro-strip Analysis/Synthesis Calculator, Version 1.4A.
Intersymbol Interference.
86
Appendix A
" Schematics: Figures A-I - A-7.
" Board Layout: Figures A-8 - A-11.
87
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to (0
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89
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WT VkF GND
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ND ND NO NDGND =tI a*D
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26.1
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100
Appendix B
LMX2330L Dual Frequency Synthesizer
LMX2330L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
Communications (courtesy of National Semiconductor) is used as a local oscillator for
the single conversion subsampling receiver in this project. It belongs to the LMX233XL
family of monolithic, integrated dual frequency synthesizers with dual modulus
prescalers: 32/33 and 64/65 in the 2.5 GHz LMX2330L RF synthesizer. This family of
synthesizers is characterized by low current consumption with serial data being
transferred via a three-wire interface: Clock, Data, and Enable. The simplified block
diagram of LMX2330L is shown in Figure A. 1.
F Prescaler N COUNTER PHASE CHARGECOMP, PUMP
15-BIT IF FDRCOUNTER A LD
Lock
OSCin -- -ete---ck
RF MUX15-DT RFLD
PHASE CHARGE0,R
ilt RF PResaF C881 TRF COMP, PUMP O
C AT Ao DATA REGISTER ..A.....K
Figure B. 1: Symplified block diagram of LMX2330L.
101
Programming the LMX2330L
Programming words for this synthesizer are provided serially through Clock, Data, and
Enable pins. Data for the various counters is clocked in on the rising edge into the 22-bit
shift register. Serial data input entered MSB first. The last two bits are the control bits. If
Load Enable (LE) input goes HIGH, data residing in the shift registers is loaded into one
of the control bit dependent latches. Clock, Data and Enable pins must be provided with
high impedance CMOS inputs.
The synthesizer must provide 1.75GHz local oscillator input to the mixer in the front end
for 140MHz IF to be produced. The relationship between the frequency provided by the
crystal reference (fosc) in the synthesizer and the LO frequency (fvco) is given by the
pulse swallow function
fVC0 = [(P .B) + A] -fosc I R
fvco: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 1 1-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0 A 127 {RF}, A B)
fosc: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual modulus prescaler (for RF; LMX2330L: P=32 or 64)
30MHz crystal oscillator was used to produce the reference signal.
Functional Description
The three wire interface is connected to the 22-bit shift register. The data stream is
clocked into this register on the rising edge of the Clock signal, MSB first. On the rising
edge of LE the data stored in the shift register is loaded in one of the four latches
depending on the value of the Control Bits (Table T. 1).
102
Control Bits DATA Location
C2 Cl
0 0 IEF R Counter
0 1 IF N Counter
1 0 RF R Counter1 1 RF N Counter
Table T. 1: Counter selection via control bits.
R Counter
RF counters were the only ones relevant for this project. If the Control Bits ClC2 are 01
(RF R Counter), the data is transferred into the RF 15-bit R Counter. Serial data format
for R Counters is shown in Table T.2 and Table T.3.
R R R R R R IRTRrR R R R R R R R R RR R 2 C20119 18 71 15 14113112 111 10 9 8 7 6 5 4 3 2 1 qRProgj~r- - 15-bit Divide Ratio (R)
Table T.2: Reference divider (R) serial format.
Divide R R R R R R R R R R R R R R RRatio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Notes:
Divide ratios less than 3 are prohibited.Divide ratio: 3 to 32767R1 to RIS: These bits select the divide ratio ofData is shifted in MSB first.
the programmable reference divider.
Table T.3: 15-Bit Programmable Reference Divider Ratio (R counter).
103
MSB LSB
N Counter
If the Control Bits C IC2 are 11, the data is transferred from the 22-bit register into the N
Counter. Programmable reference dividers for RF N Counters have A counter (7-bit
swallow) and B counter (11-bit programmable). When the Control Bits are 11 (RF N
Counter), data is transferred to a 4- or 7-bit latch and 11-bit latch from the 22-bit shift
register, MSB first. The RF N counter is without so-called don't care bits. Serial data
format for N Counters is shown in Tables A.4, A.5 and A.6.
MSB B Counter Swallow Counter (A) LSB
N |N N N N N N N N N N N N N N N N N N |N C2C20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Prgm 18-bit Divide Ratio (N) CTRL
Table T.4: Divider (N) serial format.
RF
Divide N N N N N N N
Ratio 7 6 5 4 3 2 1
A
0 0 000 00 0
1 0 000 00 1
17 1 1 1 1 1 1 1
Notes: Divide ratio: 0 to 127B 2 A
Table T.5: 7-Bit Swallow Counter Divide Ratio (A counter).
Divide N N N N N N N N N N N
Ratio 18 17 16 15 14 13 12 11 10 9 8
B
3 0 2 0 00 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 1 0 0
2047 1 1 1 1 1 1 1 1 1 1 1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3B > A
are prohibited)
Table T.6: 11-Bit Programmable Counter Divide Ratio (B counter).
104
Programmable Modes
The truth table for the programmable modes is shown in Tables A.7 and A.8.
C1 C2 R16 R17 R18 R19 R200 0 IF Phase IF IcpO IF DO IF LD IF FO
Detector Polarity TRI-STATE
0 1 RF Phase RF 'Gpo RF DO RF LD RF FODetector Polarity TRI-STATE
1 C2 N19 N200 IF Prescaler Pwdn IF1 RF Prescaler Pwdn RF
Table T.7: Synthesizer Programmable Modes.
01t
Phase Detector Polarity(Note 1)
Negative
PositiveII
DO TRI-STATE
Normal Operation
TRI-STATE
,CPO(Note 2)
LOW
HIGHIII
IF
Prescaler8/9
16/17
2330L RF
Prescaler32/33
64/65
2331L/32L RF
Prescaler64/65
128/129
PowerDown
Pwrd UpPwrd Dn
Table T.8: Mode Select Truth Table.
Serial Data Input Timing
DATA N20:MSBIN9
CLOCK Jl J L
LE
Figure B.2: The timing diagram for Data, Clock and Enable input signals.
105
C
-
NIO N9 IC2 ClLSB
Programming Data Words
Using the information provided, it was determined that the following data words will be
used to program the synthesizer.
RF(R)=9:
RF(N)=525:
(0100100000000000100110)2
(0000000010000000110111)2.
I
106