section b: analogue electronics - school of electronic...

SOLUTIONS - SEMESTER TWO - 2008

MODULE: Digital Circuits and Systems (EE201)

COURSE: B.Eng. in Mechatronic Engineering

YEARS: 3 (three)

EXAMINERS: Mr. David Bermingham

Dr. R. MillarDr. F. DevittDr. F. Owens

TIME ALLOWED: 2 hours

INSTRUCTIONS: Answer FOUR questions. All questions carry equal marks

___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

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QUESTION 1

A) Describe, using a diagram, the structure and operation of a CMOS NOR gate

Answer:CMOS NOR Gates are built using 2 NMOS and 2 PMOS Circuits

A B F0 0 10 1 01 0 01 1 0

From the truth table of a NOR gate we can see that only when both inputs are logic zero will the output be high. From this we can derive that the PMOS transistors must be in series, as only when both are ON (A=0, B=0) will current pass through the PMOS transistors. When either input is high, a path to GND must be created, the NMOS FETs are therefore arranged in parallel.

3 Marks

5 MarksTOTAL : 8 Marks


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A B P0 P1 N0 N1 F0V 0V ON ON OFFOFF 10V VDD ON OFFOFFON 0VDD0V OFF ON ON OFF 0VDDVDD OFF OFFON ON 0

b) Describe the three components of CMOS power dissipation. Name 3 methods of reducing power consumption within CMOS circuits?

CMOS Power is derived from 3 components:A) Dynamic Power

Dynamic Power is due to the constant charging and discharging of the gate capacitance. The insulator between the Gate and MOSFET create a small dielectric capacitance at the gate. To switch the gate ON and OFF requires charge to be either added or removed from this capacitance. The dynamic power of a CMOS circuit is calculated using the equation

Where f is the operating frequency of the CMOS circuit, Vdd is the supply voltage of the circuit, Ag is the switching activity of the CMOS gate and CG

L is the average gate load capacitance

3 MarksB) Static Power

Static Power within CMOS circuit is due to leakage between both the gate to substrate (IGS) and the drain to source leakage (IDS). As MOSFET technology advances, the need for smaller MOSFET requires components such as a gate width or insulator width to be correspondingly reduced. Reductions in parameters such as gate width will in turn increase the leakage through the MOSFET

3 MarksC) Short Circuit Power

The final and smallest component of CMOS power is the short circuit dissipation seen during CMOS transition. Since NMOS and PMOS circuits will typically have differing switching times, there is a small period when switching state that both transistor may be on. For a small period of time, this situation creates a short circuit between VDD and GND.

Overall, the power consumption in a CMOS circuit is calculated using the equation

PTOTAL= PSTATIC + PSHORT + PDYNAMICWhere PSHORT is negligible, PSTATIC is determined by the technology utilized and PDYNAMIC can be estimated using a typically circuit load

3 MarksWithin a CMOS circuit, Power can be reduced by either

A) Reducing the Supply VoltageB) Reducing the frequency of the deviceC) Reducing the average switching load (how often the CMOS gate switches)


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D) Utilize a technology which reduces static power consumptiona. Better Insulatorb. Larger gate width

3 MarksTOTAL : 12

Marks

C) Which of the two circuits shown in table 1 has the lowest power consumption? You can assume all MOSFET are identical and switch the same amount of times.

Circuit A =>PTOTAL= PSTATIC + PSHORT + PDYNAMIC

Where PSHORT = 0PSTATIC = 1PYNAMIC = ½ * 100.106

* 3.3 * (0.5 * 2.10-12)= 0.165 mW

PTOTAL = 1.165 mW

Circuit B =>PTOTAL= PSTATIC + PSHORT + PDYNAMIC

Where PSHORT = 0PSTATIC = 1PYNAMIC = ½ * 500.106

* 1.8 * (0.5 * 2.10-12)= 0.45 mW

PTOTAL = 1.45 mWTOTAL:5 Marks


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Question 2A) Using a 2-1 Line multiplexer only, generate the following function:

Answer

Factorize using C

Factorize both sub functions using B

The sub functions of F00 are expanded out to full form

6 Marks

4 MarksTOTAL: 10 Marks

B) Design a 2-channel 2-bit Multiplexer using 2-to-1 line Multiplexers only.

Answer


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2 Marks2-Channel 2-Bit MUX requires single select line which is used to route either the I or J inputs to the output bits.The Boolean equations for this truth table are

O0 = I./S + J0.SO1 = I1./S + J1.S

2 MarksThese equations match the Boolean equation for a 2-1 MUX and a 2-channel 2-bit MUX can be implemented by placing 2 2-1 MUXs in parallel

3 MarksTotal: 7 Marks

C) How would this function be implemented within an FPGA Logic Slice?

AnswerAn FPGA would typically implement such a function using a Lookup

table. Xilinx Logic Slices (or Logic Blocks) comprise 2 4-input LUTs along with some carry & control logic, with Flip Flops at the output allowing the combinational result to be register or latched

In the case of function F, the LUT would be programmed with the pre-computed solutions for all possible input combinations

3 MarksExpanding F out to its full form:

when the input bits are 0000, 1011, 0011, 0101, 1111 OR 1110 the output is ONE, for all other input combinations the output is zero. The LUT would therefore be programmed

3 Marks


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Select OutputS O0 O10 I0 I11 J2 J1

The control logic of the MUX would be programmed to allow the LUT output to propagate to the output, with the final control MUX determining if a registered output is required


Question 3

A) Describe an algorithm for multiplying 2 floating point numbers stored using the IEEE 754 Single Precision Format.

Answer___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

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Address (A->D) LUT Result0000 10001 00010 00011 10100 00101 10110 00111 01000 01001 01010 01011 11100 01101 01110 11111 1

Using floating point system, numbers are represented in the form

For IEEE 754 single precision, 32-bits are utilized to store such numbers

Where S is the sign bit, E represent the biased exponent and the M bits store the floating point Mantissa

Any real number is converted to IEEE format by Converting the number to its binary equivalent Shifting the number either left of right until only the implied 1 is left of the decimal pointThe exponent is created by adding 127 to the number of shifts (exponent biasing)All digits right of the decimal point are stored in the mantissa while the sign bit is used

To multiply, a similar method to decimal floating point is used:Multiplication Algorithm:Lets assume that A*2a and B*2b will be multiplied

The multiplication result will have: Mantissa resulted from the multiplication of the two mantissas (C = A*B)

Exponent resulted from the addition of the two exponents (c = a+b)

Therefore, C = (A*B). 2(a+b)

B) Using this algorithm, show the steps required to multiply: 8 * 10.5Step 1: Convert 8 and 10.5 to binary

8 => 1000.0Normalising would require three shifts right => A = 1.0.23

10.5 => 1010.1Normalising would require three shifts right => A = 1.0101.23

3 MarksStep 2:

Result Mantissa C is createdC = (A*B) => C = (1.0 * 1.0101) => 1.0101

Step 3:Result Exponent c is createdc = (a+b) => c = 3 + 3 => 6

Result 1.0101.26

3 MarksCheck 1.0101.26 => 1010100 = 84Using IEEE, result would be stored as:

Decimal Binary


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Sign bit = 0 0Exponent = 6+ 127 =133 10000101 Mantissa bits = 01010000000000000…etc

2 MarksTOTAL:8 Marks

C) Outline 3 issues which should be considered when utilizing floating point numbers?

Any 3 of these design considerations Round off Error

Limited space in which to store recurring fractions Must chop or round at some point

Underflow Result is too small for FP representation Division of small numbers

Overflow Result is too large for FP representation Large multiplications can result in overflow

NUM Divide by Zero IEEE754 FP System should return +infinity when NUM>0 & -infinity

when NUM<0

Zero Divide by Zero IEEE754 FP System should return NaN

TOTAL: 5 Marks

Question 4

A) Design an 8-bit barrel shifter capable of performing arbitrary Arithmetic Shift Right (ASR), Logical Shift Right (LSR), Logical Shift Left (LSL) and rotate right (ROR)


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AnswerIn total we have 4 different shift methods, requiring 2 control signals for the output MUX. To be able to shift anywhere between 0 and 7-bits we require 3 shift amount bits.The barrel shifter is comprised of 4 parallel hardwired cascading shifters, where each shifter is built using the following circuit.

The bit shifting hardware is built using a re-wiring of the data input from each stage. As the data traverses the MUXs, we can select either the previous input or a shifted (or rotated) version of the stage input. I.E, to shift one time we would select the shifted input via MUX 1, while allowing this value to pass unmodified through the remaining 2 MUXs

TOTAL: 12 MarksB) How is the rotate function extended to allow rotate with carry

(RRX) to be carried out?

Normal rotate functions (without carry) will attempt to feed the shift out bits into the Most Significant bits of the result.


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However sometimes a previous result will generate a result larger than the CPUs native word size, i.e a carry was generated. By extending the rotate registers from 8-bits to 9-bits we can feed a carry in(X) into the result, while at the same time catching the LSB as the carry out (Y)

4 Marks

In this way the CPU can handle word sizes larger than it native bus width. Since the rotate function operates in 2 modes now, an additional shifter + MUX is required. Overall, a carry in, carry out and rotate select signal are needed.


C) How does placing the barrel shifter on one of the ALU input bus improve the performance of an ARM microprocessor? What is the major disadvantage with this placement?

TOTAL: 5 Marks


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By placing the barrel shifter on the B BUS, between the register file and ALU, the ARM microprocessor allows fast generation of shift + arithmetic results. This is particularly useful in functions such as bit masking or address generation. For example, say we wanted to compute the address:

Z = Y + (X<<4)Within an ARM CPU, this instruction would require only one clock cycle. The B bus is loaded with X, which is shifted in the barrel shifter before being added to Y in the ALU.

Another advantage would be within bit masking operations. For example, say we wanted to extract bit 4 of X and bit 7 of Y. With the barrel shifter in this position we can complete these operations without having to store the bit mask. Assuming one register (T) contains the number 1, the operations are:

Z1 = (X & (T<<3))Z2 = (Y & (Y<<7))

4 MarksThe major disadvantage of placing the barrel shifter in this position is that it is comprise of a large number of cascading MUXs. When compared to the ALU critical path it will typically be a longer delay, by placing them is series the delay is summed between the ALU and barrel shifter.

1 MarkTOTAL: 5 Marks

Question 5


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A) Briefly describe the dynamic RAM cell and its operation. How does it compare with a single static RAM cell in terms of area, speed, control circuitry and power?

Answer

DRAM utilises MOSFET capacitance to store data bit

Transistor per bit cost is approx 1

Si02 insulates gate and substrate

Creating dielectric capacitor between gate and substrate

Data bit is stored in this capacitance

3 Marks

To write the memory cell, the bit line is charged to logic 1 or 0 while the row and column select lines are asserted. This enables the access transistor, making it possible to charge up the storage capacitor with the desired logic voltage.

The read operation takes place by asserting the word line. The access transistor is turned on, sharing the voltage on the capacitor with the bit line. Sensitive amplifier circuits detect small changes on the bit line to determine whether a 1 or 0 was stored in the selected memory element.

The destructiveness of the read operation makes DRAMs complex. To read the contents of the storage capacitor, we must discharge it across the bit line. Thus, external circuitry in the DRAM must buffer the values that have been read out and then write them right back.

The second problem with DRAMs, and the most significant one is that their contents decay over time. Every once in a while (measured in milliseconds), the charge on the storage capacitors leaks off. To counteract this, the DRAM must be refreshed. Periodically, the memory elements must be read and written back to their storage locations.

3 Marks

Comparison to SRAM Advantages of DRAM

o Denser : Smaller Area requiredo Cheaper: Cost per bit is lesso Power: More power efficient than high speed SRAM

However SRAM can be designed to consume little power

Disadvantages of DRAM___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

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o Control Logic : Requires memory controller to ensure data is refreshed automatically unlike SRAM

o Interface: Much more complicated to interface than simple address/data bus structure of SRAM

o Speed: Difficult to scale DRAM to ultra high performance without long latencies, errors, etc. High speed memory like processor cache uses SRAM cells

o Power: Power consumption analysis must include additional control circuitry in calculations.

PD(SRAM) = Power dissipated by SRAM cells at freq f

PD(SRAM) = Power dissipated by DRAM cells at freq f + Power dissipated by DRAM controller


B) Design an 8-bit wide * 64 work DRAM using 1-bit * 64 word DRAM arrays? Indicate all control signals.

Each 1-bit * 64 word DRAM is comprise the following structure (diagram not needed). The 64 locations are divided into 8 rows and 8 columns, in order to address each row/column the column and row address decoders use a 3-bit input which is decoded into an 8-bit (single bit high) output code.

2 Marks


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To create an 8-bit * 64-word we chain 8 of these modules in parallel. The same 6-bit address is used (3-row and 3-column).

Signals missing from diagramOutput EnableWrite EnableClock


C) Describe how multiplexed addressing is used within DRAM memory? What additional signals are needed when using such a scheme?

Multiplexed Address Lines To further reduce cost, DRAM uses multiplexed address

4K x 1 = 12 Address lines 16M x 1 = 24 Address lines

Since column address is independent of row address We can provide row address and then column address

If 12-bit address bus is multiplexed we can address 16M DRAM with only 2 additional lines (RAS and CAS)

RAS : Row Address Strobe CAS : Column Address Strobe

Multiplexed Address, Step by Step:Step 1: Latch out 12 row address bitsStep 2: Strobe RAS line which causes DRAM to latch in row addressStep 3: Wait until you are sure it has been registered and latch out column address bitsStep 4: Strobe CAS line which causes DRAM to latch in column addressStep 5: Wait some period of time and read/write to data bus

3 Marks


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2 Marks

When compared to DRAM designed in part B, a multiplexed scheme would require 2 additional signals to assert when a row address and column address had been placed on the CPU address bus. These signals are typically called /RAS and /CAS, with the time between asserted a RAS and CAS referred to as the RAS-to-CAS delay.Along with these signals, a register to store the Row Address and a register to store the Column Address is required. These registers are enabled by the RAS and CAS signals. A timing register is also required to synchronize these operations.



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section b: analogue electronics - school of electronic...

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