section 7.2 - i2cnewmarch27

8/19/2019 Section 7.2 - I2CNewMarch27

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7.2: Inter-integrated Circuit7.2: Inter-integrated CircuitInterface (IInterface (I22C)C)

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Inter-Integrated Circuit (IInter-Integrated Circuit (I22C)C)

• Synchronous serial interface protocolSynchronous serial interface protocol

for transmitting and receiving data fromfor transmitting and receiving data from

external devices.external devices.

• II22C uses to lines:C uses to lines: SSerialerial ClCloc! Signaloc! Signal(SC") and(SC") and SSerialerial #a#ata (ta (S#$S#$))

• #ata flo in I#ata flo in I22C is %idirectional (halfC is %idirectional (half

duplex).duplex).

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&aster(s) and Slave(s)&aster(s) and Slave(s)

• &aster is responsi%le for:&aster is responsi%le for: – Initiali'ingInitiali'ingstoppingstopping data transfer data transfer – Control data transfer directionControl data transfer direction – enerating cloc! signalsenerating cloc! signals

• *ypically+ the microcontroller operates as a master*ypically+ the microcontroller operates as a masterand the peripheral component (e.g.+ memory) as aand the peripheral component (e.g.+ memory) as aslave.slave.

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,ardare Configuration,ardare Configuration

• S#$ and SC" lines have to possi%le states:S#$ and SC" lines have to possi%le states:float highfloat high andand driven low driven low ..

• oth the S#$ and SC" lines are pulled up to oth the S#$ and SC" lines are pulled up to #### %y pull-up resistors at Idle state%y pull-up resistors at Idle state

• /hen the sitch of the master or slave turns/hen the sitch of the master or slave turnson+ the signal is pulled don %ecause there ison+ the signal is pulled don %ecause there iscurrent floing from the Icurrent floing from the I22C %us to the sitch.C %us to the sitch.

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Start and Stop ConditionsStart and Stop Conditions

• II22C %us allos for more than one deviceC %us allos for more than one device

to ta!e over as master (although notto ta!e over as master (although not

simultaneously).simultaneously).

• /hen a microcontroller transfers data to/hen a microcontroller transfers data toa slave+ it needs to send a S*$0*a slave+ it needs to send a S*$0*

condition.condition.

• /hen transfer of data ends+ the/hen transfer of data ends+ themicrocontroller needs to relin1uish themicrocontroller needs to relin1uish the

control %y sending a S*3 condition.control %y sending a S*3 condition.

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#ata *ransfer %eteen &aster and Slave#ata *ransfer %eteen &aster and Slave

4.4. &aster sends out S*$0* condition&aster sends out S*$0* condition

2.2. &aster sends out 7-%it address of the&aster sends out 7-%it address of theslave to communicate ith. *he last %itslave to communicate ith. *he last %itdetermine hether the master reads ordetermine hether the master reads orrite to the slave.rite to the slave.

5.5. #ata %ytes are sent until a S*3 condition#ata %ytes are sent until a S*3 conditionis asserted %y the master.is asserted %y the master.

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Control yte


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3IC46 &SS3 &odule in I3IC46 &SS3 &odule in I22C &odeC &ode

• 0egisters supporting I0egisters supporting I22C operations:C operations:

– &SS3 Control 0egister 4 (SS3C4)&SS3 Control 0egister 4 (SS3C4)

– &SS3 Control 0egister 2 (SS3C2)&SS3 Control 0egister 2 (SS3C2)

– &SS3 Status 0egister (SS3S*$*)&SS3 Status 0egister (SS3S*$*)

– Serial 0eceive*ransmit uffer (SS389)Serial 0eceive*ransmit uffer (SS389)

– &SS3 Shift 0egister (SS3S0)not directly&SS3 Shift 0egister (SS3S0)not directly

accessi%leaccessi%le – &SS3 $ddress 0egister (SS3$##)&SS3 $ddress 0egister (SS3$##)

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aud 0ate enerator (0)aud 0ate enerator (0)

• *ime re1uired to shift out one %it of data ;*ime re1uired to shift out one %it of data ;

2*2*-0)-0)

• **-0)-0) ; time re1uired for the; time re1uired for the BRG counter BRG counter toto

count don to < from an initial valuecount don to < from an initial value• *he initial value is placed in the loer 7 %it*he initial value is placed in the loer 7 %it

of register SS3$## (i.e.+ SS3$##=?)of register SS3$## (i.e.+ SS3$##=?)

hich can %e set %y users.hich can %e set %y users.• *he 0 counter is decremented tice per*he 0 counter is decremented tice per

instruction cycle.instruction cycle.

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aud 0ateaud 0ate

**-0)-0) ; (@ *; (@ *SCSC 2) x (SS3$##=?A4) 2) x (SS3$##=?A4)

aud 0ate ; 4(2 *aud 0ate ; 4(2 *-0)-0)))

;;

99SCSC

B@ B@

((SS3$##=?SS3$##=?

A4)A4)

here *here *SCSC ; scillation period of cloc!; scillation period of cloc!

99SCSC ; 4*; 4*SCSC ; Cloc! fre1uency; Cloc! fre1uency

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aud 0ate Dxampleaud 0ate Dxample

• /hat is the initial value e need to load/hat is the initial value e need to load

to theto the SS3$## register if e ant to setSS3$## register if e ant to set

the %aud rate to %e 4cloc! has a fre1uency of @&,'.cloc! has a fre1uency of @&,'.• "et x ; initial value"et x ; initial value

• aud 0ate ;aud 0ate ; @&,' B@@&,' B@ ((xxA4) ; 4• x ;


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Start Condition *imingStart Condition *iming

• Start condition is initiated %y riting toStart condition is initiated %y riting toSD %it (SS3CS2=


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$ssert a Start Condition$ssert a Start Condition

• $ssert the start condition %y setting the$ssert the start condition %y setting the

SD %it in SS3C2:SD %it in SS3C2:

bsf bsf SSPCON2, SENSSPCON2, SEN

• /ait for the start condition to complete/ait for the start condition to complete

I2C_WaitFinish: bcf PIR1, SSPIFI2C_WaitFinish: bcf PIR1, SSPIF

I2C_WaitLoop:I2C_WaitLoop: btfss btfss PIR1, SSPIFPIR1, SSPIF bra I2C_WaitLoop bra I2C_WaitLoop

returnreturn

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Stop ConditionStop Condition

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SDA

SCL

Figure 11.3 Stop (P) condition


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Stop ConditionStop Condition

• $ssert the stop condition %y setting the$ssert the stop condition %y setting the

3D %it (SS3C2=2?):3D %it (SS3C2=2?):

bsf bsf SSPCON2, PENSSPCON2, PEN

• /ait for SS3I9 to get asserted+/ait for SS3I9 to get asserted+

indicating completion:indicating completion:

bra bra I2C_WaitFinishI2C_WaitFinish

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0epeated Start Condition *iming0epeated Start Condition *iming

• enerated hen theenerated hen themaster device antsmaster device ants

to transfer more datato transfer more data

after changing:after changing:

– data transferdata transfer

direction (i.e.+ rite todirection (i.e.+ rite to

read or vice versa)read or vice versa)

–Slave addressSlave address

• eed to send aeed to send a

S*$0* signal toS*$0* signal to

ma!e that change.ma!e that change.

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Stop Start


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0epeated Start Condition *iming0epeated Start Condition *iming

• SC" ; < %efore repeated start condition isSC" ; < %efore repeated start condition isactivated (since it happens after a readrite)activated (since it happens after a readrite)• $ctivated %y 0SD %it (SS3C2=4?)$ctivated %y 0SD %it (SS3C2=4?)• S %it (SS3S*$*=5?) is set during repeated startS %it (SS3S*$*=5?) is set during repeated start

• /hen completed+ 0SD %it is cleared and/hen completed+ 0SD %it is cleared andSS3I9 is set.SS3I9 is set.

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$ssert a 0epeated Start Condition$ssert a 0epeated Start Condition

• $ssert the repeated start condition %y set the 0SD %it$ssert the repeated start condition %y set the 0SD %itin SS3C2:in SS3C2:

bsf bsfSSPCON2, RSENSSPCON2, RSEN

• /ait for SS3I9 to get asserted:/ait for SS3I9 to get asserted:

bra braI2C_WaitFinishI2C_WaitFinish

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*ransmission*ransmission

• *ransmission of a data %yte or an*ransmission of a data %yte or anaddress is achieved %y riting to theaddress is achieved %y riting to theSS389 register. 9 flag (SS3S*$*=


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*ransmission*ransmission

• *o rite dataaddress to I*o rite dataaddress to I22C %us:C %us: – 9irst rite to /0D register 9irst rite to /0D register

– *hen move the value of /0D to SS389*hen move the value of /0D to SS389

o!"f o!"f SSP#$FSSP#$F

– 9inally+ rite for the SS3I9 signal to9inally+ rite for the SS3I9 signal to

get asserted:get asserted:

bra I2C_WaitFinish bra I2C_WaitFinish

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0eception0eception

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0eception0eception

• *o start reception:*o start reception:

bsf bsf SSPCON2, RCEN SSPCON2, RCEN

• /ait for SS3I9 to get asserted:/ait for SS3I9 to get asserted:

bra bra I2C_WaitFinish I2C_WaitFinish

• /rite SS389 into a register for further/rite SS389 into a register for further

processing:processing:

o!ff SSP#$F, I2C_#%&E o!ff SSP#$F, I2C_#%&E

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$c!noledge 0eception$c!noledge 0eception

• Clear the $CG#* %it (SS3C2=H?) toClear the $CG#* %it (SS3C2=H?) toac!noledge reception. Set $CG#* toac!noledge reception. Set $CG#* tosend a negative ac!noledgesend a negative ac!noledge

• Set $CGD to activate theSet $CGD to activate theac!noledgement processac!noledgement process

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$c!noledge 0eception$c!noledge 0eception

• SetClear $CG#*:SetClear $CG#*:

bsf 'bcf( bsf 'bcf( SSPCON2, )C*+&SSPCON2, )C*+&

• Set $CGD to activate ac!noledgement:Set $CGD to activate ac!noledgement:

bsf SSPCON2, )C*EN bsf SSPCON2, )C*EN

• /ait for SS3I9 to get asserted+ indicating/ait for SS3I9 to get asserted+ indicating

completion:completion:

bra I2C_WaitFinish bra I2C_WaitFinish

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II22C Interface ith $*2@C


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yte /riteyte /rite

4.4. *he master asserts the start condition*he master asserts the start condition2.2. *he master sends the*he master sends the control bytecontrol byte to $*2@C


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yte /riteyte /rite

0ecap hat e defined0ecap hat e defined /rite to DD30&/rite to DD30&

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$c!noledgement 3olling$c!noledgement 3olling

• nce the stop condition has %een issuednce the stop condition has %een issuedafter the rite operation+ the DD30&after the rite operation+ the DD30&enters the internal rite cycle.enters the internal rite cycle.

• *he duration of this cycle depends on the*he duration of this cycle depends on the

device.device.• Acknowledgement polling Acknowledgement polling involvesinvolves

sending a start condition folloed %y thesending a start condition folloed %y the

control %yte.control %yte.• If the internal rite cycle has not %eenIf the internal rite cycle has not %eencompleted+ the DD30& ould responsecompleted+ the DD30& ould responseith a $G otherise it ould responseith a $G otherise it ould response

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3age /rite3age /rite

• Instead of sending a S*3 conditionInstead of sending a S*3 conditionafter the transmission of the 4after the transmission of the 4stst %yte+%yte+

send 7 more %ytes.send 7 more %ytes.

• If more than 6 %ytes are ritten+ the dataIf more than 6 %ytes are ritten+ the dataord address ould Jroll overK.ord address ould Jroll overK.

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yte 0eadyte 0ead

4.4. 3erform Steps 4 to H of yte /rite to define the3erform Steps 4 to H of yte /rite to define thedevice address and ord address to read from.device address and ord address to read from.2.2. *he master asserts the*he master asserts the repeated startrepeated start conditioncondition5.5. *he master sends the*he master sends the control %ytecontrol %yte ith last %itith last %it

e1ual to 4 indicating a read operatione1ual to 4 indicating a read operation

@.@.

$*2@C. *he master receives the data %yte and asserts*he master receives the data %yte and asserts

$CG to the DD30&$CG to the DD30&7.7. *he master asserts the stop condition*he master asserts the stop condition

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yte 0eadyte 0ead

Conditions previously definedConditions previously defined yte 0ead from DD30&yte 0ead from DD30&

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Se1uential 0eadSe1uential 0ead

• Instead of sending a $CG after the first %yteInstead of sending a $CG after the first %yteis read+ the master sends out an $CG.is read+ the master sends out an $CG.

• *he operation terminates hen the master*he operation terminates hen the master

sends out a $CG %it and assert the stopsends out a $CG %it and assert the stopconditioncondition

• Se1uential read is not limited to 6 %ytes.Se1uential read is not limited to 6 %ytes.

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Lou should %e a%le to ... Lou should %e a%le to ...

• 8nderstand the characteristics of the I8nderstand the characteristics of the I22CCprotocolprotocol

• #escri%e different conditions that needs#escri%e different conditions that needs

to %e asserted during a Ito %e asserted during a I22C transfer.C transfer.• #esign the %aud rate of the data transfer#esign the %aud rate of the data transfer

%y setting the values in SS3$##.%y setting the values in SS3$##.

• #escri%e and implement different#escri%e and implement differentmethods of interfacing ith themethods of interfacing ith the

$*2@C

section 7.2 - i2cnewmarch27

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