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SECTION 2

HIGH SPEED OP AMPS

Driving Capacitive Loads

Cable Driving

Single-Supply Considerations

Application Circuits

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SECTION 2

HIGH SPEED OP AMPSWalt Jung and Walt Kester

Modern system design increasingly makes use of high speed ICs as circuit buildingblocks. With bandwidths going up and up, demands are placed on the designer forfaster and more power efficient circuits. The default high speed amplifier haschanged over the years, with high speed complementary bipolar (CB) process ICssuch as the AD846 and AD847 in use just about ten years at this writing. Duringthis time, the general utility/availability of these and other ICs have raised the “highspeed” common performance denominator to 50MHz. The most recent extendedfrequency complementary bipolar (XFCB) process high speed devices such as theAD8001/AD8002, the AD9631/9632 and the AD8036/AD8037 now extend theoperating range into the UHF region.

Of course, a traditional performance barrier has been speed, or perhaps moreaccurately, painless speed. While fast IC amplifiers have been around for some time,until more recently they simply haven’t been the easiest to use. As an example,devices with substantial speed increases over 741/301A era types, namely the 318-family, did so at the expense of relatively poor settling and capacitive loadingcharacteristics. Modern CB process parts like the AD84X series provide far greaterspeed, faster settling, and do so at low user cost. Still, the application of highperformance fast amplifiers is never entirely a cookbook process, so designers stillneed to be wary of many inter-related key issues. This includes not just the amplifierselection, but also control of parasitics and other potentially performance-limitingdetails in the surrounding circuit.

It is worth underscoring that reasons for the "speed revolution" lie not just inaffordability of the new high speed ICs, but is also rooted in their ease of use.Compared to earlier high speed ICs, CB process devices are generally more stablewith capacitive loads (with higher phase margins in general), have lower DC errors,consume less power for a given speed, and are all around more "user friendly".Taking this a step further, XFCB family devices, which extend the utility of the opamp to literally hundreds of MHz, are understandably less straightforward in termsof their application (as is any amplifier operating over such a range). Thus, gettingthe most from these modern devices definitely stresses the “total environment”aspects of design.

Another major ease of use feature found in today's linear ICs is a much wider rangeof supply voltage characterization. While the older ±15V standard is still much inuse, there is a trend towards including more performance data at popular lowervoltages, such as ±5V, or +5V only, single supply operation. The most recent devicesusing the lower voltage XFCB process use supply voltages of either ±5V, or simply+5V only. The trend towards lower supply voltages is unmistakable, with a goal ofsqueezing the highest performance from a given voltage/power circuit environment.These "ease of use" design aspects with current ICs are illustrated in this chapter,

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along with parasitic issues, optimizing performance over supply ranges, and lowdistortion stages in a variety of applications.

DRIVING CAPACITIVE LOADS

From system and signal fidelity points of view, transmission line coupling betweenstages is best, and is described in some detail in the next section. However, completetransmission line system design may not always be possible or practical. In addition,various other parasitic issues need careful consideration in high performancedesigns. One such problem parasitic is amplifier load capacitance, which potentiallycomes into play for all wide bandwidth situations which do not use transmission linesignal coupling.

A general design rule for wideband linear drivers is that capacitive loading (caploading) effects should always be considered. This is because PC board capacitancecan build up quickly, especially for wide and long signal runs over ground planesinsulated by thin, higher K dielectric. For example, a 0.025” PC trace using a G-10dielectric of 0.03” over a ground plane will run about 22pF/foot (Reference 1). Evenrelatively small load capacitance (i.e., <100 pF) can be troublesome, since while notcausing outright oscillation, it can still stretch amplifier settling time to greaterthan desirable levels for a given accuracy.

The effects of cap loading on high speed amplifier outputs are not simplydetrimental, they are actually an anathema to high quality signals. However, before-the-fact designer knowledge still allows high circuit performance, by employingvarious tricks of the trade to combat the capacitive loading. If it is not driven via atransmission line, remote signal circuitry should be checked for capacitive loadingvery carefully, and characterized as best possible. Drivers which face poorly definedload capacitance should be bullet-proofed accordingly with an appropriate designtechnique from the options list below.

Short of a true matched transmission line system, a number of ways exist to drive aload which is capacitive in nature while maintaining amplifier stability.

Custom capacitive load (cap load) compensation, includes two possible options,namely a); overcompensation, and b); an intentionally forced-high loop noise gainallowing crossover in a stable region. Both of these steps can be effective in specialsituations, as they reduce the amplifier’s effective closed loop bandwidth, so as torestore stability in the presence of cap loading.

Overcompensation of the amplifier, when possible, reduces amplifier bandwidth sothat the additional load capacitance no longer represents a danger to phase margin.As a practical matter however, amplifier compensation nodes to allow this areavailable on few high speed amplifiers. One such useful example is the AD829,compensated by a single capacitor at pin 5. In general, almost any amplifier usingexternal compensation can always be over compensated to reduce bandwidth. Thiswill restore stability against cap loads, by lowering the amplifier’s unity gainfrequency.

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CAPACITIVE LOADING ON OP AMP GENERALLY REDUCESPHASE MARGIN AND MAY CAUSE INSTABILITY,

BUT INCREASING THE NOISE GAIN OF THE CIRCUITIMPROVES STABILITY

Figure 2.1

Forcing a high noise gain, is shown in Figure 2.1, where the capacitively loadedamplifier with a noise gain of unity at the left is seen to be unstable, due to a 1/ß -open loop rolloff intersection on the Bode diagram in an unstable –12dB/octaveregion. For such a case, quite often stability can be restored by introducing a highernoise gain to the stage, so that the intersection then occurs in a stable –6dB/octaveregion, as depicted at the diagram right Bode plot.

RAISING NOISE GAIN (DC OR AC) FORFOLLOWER OR INVERTER STABILITY

Figure 2.2

To enable a higher noise gain (which does not necessarily need to be the same as thestage’s signal gain), use is made of resistive or RC pads at the amplifier input, as inFigure 2.2. This trick is more broad in scope than overcompensation, and has theadvantage of not requiring access to any internal amplifier nodes. This generallyallows use with any amplifier setup, even voltage followers. The technique adds anextra resistor RD, which works against RF to force the noise gain of the stage to alevel appreciably higher than the signal gain (which is unity in both cases here).Assuming that CL is a value which produces a parasitic pole near the amplifier’snatural crossover, this loading combination would likely lead to oscillation due to the

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excessive phase lag. However with RD connected, the higher amplifier noise gainproduces a new 1/ß - open loop rolloff intersection, about a decade lower infrequency. This is set low enough that the extra phase lag from CL is no longer aproblem, and amplifier stability is restored.

A drawback to this trick is that the DC offset and input noise of the amplifier areraised by the value of the noise gain, when the optional CD is not present. But, whenCD is used in series with RD, the offset voltage of the amplifier is not raised, and thegained-up AC noise components are confined to a frequency region above1/(2pi•RD•CD). A further caution is that the technique can be somewhat trickywhen separating these operating DC and AC regions, and should be appliedcarefully with regard to settling time (Reference 2). Note that these simplifiedexamples are generic, and in practice the absolute component values should bematched to a specific amplifier.

“Passive” cap load compensation, shown in Figure 2.3, is the most simple (and mostpopular) isolation technique available. It uses a simple “out-of-the-loop” series resistorRX to isolate the cap load, and can be used with any amplifier, current or voltagefeedback, FET or bipolar input.

OPEN-LOOP SERIES RESISTANCE ISOLATES CAPACITIVELOAD FOR AD811 CURRENT FEEDBACK OP AMP

(CIRCUIT BANDWIDTH = 13.5 MHz)

Figure 2.3

As noted, this technique can be applied to virtually any amplifier, which is a majorreason why it is so useful. It is shown here with a current feedback amplifiersuitable for high current line driving, the AD811, and it consists of just the simple(passive) series isolation resistor, RX. This resistor’s minimum value for stabilitywill vary from device to device, so the amplifier data sheet should be consulted forother ICs. Generally, information will be provided as to the amount of loadcapacitance tolerated, and a suggested minimum resistor value for stabilitypurposes.

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Drawbacks of this approach are the loss of bandwidth as RX works against CL, theloss of voltage swing, a possible lower slew rate limit due to IMAX and CL, and again error due to the RX-RL division. The gain error can be optionally compensatedwith RIN, which is ratioed to RF as RL is to RX. In this example, a ±100mA outputfrom the op amp into CL can slew VOUT at a rate of 100V/µs, far below the intrinsicAD811 slew rate of 2500V/µs. Although the drawbacks are serious, this form of capload compensation is nevertheless useful because of its simplicity. If the amplifier isnot otherwise protected, then an RX resistor of 50-100ohms should be used withvirtually any amplifier facing capacitive loading. Although a non-inverting amplifieris shown, the technique is equally applicable to inverter stages.

With very speed high amplifiers, or in applications where lowest settling time iscritical, even small values of load capacitance can be disruptive to frequencyresponse, but are nevertheless sometimes inescapable. One case in point is anamplifier used for driving ADC inputs. Since high speed ADC inputs quite often lookcapacitive in nature, this presents an oil/water type problem. In such cases theamplifier must be stable driving the capacitance, but it must also preserve its bestbandwidth and settling time characteristics. To address this type of cap load caseperformance, Rs and CL data for a specified settling time is most appropriate.

Some applications, in particular those that require driving the relatively highimpedance of an ADC, do not have a convenient back termination resistor to dampenthe effects of capacitive loading. At high frequencies, an amplifier’s outputimpedance is rising with frequency and acts like an inductance, which incombination with CL causes peaking or even worse, oscillation. When the bandwidthof an amplifier is an appreciable percentage of device ft,the situation is complicatedby the fact that the loading effects are reflected back into its internal stages. In spiteof this, the basic behavior of most very wide bandwidth amplifiers such as theAD8001 is very similar.

In general, a small damping resistor (Rs) placed in series with CL will help restorethe desired response (see Figure 2.4). The best choice for this resistor’s value willdepend upon the criterion used in determining the desired response. Traditionally,simply stability or an acceptable amount of peaking has been used, but a more strictmeasure such as 0.1% (or even 0.01%) settling will yield different values. For a givenamplifier, a family of Rs - CL curves exists, such as those of Figure 2.4. These datawill aid in selecting Rs for a given application.

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AD8001 RS REQIRED FOR VARIOUS CL VALUES

Figure 2.4

The basic shape of this curve can be easily explained. When CL is very small, noresistor is necessary. When CL increases to some threshold value an Rs becomesnecessary. Since the frequency at which the damping is required is related to theRs•CL time constant, the Rs needed will initially increase rapidly from zero, andthen will decrease as CL is increased further. A relatively strict requirement, suchas for 0.1%, settling will generally require a larger Rs for a given CL, giving a curvefalling higher (in terms of Rs) than that for a less stringent requirement, such as20% overshoot. For the common gain condition of +2, these two curves are plotted inthe figure for 0.1% settling (upper-most curve) and 20% overshoot (middle curve). Itis also worth mentioning that higher closed loop gains lessen the problemdramatically, and will require less Rs for the same performance. The third (lower-most) curve illustrates this, demonstrating a closed loop gain of 10 Rs requirementfor 20% overshoot for the AD8001 amplifier. This can be related to the earlierdiscussion associated with Figure 2.2.

The recommended values for Rs will optimize response, but it is important to notethat generally CL will degrade the maximum bandwidth and settling timeperformance which is achievable. In the limit, a large Rs•CL time constant willdominate the response. In any given application, the value for Rs should be taken asa starting point in an optimization process which accounts for board parasitics andother secondary effects.

Active or “in-the-loop” cap load compensation can also be used as shown in Figure2.5, and this scheme modifies the passive configuration to provide feedback correctionfor the DC & low frequency gain error associated with RX. In contrast to the passiveform, active compensation can only be used with voltage feedback amplifiers, becausecurrent feedback amplifiers don’t allow the integrating connection of CF.

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ACTIVE “IN-LOOP” CAPACITIVE LOAD COMPENSATIONCORRECTS FOR DC AND LF GAIN ERRORS

Figure 2.5

This circuit returns the DC feedback from the output side of isolation resistor RX,thus correcting for errors. AC feedback is returned via CF, which bypasses RX/RF athigh frequencies. With an appropriate value of CF (which varies with CL, for fixedresistances) this stage can be adjusted for a well damped transient response(Reference 2,3). There is still a bandwidth reduction, a headroom loss, and also(usually) a slew rate reduction, but the DC errors can be very low. A drawback is theneed to tune CF to CL, as even if this is done well initially, any change to CL willalter the response away from flat. The circuit as shown is useful for voltage feedbackamplifiers only, because capacitor CF provides integration around U1. It also can beimplemented in inverting fashion, by driving the bottom end of RIN.

Internal cap load compensation involves the use of an amplifier which internally hastopological provisions for the effects of external cap loading. To the user, this is themost transparent of the various techniques, as it works for any feedback situation, forany value of load capacitance. Drawbacks are that it produces higher distortion thandoes an otherwise similar amplifier without the network, and the compensationagainst cap loading is somewhat signal level dependent.

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AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNALCOMPENSATION FOR DRIVING CAPACITIVE LOADS

Figure 2.6

The internal cap load compensated amplifier sounds at first like the best of allpossible worlds, since the user need do nothing at all to set it up. Figure 2.6, asimplified diagram of an amplifier with internal cap load compensation, shows howit works. The cap load compensation is the CF -resistor network shown around theunity gain output stage of the amplifier - note that the dotted connection of thisnetwork underscores the fact that it only makes its presence felt for certain loadconditions.

Under normal (non-capacitive or light resistive) loading, there is limitedinput/output voltage error across the output stage, so the CF network then sees arelatively small voltage drop, and has little or no effect on the amplifier’s highimpedance compensation node. However when a capacitor (or other heavy) load ispresent, the high currents in the output stage produce a voltage difference across theCF network, which effectively adds capacitance to the compensation node. With thisrelatively heavy loading, a net larger compensation capacitance results, and reducesthe amplifier speed in a manner which is adaptive to the external capacitance, CL.As a point of reference, note that it requires 6.3mA peak to support a 2Vp-p swingacross a 100pF load at 10MHz.

Since this mechanism is resident in the amplifier output stage and it affects theoverall compensation characteristics dynamically, it acts independent of the specific

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feedback hookup, as well as size of the external cap loading. In other words, it can betransparent to the user in the sense that no specific design conditions need be set tomake it work (other than selecting an IC which employs it). Some amplifiers usinginternal cap load compensation are the AD847 and the AD817, and their dualequivalents, AD827 and AD826.

There are, however, some caveats also associated with this internal compensationscheme. As with the passive compensation techniques, bandwidth decreases as thedevice slows down to prevent oscillation with higher load currents. Also, thisadaptive compensation network has its greatest effect when enough output currentflows to produce significant voltage drop across the CF network. Conversely, atsmall signal levels, the effect of the network on speed is less, so greater ringing mayactually be possible for some circuits for lower-level outputs.

RESPONSE OF INTERNAL CAP LOADCOMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL

Figure 2.7

The dynamic nature of this internal cap load compensation is illustrated in Figure2.7, which shows an AD817 unity gain inverter being exercised at both high and lowoutput levels, with common conditions of Vs = ±15V, RL = 1kohm, CL = 1nF, andusing 1kohm input/feedback resistors. In both photos the input signal is on the toptrace and the output signal is on the bottom trace, and the time scale is fixed. In the10Vp-p output (A) photo at the left, the output has slowed down appreciably toaccommodate the capacitive load, but settling is still relatively clean, with a smallpercentage of overshoot. This indicates that for this high level case, the bandwidthreduction due to CL is most effective. However, in the (B) photo at the right, the200mVp-p output shows greater overshoot and ringing, for the lower level signal.The point is made that, to some degree at least, the relative cap load immunity ofthis type of internally cap load compensated amplifier is signal dependent.

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Finally, because the circuit is based on a nonlinear principle, the internal networkaffects distortion and load drive ability, and these factors influence amplifierperformance in video applications. Though the network’s presence does not by anymeans make devices like the AD847 or AD817 unusable for video, it does not permitthe very lowest levels of distortion and differential gain and phase which areachievable with otherwise comparable amplifiers (for example, the AD818).

While the individual techniques for countering cap loading outlined above havevarious specific tradeoffs as noted, all of the techniques have a serious commondrawback of reducing speed (both bandwidth and slew rate). If these parameterscannot be sacrificed, then a matched transmission line system is the solution, and isdiscussed in more detail later in the chapter. As for choosing among the cap loadcompensation schemes, it would seem on the surface that amplifiers using theinternal form offer the best possible solution to the problem- just pick the rightamplifier and forget about it. And indeed, that would seem the “panacea” solutionfor all cap load situations - if you use the “right” amplifier you never need to thinkabout cap loading again. Could there be more to it?

Yes! The “gotcha” of internal cap load compensation is subtle, and lies in the factthat the dynamic adaptive nature of the compensation mechanism actually canproduce higher levels of distortion, vis-à-vis an otherwise similar amplifier, withoutthe CF -resistor network. Like the old saying about no free lunches, if you care aboutattaining top-notch levels of high frequency AC performance, you should give theissue of whether to use an internally compensated cap load amplifier more seriousthought than simply picking a trendy device.

On the other hand, if you have no requirements for the lowest levels of distortion,then such an amplifier could be a good choice. Such amplifiers are certainly easier touse, and relatively forgiving about loading issues. Some applications of this chapterillustrate the distortion point specifically, quoting performance in a driver circuitwith/without the use of an internal cap load compensated amplifiers.

With increased gain bandwidths of greater than or equal to 100MHz available intoday’s ICs, layout, grounding and the control of parasitics become much, much moreimportant. In fact, with the fastest available ICs such as the XFCB types, theseissues simply cannot be ignored, they are critical and must be addressed for stableperformance. All high frequency designs can profit from the use of low parasiticconstruction techniques, such as described in Chapter 9. In the circuit discussionswhich follow, similar methods should be used for best results, and in the very highfrequency circuits (greater than 100MHz) it is mandatory. Some common pitfalls arecovered before getting into specific circuit examples.

As with all wide bandwidth components, good PC board layout is critical to obtainthe best dynamic performance with these high speed amplifiers. The ground plane inthe area of the op amp and its associated components should cover as much of thecomponent side of the board as possible (or first interior ground layer of a multilayerboard).

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The ground plane should be removed in the area of the amplifier inputs and thefeedback and gain set resistors to minimize stray capacitance at the input. Eachpower supply trace should be decoupled close to the package with a minimum of0.1µF ceramic (preferably surface mount), plus a 6.8µF or larger tantalum capacitorwithin 0.5", as a charge storage reservoir when delivering high peak currents (linedrivers, for example). Optionally, larger value conventional electrolytic can be usedin place of the tantalum types, if they have a low ESR.

All lead lengths for input, output, and feedback resistor should be kept as short aspossible. All gain setting resistors should be chosen for low values of parasiticcapacitance and inductance, i.e., microwave resistors (buffed metal film rather thanlaser-trimmed spiral-wound) and/or carbon resistors.

Microstrip techniques should be used for all input and output lead lengths in excessof one inch (Reference 1). Sockets should be avoided if at all possible because of theirparasitic capacitance and inductance. If sockets are necessary, individual pin socketssuch as AMP p/n 6-330808-3 should be used. These contribute far less straycapacitance and inductance than molded socket assemblies.

The effects of inadequate decoupling on harmonic distortion performance aredramatically illustrated in Figure 2.8. The left photo shows the spectral output ofthe AD9631 op amp driving a 100ohm load with proper decoupling (output signal is20MHz, 2V p-p). Notice that the second harmonic distortion at 40MHz isapproximately –70dBc. If the decoupling is removed, the distortion is increased, asshown in the right photo of the same figure. Figure 2.8 (right-hand photo) also showsstray RF pickup in the wiring connecting the power supply to the op amp testfixture. Unlike lower frequency amplifiers, the power supply rejection ratio of manyhigh frequency amplifiers is generally fairly poor at high frequencies. For example,at 20MHz, the power supply rejection ratio of the AD9631 is less than 25dB. This isthe primary reason for the degradation in performance with inadequate decoupling.The change in output signal produces a corresponding signal-dependent load currentchange. The corresponding change in power supply voltage due to inadequatedecoupling produces a signal-dependent error in the output which manifests itself asan increase in distortion.

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EFFECTS OF INADEQUATE DECOUPLING ONHARMONIC DISTORTION PERFORMANCE OF AD9631 OP AMP

Figure 2.8

Inadequate decoupling can also severely affect the pulse response of high speedamplifiers such as the AD9631. Figure 2.9 shows normal operation and the effects ofremoving all decoupling capacitors on the AD9631 in its evaluation board. Notice thesevere ringing on the pulse response for the poorly decoupled condition, in the rightphoto. A Tektronix 644A, 500MHz digitizing oscilloscope was used to make themeasurement (as well as the pulse responses in Figure 2.10, 2.14, 2.15, 2.16, and2.17).

EFFECT OF INADEQUATE DECOUPLINGON PULSE RESPONSE OF AD9631 OP AMP

Figure 2.9

The effects of stray parasitic capacitance on the inverting input of such high speedop amps as the AD8001 is shown in Figure 2.10. In this example, 10pF wasconnected to the inverting input, and the overshoot and ringing increasedsignificantly. (The AD8001 was configured in the inverting mode with a gain of –1,and the feedback and feedforward resistors were equal to 649ohms). In some cases,

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low-amplitude oscillation may occur at frequencies of several hundred megahertzwhen there is significant stray capacitance on the inverting input. Unfortunately,you may never actually observe it unless you have a scope or spectrum analyzerwhich has sufficient bandwidth. Unwanted oscillations at RF frequencies willprobably be rectified and averaged by devices to which the oscillating signal isapplied. This is referred to as RF rectification and will create small unexplained dcoffsets which may even be a function of moving your hand over the PC board. It isabsolutely essential when building circuits using high frequency components to havehigh bandwidth test equipment and use it to check for oscillation at frequencies wellbeyond the signals of interest.

EFFECT OF 10pF STRAY INVERTING INPUT CAPACITANCEON PULSE RESPONSE OF AD8001 OP AMP

Figure 2.10

Many of these problems occur in the prototype phase due to a disregard for highfrequency layout and decoupling techniques. The solutions to them lie in rigorousattention to such details as above, and those described in Chapter 9.

CABLE DRIVING

For a number of good reasons, wide bandwidth amplifier systems traditionally usetransmission line interconnections, such as that shown in the basic diagram ofFigure 2.11. This system uses a drive amplifier A, matched in terms of outputimpedance by the 75ohm source termination RT to the transmission line connectingstages A and B. In this particular case the line is a 75ohm coax, but in general it is awideband line matched at both ends, and can alternately be of twisted pair orstripline construction. It is followed immediately by the differential receiver circuit,B, which terminates the line with a load RTERM , equal to its 75ohm impedance.The receiver stage recovers a noise-free 1V signal which is referenced to systemground B.

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SINGLE-ENDED DRIVER AND DIFFERENTIAL RECEIVER

Figure 2.11

When properly implemented (i.e., the line is source and load terminated in itscharacteristic impedance), this system presents resistive-only loading to driveamplifier A. This factor makes it near ideal from the mutual viewpoints of amplifierstability, distortion and frequency response, as well as minimizing line reflectionsand associated time domain aberrations. There is an intrinsic 2/1 (6dB) signal lossassociated with the line’s source and load terminations, but this is easily made upby a 2x driver stage gain.

It is very important to understand that the capacitive-load compensation techniquesdescribed above are hardly the perfect solution to the line-driving problem. The mostfoolproof way to drive a long line (which could otherwise present a substantialcapacitive load) is to use a transmission line, a standard for signal distribution invideo and RF systems for years. Figure 2.12 summarizes several important cablecharacteristics.

CABLE CAPACITANCE

All Interconnections are Really Transmission Lines Which Have aCharacteristic Impedance (Even if Not controlled)

The Characteristic Impedance is Equal to (L/C), where L and C arethe Distributed Inductance and Capacitance

Correctly Terminated Transmission Lines Have Impedances Equal toTheir Characteristic Impedance

Unterminated Transmission Lines Behave Approximately asLumped Capacitance at Frequencies << 1/tp, where tp = PropagationDelay of Cable

Figure 2.12

A transmission line correctly terminated with pure resistance (no reactivecomponent) does not look capacitive. It has a controlled distributed capacitance perfoot (C) and a controlled distributed inductance per foot (L). The characteristicimpedance of the line is given by the equation Zo = sqrt(L/C). Coaxial cable is the

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most popular form of single-ended transmission line and comes in characteristicimpedances of 50ohms, 75ohms, and 93ohms.

Because of skin effect, it exhibits a loss which is a function of frequency as shown inFigure 2.13 for several popular coaxial cables (Reference 5). Skin effect also affectsthe pulse response of long coaxial cables. The response to a fast pulse will risesharply for the first 50% of the output swing, then taper off during the remainingportion of the edge. Calculations show that the 10 to 90% waveform risetime is 30times greater than the 0 to 50% risetime when the cable is skin effect limited(Reference 5).

COAXIAL CABLE ATTENUATION VERSUS FREQUENCY

Figure 2.13

It is useful to examine what happens for conditions of proper and improper cablesource/load terminations. To illustrate the behavior of a high speed op amp driving acoaxial cable, consider the circuit of Figure 2.14. The AD8001 drives 5 feet of 50ohmcoaxial cable which is load-end terminated in the characteristic impedance of50ohms. No termination is used at the amplifier (driving) end. The pulse response isalso shown in the figure.

The output of the cable was measured by connecting it directly to the 50ohm input ofa 500MHz Tektronix 644A digitizing oscilloscope. The 50ohm resistor termination isactually the input of the scope. The 50ohm load is not a perfect termination (thescope input capacitance is about 10pF), so some of the pulse is reflected out of phaseback to the source. When the reflection reaches the op amp output, it sees the closed-loop output impedance of the op amp which, at 100MHz, is approximately 100ohms.Thus, it is reflected back to the load with no phase reversal, accounting for thenegative-going "blip" which occurs approximately 16ns after the leading edge. This isequal to the round-trip delay of the cable (2•5ft•1.6 ns/ft=16ns). In the frequencydomain (not shown), the cable mismatch will cause a loss of bandwidth flatness atthe load.

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PULSE RESPONSE OF AD8001 DRIVING5 FEET OF LOAD-TERMINATED 50 COAXIAL CABLE

Figure 2.14

Figure 2.15 shows a second case, the results of driving the same coaxial cable, butnow used with both a 50ohm source-end as well as a 50ohm load-end termination.This case is the preferred way to drive a transmission line, because a portion of thereflection from the load impedance mismatch is absorbed by the amplifier’s sourcetermination resistor. The disadvantage is that there is a 2x gain reduction, becauseof the voltage division between the equal value source/load terminations. However, amajor positive attribute of this configuration, with matched source and loadterminations in conjunction with a low-loss cable, is that the best bandwidth flatnessis ensured, especially at lower operating frequencies. In addition, the amplifier isoperated under near optimum loading conditions, i.e., a resistive load.

PULSE RESPONSE OF AD8001 DRIVING 5 FEETOF SOURCE AND LOAD-TERMINATED 50 COAXIAL CABLE

Figure 2.15

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Source-end (only) terminations can also be used as shown in Figure 2.16, where theop amp is source terminated by the 50ohm resistor which drives the cable. The scopeis set for 1Mohm input impedance, representing an approximate open circuit. Theinitial leading edge of the pulse at the op amp output sees a 100ohm load (the 50ohmsource resistor in series with the 50ohm coax impedance. When the pulse reachesthe load, a large portion is reflected in phase because of the high load impedance,resulting in a full-amplitude pulse at the load. When the reflection reaches thesource-end of the cable, it sees the 50ohm source resistance in series with the opamp closed loop output impedance (approximately 100ohms at the frequencyrepresented by the 2ns risetime pulse edge). The reflected portion remains in phase,and appears at the scope input as the positive-going "blip" approximately 16ns afterthe leading edge.

PULSE RESPONSE OF AD8001 DRIVING 5 FEETOF SOURCE-TERMINATED 50 COAXIAL CABLE

Figure 2.16

From these experiments, one can easily see that the preferred method for minimumreflections (and therefore maximum bandwidth flatness) is to use both source andload terminations and try to minimize any reactance associated with the load. Theexperiments represent a worst-case condition, where the frequencies contained inthe fast edges are greater than 100MHz. (Using the rule-of-thumb that bandwidth =0.35/risetime). At video frequencies, either load-only, or source-only terminationsmay give acceptable results, but the data sheet should always be consulted todetermine the op amp's closed-loop output impedance at the maximum frequency ofinterest. A major disadvantage of the source-only termination is that it requires atruly high impedance load (high resistance and minimal parasitic capacitance) forminimum absorption of energy.

Now, for a truly worst case, let us replace the 5 feet of coaxial cable with anuncontrolled-impedance cable (one that is largely capacitive with little inductance).Let us use a capacitance of 150pF to simulate the cable (corresponding to the totalcapacitance of 5 feet of coaxial cable whose distributed capacitance is about30pF/foot). Figure 2.17 shows the output of the AD8001 driving a lumped 160pF

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capacitance (including the scope input capacitance of 10pF). Notice the overshootand ringing on the pulse waveform due to the capacitive loading. This exampleillustrates the need to use good quality controlled-impedance coaxial cable in thetransmission of high frequency signals.

PULSE RESPONSE OF AD8001 DRIVING 160Pf || 50 LOAD

Figure 2.17

Line Drivers

The single-ended line driver function complements the receiver at the transmissionend (below). This type driver is usually non-inverting, and accepts a signal from ahigh impedance board level source, scales it, and buffers it to drive a source matchedcoaxial transmission line of 50-100ohms. Typically, the driver has a gain of 2 times,which complements the 2/1 attenuation of system source/load terminations. A gain-of-two stage seems simple on the surface, but actually many factors become involvedin optimizing device and power supply selection to meet overall system performancecriteria. Among these are bandwidth/distortion levels versus load impedance, supplyvoltage/power consumption, and device type.

Fortunately, modern ICs have become more complete in their specifications, as wellas more flexible in terms of supply voltage, so there is much from which to choose.For high performance in such demanding applications as wideband video, designersneed a fully specified circuit environment, so that the best choice can be easy. ForNTSC video systems, distortion is usually rated in terms of differential gain anddifferential phase, expressed as change in percentage for gain and change in degreesfor phase, driving a rated load at the 3.58MHz subcarrier frequency. Whiletraditional 3dB bandwidth is important, a more stringent specification of 0.1dBbandwidth is also often used.

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VIDEO LINE DRIVER USING THE AD818 VOLTAGEFEEDBACK OP AMP HAS 50MHz BANDWIDTH (-0.1 dB)

Figure 2.18

An excellent single-ended, high performance line driver meeting these guidelines isshown in Figure 2.18. Although this circuit uses inexpensive amplifiers, an AD818(or 1/2 an AD828), it is still has excellent performance. Stage gain is set at 2 timesby the equal R1- R2 values, which are also relatively low (500-1kohms), to minimizethe feedback time constant. This voltage feedback op amp has maximum effectivebandwidth when operated at G=2, and has been optimized for this specificapplication, thus it is able to achieve a 50MHz 0.1dB bandwidth. For highestlinearity, it does not use internal capacitive load compensation. This factor, plus ahigh current (50mA) output stage provides the gain linearity required for highperformance video, and line driving applications.

The NTSC video differential gain/phase performance of this circuit is quite goodwith the 150ohm loading presented by the 75ohm source termination RT plus the75ohm load, RL, and is typically on the order of 0.01%/0.05° for a 2Vp-p VOUT videoswing while operating at ±15V. These figures do degrade for operation at Vs= ±5V,but can be maintained for supplies of ±10V or more. Thus to minimize distortion,supplies of ±10V to ±15V should be used. Other video grade op amps can also be usedfor U1, but illustrate the potential for distortion tradeoffs. For example, the AD817(a similar op amp with internal cap load compensation, see above) achieves NTSCvideo distortion figures of 0.04%/0.08° at Vs=±15V for the same 150ohm loading.

Supply bypassing for line drivers such as this should include both local lowinductance caps C1- C3, as well as larger value electrolytics, for a charge reservoir tobuffer heavy load currents. Tantalum types can be used for C2 - C4, and tend tohave both lower ESR and small physical size (both desirable), but the 100µFaluminum types shown can also be used. Quiescent current of this circuit is 7mA,which equates to power dissipations of 210 and 70mW for Vs=±15V and ±5V,respectively.

21

VIDEO LINE DRIVER USING THE AD810 CURRENT FEEDBACKOP AMP HAS DISABLE MODE, 65MHz BANDWIDTH (-3 dB)

AND 20MHz BANDWIDTH (-0.1 dB)

Figure 2.19

Figure 2.19 shows another high-performance video line driver using the AD810current feedback amplifier. This circuit is also inexpensive and has higher slew rateand higher output current. The AD810 has a 3dB bandwidth of 65MHz, and a 0.1dBbandwidth of 20MHz, while the quiescent current is only 8mA.

A unique feature of the AD810 is its power-down mode. The DISABLE pin is active-low to shut the device down to a standby current drain of 2mA, with 60dB inputisolation at 10MHz. This permits on/off control of a single amplifier, or "wire or-ing"the outputs of a number of devices to achieve a multiplexing function. Note: If theAD810’s disabling function is not required, then the DISABLE pin can float, and itoperates conventionally.

Note that when the AD810 is used on different power supplies, the optimum RF willchange (see table... this also will be true for other current feedback amplifiers).Other current feedback amplifiers suitable for this driver function are the singleAD811, the dual AD812, and the triple AD813 (with the AD813 also featuring aDISABLE function).

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VERY HIGH PERFORMANCE 5V VIDEO LINE DRIVER/DISTRIBUTION AMPLIFIER HAS 440MHz BANDWIDTH (-3Db)

AND 110MHz BANDWIDTH (-0.1Db)

Figure 2.20

Figure 2.20 illustrates a very high performance video line driver, which has optionaldistribution amplifier features. This circuit uses the AD8001 current feedbackamplifier as a gain-of-2 dual 75ohm line driver, generally similar to the above. Somekey performance differences which set this circuit apart lie in the fact that the opamp employs a complementary UHF process. It is capable of extremely widebandresponse, due to the NPN/PNP fts of 3-5GHz. This allows higher frequency responseat a lower power dissipation than the 500-600MHz ft complementary process parts,such as the AD818 or AD810 above. The extended frequency response and lowerpower helps achieve low distortion at higher frequencies, while operating at a muchlower quiescent power on supply voltages up to 12V.

Because the higher frequency response per mW of power, a higher output drive ispossible. Here, this leads to a performance difference in that this circuit also doublesas a distribution amplifier, that is it can drive two 75ohm output lines if desired.Operated from ±5V supplies as shown, the circuit has 3dB bandwidth of 440MHz.Video distortion for differential gain/phase is 0.01%/0.025° with one line driven (RL= 150ohms). Driving two lines (RL = 75ohms), the differential gain errors areessentially the same, while the differential phase errors rise to about 0.07°. The0.1dB bandwidth of this circuit is 110MHz, and the quiescent power is 50mW withthe ±5V supplies. Supply bypassing should follow the same guidelines as theprevious drivers, and the general physical layout should follow the RF constructiontechniques described above and in Chapter 9.

SINGLE-SUPPLY CONSIDERATIONS

The term single-supply has various implications, some of which are often furtherconfused by marketing hype, etc. As mentioned above, there is a distinct trendtoward systems which run on lower supply voltages. For high speed designs where2Vp-p swings are often the norm, ±5V power supplies have become standard. There

23

are many obvious reasons for lower power dissipation, such as the ability to runwithout fans, reliability issues, etc. There are, therefore, many applications forsingle-supply ADCs other than in systems which have only one supply voltage. Inmany instances, the lower power drain of a single-supply ADC can be the reason forits selection, rather than the fact that it requires just one supply.

Then, there are also systems which truly operate on a single power supply. In suchcases, it can often be difficult to maintain DC coupling from a source all the way tothe ADC. In fact, AC coupling is quite often used in single-supply systems, with aDC restoration circuit preceding the ADC. This is necessary to prevent the loss ofdynamic range which could otherwise occur, because of a need to provide maximumheadroom to an AC coupled signal of arbitrary duty cycle. In the AC-coupledportions of such systems, a “false ground” is often created, usually centered betweenthe rails.

This introduces the question of an optimum input voltage range for a single-supplyADC. At first it would seem that a zero-volt referenced input might be desirable. Butin fact, this places severe constraints on the ADC driving amplifier in DC coupledsystems, as it must maintain full linearity at or near 0V out. In actuality, there is nosuch thing as a true rail-rail output amplifier, since all output stage types will havefinite saturation voltage(s) to the +Vs rail or ground. Bipolar stages come the closest,and can go as low as an NPN VCESAT of ground (or, a complementary PNP can gowithin a VCESAT of the + rail). The exact saturation voltage is current dependent,and while it may be only a few mV at light currents, it can be several hundred mVfor higher load currents. The traditional CMOS rail-rail output stage looks like aresistor to ground for zero-volt outputs (or to the + rail, for + outputs), so substantialload currents create proportionally higher voltage drops across these resistors,thereby limiting the output swing.

A more optimum ADC input range is thus one which includes neither ground nor thepositive supply, and a range centered around Vs/2 is usually optimum. For example,an input range of 2Vp-p around +2.5V is bounded by +1.5V and +3.5V. Acomplementary common-emitter type single-supply output stage is quite capable ofhandling this range.

For design and process reasons however, the ADC input common-mode range maybe offset from the ideal Vs/2 voltage midpoint. Single-supply op amps dynamicspecifications such as distortion, settling time, slew rate, bandwidth, etc. aretypically stated for a Vs/2 output bias condition. Distortion and other dynamics candegrade if the signal is offset substantially in either direction from this nominalrange.

The output voltage range of an op amp is most often given for DC or low frequencyoutput signals. Distortion may increase as the signal approaches either high or lowsaturation voltage limits. For instance, a +5V op amp can have a distortionspecification of –60dBc for a 3Vp-p output signal. If not stated otherwise, theimplication is that the signal is centered around +2.5V (or Vs/2), i.e., the sinewave isbounded by +1V and +4V. If the signal is offset from +2.5, distortion may very wellincrease.

24

Low distortion op amp designs typically use a complementary emitter followeroutput stage. This limits their output swing to slightly greater than 1 diode drop ofthe rails, in general more like 1V of the rails. In order to maintain low distortion athigh frequencies, even more headroom may be required, reducing the availablepeak-to-peak swing.

The complementary common-emitter output stage allows the output to approachwithin VCESAT of the rails. However, it does have a higher open-loop outputimpedance than that of the follower type of stage, and is more likely to distort whendriving such non-linear loads as flash converters. When driving constant impedanceloads, distortion performance can be equal to or better that the follower type ofstage, but such a generalization obviously has its limitations.

The input voltage range of a single-supply op amp may also be restricted. The abilityto handle zero-volt input signals can be realized by either a PNP bipolar transistoror N-channel JFET differential input stage. Including both supply rails is rarelyrequired for high frequency signal processing. Of course, the positive rail can beincluded, if the op amp design uses NPN bipolars, or P-channel JFETs. For true rail-rail input capability, two amplifier input stages must operate in parallel, and thenecessary bias crossover point between these stages can result in distortion andreduced CMRR. This type of input stage serves DC and lower frequency amplifiersbest.

In many cases, an amplifier may be AC-specified for low voltage single-supplyoperation, but neither its input nor its output can actually swing very close to therails. Such devices must use applications designed so that both the input and outputcommon-mode restrictions are not violated. This generally involves offsetting theinputs using some sort of a false ground reference scheme.

To summarize, there are many tradeoffs involved in single-supply high speeddesigns. In many cases using devices specified for operation on +5V, but withouttrue rail inclusive input/output operation, can give best available performance. Asmore high speed devices which are truly single-supply become available, they can beadded to the designer’s bag of tricks.

Direct Coupling Requires Careful Design and ControlledLevels

A design which operates on a single +5V supply with DC coupling is illustrated inFigure 2.21. This type of circuit is useful when the input signal maximum amplitudeis known, and a specified output bias level is required to interface to the next stage(such as the ADC input range mentioned).

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CAREFUL BIASING AND CONTROLLED LEVELS ALLOWDC COUPLING WITHIN SINGLE-SUPPLY SYSTEMS

Figure 2.21

Here the source voltage is a ±2V 75ohm source, which is DC coupled and terminatedby RT. An AD812 amplifier is used, which has an input CM range of +1V to +4V(when operating on +5V), and a minimum output swing of 3Vp-p into 1kohm on 5V.It can easily swing the required 2Vp-p at the output, so there is some latitude forbiasing it around an output level of Vs/2. For unity signal gain, equal value feedbackand input resistors are used. The RF and RIN values chosen are a slight compromiseto maximum bandwidth (the optimum value is 715ohms), but the input line isterminated properly at 75ohms (the parallel equivalent value of RT and RIN).

The resulting resistor values provide a gain of about 1.95 to the DC voltage appliedto pin 3, VBIAS. A voltage of 1.235V from a stable reference source such the AD589will fix the static output DC level at 1.95•1.235V, or 2.41V. Because of the invertingmode signal operation, pin 2 of the op amp does not change appreciably with signal,therefore this node effectively operates at a fixed DC level, equal to VBIAS. As longas this bias voltage is well above the amplifier’s minimum CM range of +1V, thereshould be no problem. The RC network at pin 3 provides a noise filter for the diode.If a more precise output DC level is required from this stage, then VBIAS can beadjusted to provide it without change to the stage’s signal gain.

Single-Supply Line Drivers

By choosing a high frequency op amp which is specified for operation on low voltagesupplies, single-ended line drivers can also be adapted for single 5V supplyoperation. An example is the 5V supply line driver circuit of Figure 2.22, which alsoillustrates AC coupling in single-supply design.

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AC COUPLED SINGLE-SUPPLY LINE DRIVER

Figure 2.22

Speaking generally, this circuit can use a number of op amps, both voltage andcurrent feedback types. The output of the AD812 and AD813 devices can swing towithin about 1V of either rail, allowing 3Vp-p outputs to be delivered into 150ohmloads on 5V. While bandwidth of these current feedback amplifiers does reduces withlow voltage operation, they are still capable of a small signal 0.1dB bandwidth onthe order of 10MHz, and good differential gain/phase performance, about0.07%/0.06°, quite good for a simple circuit. The AD817 and AD818 are not as cleanin performance, and not necessarily recommended for 5V line drivers, but areincluded as examples of more general purpose voltage feedback types operable on5V. For optimizing the bias and bandwidth of any of these amplifiers, use theresistor values from the table.

As would be expected, headroom is critical on such low supplies, so if nothing else,biasing should be optimized for the voltage in use, via the R5 value as noted. R3 andR4 are equal values, AC bypassed for minimum noise coupling from the supply line.All input and output coupling capacitors are large in value, and are so chosen for aminimum of low frequency phase shift, for composite video uses. They can bereduced for applications with higher low frequency cutoffs. COUT is potentially aproblem in the large value shown, as large electrolytics can be inductive. C5, a non-critical optional low inductance shunt, can minimize this problem.

Obviously, the stage cannot be driven beyond 3Vp-p at VOUT without distortion, sooperating levels need to maintained conservatively below this. The next sectiondiscusses AC coupling issues and headroom in more detail.

The AC coupling of arbitrary waveforms can actually introduce problems which don’texist at all in DC coupled or DC restored systems. These problems have to do with

27

the waveform duty cycle, and are particularly acute with signals which approach therails, as they can in low supply voltage systems which are AC coupled.

In an amplifier circuit such as that of Figure 2.22, the output bias point will be equalto the DC bias as applied to the op amp’s (+) input. For a symmetric (50% duty cycle)waveform of a 2Vp-p output level , the output signal will swing symmetrically aboutthe bias point, or nominally 2.5V ±1V. If however the pulsed waveform is of a veryhigh (or low) duty cycle, the AC averaging effect of CIN and R4||R5 will shift theeffective peak level either high or low, dependent upon the duty cycle. Thisphenomenon has the net effect of reducing the working headroom of the amplifier,and is illustrated in Figure 2.23.

WAVEFORM DUTY CYCLE TAXESHEADROOM IN AC COUPLED AMPLIFIERS

Figure 2.23

In Figure 2.23 (A), an example of a 50% duty cycle square wave of about 2Vp-p levelis shown, with the signal swing biased symmetrically between the upper and lowerclip points of a 5V supply amplifier. This amplifier, for example, (an AD817 biasedsimilarly to Figure 2.22) can only swing to the limited DC levels as marked, about1V from either rail. In cases (B) and (C), the duty cycle of the input waveform isadjusted to both low and high duty cycle extremes while maintaining the same peak-to-peak input level. At the amplifier output, the waveform is seen to clip eithernegative or positive, in (B) and (C), respectively.

Since standard video waveforms do vary in duty cycle as the scene changes, thepoint is made that low distortion operation on AC coupled single supply stages musttake the duty cycle headroom degradation effect into account. If a stage has a 3Vp-poutput swing available before clipping, and it must cleanly reproduce an arbitrarywaveform, then the maximum allowable amplitude is less than 1/2 of this 3Vp-pswing, that is <1.5Vp-p. An example of violating this criteria is contained the 2Vp-pwaveform of Figure 2.23, which is clipping for both the high and low duty cycles.Note that the criteria set down above is based on avoiding hard clipping, whilesubtle distortion increases may in fact take place at lower levels. This suggests an

28

even more conservative criteria for lowest distortion operation such as compositeNTSC video amplifiers.

Of course, amplifiers designed with rail-rail outputs and low distortion in mindaddress these problems most directly. One such device is the AD8041, an XFCBsingle-supply op amp designed for video applications, and summarized briefly byFigure 2.24. As these data show, this part is designed to provide low NTSC videodistortion while driving a single 75ohm source terminated load (in a circuit such asFigure 2.22).

RAIL-RAIL OUTPUT VIDEO OP AMPS ALLOW LOWDISTORTION OUTPUT AND GREATEST FLEXIBILITY

Typical specifications for AD8041 op amp @ Vs = +5V, TA = 25 C

Common Mode Range: -0.2V to +4VOffset Voltage: 2mVBias Current: 1.2 ABandwidth: 80MHzSlew Rate: 160V/ sDifferential Gain/Phase: 0.03%/ 0.03(Vout = 2Vp-p, RL=150 )Output Current: 50mA (0.5V from rails)Quiescent Current: 5mADisable Feature Allows Multiplexing

Figure 2.24

APPLICATION CIRCUITS

A common video circuit requirement is the multiplexer, a stage which selects one of“N” video inputs, and transmits a buffered version of the selected signal to an outputtransmission line. Video amplifiers which can operate internally in a switched mode,such as the AD810 and AD813, allow this operation to be performed directly in thevideo signal path with no additional hardware. This feature is activated with the useof the device’s disable pin, which when pulled low, disables the amplifier and dropspower to a low state. The AD810 is a single channel current feedback amplifier withthis disable feature, while the AD813 offers similar functionality, in a 14 pin, threechannel format. The high performance of the AD813 on low voltages allows it toachieve high performance on ±5V supplies, and to be directly interfaced withstandard 5V logic drivers.

2:1 Video Multiplexer

The outputs of two AD810s can be wired together to form a 2:1 multiplexer withoutdegrading the flatness of the gain response. Figure 2.25 shows a recommendedconfiguration, which results in a 0.1dB bandwidth of 20MHz and OFF channelisolation of 77dB at 10MHz on ±5V supplies. The time to switch between channels isabout 750ns when the disable pins are driven by open drain output logic. With theuse of the recommended 74HC04 as shown, the switching time is about 180ns. Theswitching time is only slightly affected by the signal level.

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A 2:1 VIDEO MULTIPLEXER USING AD810s HAS -0.1dBBANDWIDTH OF 20MHz AND SWITCHES IN 180ns

Figure 2.25

3:1 Video Multiplexer

A 3:1 video multiplexer circuit using the triple AD813 is shown in Figure 2.26, andfeatures relative simplicity and high performance while operating from ±5V powersupplies. The 3 standard 1Vp-p video input signals VIN1 - VIN3 drive the 3 channelsof the AD813, one of which is ON at a given moment. If say channel 1 is selected,amplifier section 1 is enabled, by virtue of a logic HIGH signal on the SELECT1 linedriving the ENABLE input of the first amplifier. The remaining two amplifierchannels appear as open circuits looking back into them, but their feedbacknetworks do appear as a load to the active channel. Control logic decoding isprovided by U2, a 74HC238 1 of 8 logic decoder. The control lines A0 and A1 aredecoded as per the truth table, which provides selection between the 3 input signalsand OFF, as noted.

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3:1 VIDEO MULTIPLEXER USING AD813 TRIPLE OP AMP

Figure 2.26

Some design subtleties of the circuit come about because of necessity to account forseveral design criteria. One is the 590ohm value of feedback resistor R1, to provideoptimum response to the AD813 current feedback amplifier; another is the parasiticloading of the two unused gain resistor networks; a third is the source termination ofthe line, 75ohms in this case. While any given channel is ON, it drives not only loadresistor RL, but also the net dummy resistance RX/2, where RX is an equivalentseries resistance equal to R1 + R2 + R3. To provide a net overall gain of unity plusand effective 75ohm source impedance, this sets the resistance values of R1 + R2 +R3 as shown.

31

SWITCHING CHARACTERISTICS OF 3:1 VIDEO MULTIPLEXER

Figure 2.27

Performance of the circuit is excellent, with 0.1dB bandwidth of 20MHz, and an OFFstate isolation of 60dB at 10MHz. Switching time is about 180ns, and is shown inFigure 2.27 switching between two different inputs (top trace) with the control inputalso shown (bottom trace).

Video Programmable Gain Amplifier

Closely related to the 3:1 multiplexer of Figure 2.26 is a programmable gain videoamplifier, or PGA, as shown in Figure 2.28. With a similarly configured 2 line digitalcontrol input, this circuit can be set up to provide 3 different gain settings. Thismakes it a useful tool in various systems which can employ signal normalization orgain ranging prior to A/D conversion, such as CCD systems, ultrasound, etc. Thegains can be binary related as here, or they can be arbitrary. An extremely usefulfeature of the AD813 current feedback amplifier to this application is the fact thatthe bandwidth does not reduce in inverse proportion, as gain is increased. Instead, itstays relatively constant as gain is raised. Thus more useful bandwidth is availableat the higher programmed gains than would be true for a fixed gain-bandwidthproduct amplifier type.

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GAIN OF 1, 2, 4 PROGRAMMABLE GAIN VIDEO AMPLIFIER

Figure 2.28

In the circuit, channel 1 of the AD813 is a unity gain channel, channel 2 has a gainof 2, and channel 3 a gain of 4, while the fourth control state is OFF. As is indicatedby the table, these gains can varied by adjustment of the R2/R3 or R4/R5 ratios. Forthe gain range and values shown, the PGA will be able to maintain a 3dB bandwidthof about 50MHz or more for loading as shown (a high impedance load of 1kohm ormore is assumed). Fine tuning of the bandwidth for a given gain setting can beaccomplished by tweaking the absolute values of the feedback resistors (mostapplicable at higher gains).

Differential Drivers

Many applications require gain/phase matched complementary or differentialsignals. Among these are analog-digital-converter (ADC) input buffers, wheredifferential operation can provide lower levels of 2nd harmonic distortion for certainconverters. Other uses include high frequency bridge excitation, and drivers forbalanced transmission twisted pair lines such as UTP-5. While various topologiescan be employed to derive differential drive signals, many circuit details as well asthe topologies themselves are important as to how accurate two outputs can bemaintained.

Inverter-Follower Differential Driver

The circuit of Figure 2.29 is useful as a high speed differential driver for drivinghigh speed 10-12 bit ADCs, differential video lines, and other balanced loads atlevels of 1-4Vrms. As shown it operates from ±5V supplies, but it can also be adaptedto supplies in the range of ±5 to ±15V. When operated directly from ±5V as here, it

33

minimizes potential for destructive ADC overdrive when higher supply voltagebuffers drive a ±5V powered ADC, in addition to minimizing driver power.

DIFFERENTIAL DRIVER USING INVERTER/FOLLOWER

Figure 2.29

In many of these differential drivers the performance criteria is high. In addition tolow output distortion, the two signals should maintain gain/phase flatness. In thisdriver, two sections of an AD812 dual current feedback amplifier are used for thechannel A & B buffers, U1A & U1B. This measure can provide inherently betteropen-loop bandwidth matching than will the use of two individual same part numbersingles (where bandwidth varies between devices from different manufacturing lots).

The two buffers here operate with precise gains of ±1, as defined by their respectivefeedback and input resistances. Channel B buffer U1B is conventional, and uses amatched pair of 715ohm resistors- the value for using the AD812 on ±5V supplies.

In channel A, non-inverting buffer U1A has an inherent signal gain of 1, by virtue ofthe bootstrapped feedback network RFB1 and RG1(Reference 5). It also has a highernoise gain, for phase matching. Normally a current feedback amplifier operating asa simple unity gain follower would use one (optimum) resistor RFB1, and no gainresistor at all. Here, with input resistor RG1 added, a U1A noise gain like that ofU1B results. Due to the bootstrap connection of RFB1-RG1, the signal gain ismaintained at unity. Given the matched open loop bandwidths of U1A and U1B,similar noise gains in the A-B channels provide closely matched output bandwidthsbetween the driver sides, a distinction which greatly impacts overall matchingperformance.

In setting up a design for the driver, the effects of resistor gain errors should beconsidered for RG2-RFB2. Here a worst case 2% mis-match will result in less than0.2dB gain error between channels A and B. This error can be improved simply byspecifying tighter resistor ratio matching, avoiding trimming.

34

If desired, phase matching is trimmed via RG1, so that the phase of channel Aclosely matches that of B. This can be done for new circuit conditions, by using a pairof closely matched (0.1% or better) resistors to sum the A and B channels, as RG1 isadjusted for the best null conditions at the sum node. The A-B gain/phase matchingis quite effective in this driver, with test results of the circuit as shown 0.04dB and0.1° between the A and B output signals at 10MHz, when operated into dual 150ohmloads. The 3dB bandwidth of the driver is about 60MHz.

Net input impedance of the circuit is set to a standard line termination value suchas 75ohms (or 50ohms), by choosing RIN so that the desired value results with RINin parallel with RG2. In this example, an RIN value of 83.5ohms provides a standardinput impedance of 75ohms when paralleled with 715ohms. For the circuit just asshown, dual voltage feedback amplifier types with sufficiently high speed and lowdistortion can also be used. This allows greater freedom with regard to resistorvalues using such devices as the AD826 and AD828.

Gain of the circuit can be changed if desired, but this is not totally straightforward.An easy step to satisfy diverse gain requirements is to simply use a triple amplifiersuch as the AD813, with the third channel as a variable gain input buffer.

CROSS-COUPLED DIFFERENTIAL DRIVERPROVIDES BALANCED OUTPUTS AND 250MHz BANDWIDTH

Figure 2.30

Cross-Coupled Differential Driver

Another differential driver approach uses cross-coupled feedback to get very highCMR and complementary outputs at the same time. In Figure 2.30, by connectingAD8002 dual current feedback amplifier sections as cross-coupled inverters, theiroutputs are forced equal and opposite, assuring zero output common mode voltage.

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The gain cell which results, U1A and U1B plus cross-coupling resistances RX, isfundamentally a differential input and output topology, but it behaves as a voltagefeedback amplifier with regard to the feedback port at the U1A (+) node. The gain ofthe stage from VIN to VOUT is:

GVOUTVIN

2R1

R2= =

where VOUT is the differential output, equal to VOUTA – VOUTB.

This circuit has some unique benefits. First, differential gain is set by a singleresistor ratio, so there is no necessity for side-side resistor matching with gainchanges, as is the case for conventional differential amplifiers (see line receivers,below). Second, because the (overall) circuit emulates a voltage feedback amplifier,these gain resistances are not as restrictive as is true in the case of a conventionalcurrent feedback amplifier. Thus they are not highly critical as to absolute value.This is unlike standard applications using current feedback amplifiers, and will betrue as long as the equivalent resistance seen by U1A is reasonably low (less than1kohm in this case). Third, the cell bandwidth can be optimized to the desired gainby a single optional resistor, R3, as follows. If for instance, a net gain of 20 is desired(R1/R2=10), the bandwidth would otherwise be reduced by roughly this amount,since without R3 the cell operates with a constant gain-bandwidth product. With R3present however, advantage can be taken of the AD8002 current feedback amplifiercharacteristics. Additional internal gain is added by the connection of R3, which,given an appropriate value, effectively raises gain-bandwidth to a level so as torestore the bandwidth which would otherwise be lost by the higher closed loop gain.

In the circuit as shown, no R3 is necessary at the low working gain of 2 timesdifferential, since the 511ohm RX resistors are already optimized for maximumbandwidth. Note that these four matched resistances are somewhat critical, and willchange in absolute value with the use of another current feedback amplifier. Athigher gain closed loop gains as set by R1/R2, R3 can be chosen to optimize theworking transconductance in the input stages of U1A and U1B, as follows:

R3Rx

(R1 / R2) 1≅

−

As in any high speed inverting feedback amplifier, a small high-Q chip type feedbackcapacitance, C1, may be needed to optimize flatness of frequency response. In thisexample, a 0.9pF value was found optimum for minimizing peaking. In general,provision should be made on the PC layout for an NPO chip capacitor in the range of0.5-2pF. This capacitor is then value selected at board characterization for optimumfrequency response.

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FREQUENCY RESPONSE OF AD8002 CROSS-COUPLEDDRIVER IS > 250MHz (C1 = 0.9pF 0.1pF)

Figure 2.31

For the dual trace, 1-500MHz swept frequency response plot of Figure 2.31, outputlevels were 0dBm into matched 50ohm loads, through back termination resistancesRTA and RTB, at VOUTA and VOUTB. In this plot the vertical scale is 2dB/div, andit shows the 3dB bandwidth of the driver measuring about 250MHz, with peakingabout 0.1dB. The four RX resistors along with RTA and RTB control low frequencyamplitude matching, which was within 0.1dB in the lab tests, using 511ohm 1%resistor types. For tightest amplitude matching, these resistor ratios can be moreclosely controlled.

Due to the high gain-bandwidths involved with the AD8002, the construction of thiscircuit should follow RF rules, with the use of a ground plane, chip bypass capacitorsof zero lead length at the ±5V supply pins, and surface mount resistors for lowestinductance.

Differential Receivers

Another standard system application is the line receiver function, a stage whichaccepts signals from a single-ended (or differential) transmission line, and convertsthem into a buffered version for local processing (referring back to the systemdiagram of Figure 2.11). In a typical system, there is a single ended driving signalVIN at the origination point, a coaxial transmission line with the signal terminatedin the characteristic line impedance at the local end, and finally, a differential inputreceiver. The system operates the same in principle for standard impedances of 50-100ohms, as long as the source and load impedances match that of the line, underwhich conditions bandwidth is maximized. In the receiver, input impedance isassumed high in relation to line impedance, and high common-mode rejection (CMR)allows rejection of spurious noise appearing between driver/receiver grounds. Noiseis rejected in proportion to the CMR of the receiver amplifier, and typical CMRperformance goal for such a stage is 60-70dB or better for frequencies up to 10MHz.

37

Functionally, this system delivers at the output of the receiver stage a signal VOUT,a replica of the original driving signal VIN. The receiver may also scale the receivedsignal, and may also be called on to drive another transmission line. Criticalperformance parameters for the receiver are signal bandwidth and distortionspecifications. For line receivers, video distortion is rated in terms of differentialgain and differential phase at the 3.58 MHz subcarrier frequency.

4 Resistor Differential Line Receiver

Figure 2.32 shows a low cost, medium performance line receiver using a high speedop amp rated for video use. It is actually a standard 4 resistor instrumentationamplifier optimized for high speed, with a differential to single-ended gain of R2/R1.Using low value, DC accurate/AC trimmed resistances for R1-R4 and a high speed,high CMR op amp provides the good performance. Practically speaking however, atlow frequencies resistor matching can be more critical to overall CMR than the ratedCMR of the op amp. For example, the worst case CMR (in dB) of this circuit due toresistor effects is:

CMR

RR

Kr=

+

20 101 2

14

log

In this expression the term “Kr” is a single resistor tolerance in fractional form(1%=0.01, etc.), and it is assumed the amplifier has significantly higher CMR(greater than 100dB). Using discrete 1% metal films for R1/R2 and R3/R4 yields aworst case CMR of 34dB, 0.1% types 54dB, etc. Of course 4 random 1% resistors willon the average yield a CMR better than 34dB, but not dramatically so. A single sub-strate dual matched pair thin film network is preferred, for reasons of best noiserejection and simplicity. One type suitable is the Ohmtek 1005, (Reference 6) whichhas a ratio match of 0.1%, which will provide a worst case low frequency CMR of66dB.

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SIMPLE VIDEO LINE RECEIVER USING THE AD818 OP AMP

Figure 2.32

This circuit has an interesting and desirable side property. Because of the resistorsit divides down the input voltage, and the amplifier is protected against overvoltage.This allows CM voltages to exceed ±5V supply rails in some cases without hazard.Operation at ±15V should constrain the inputs within the rails.

At frequencies above 1MHz, the bridge balance is dominated by AC effects, and aC1-C2 capacitive balance trim should be used for best performance. The C1adjustment is intended to allow this, providing for the cancellation of stray layoutcapacitance(s) by electrically matching the net C1-C2 values. In a given PC layoutwith low and stable parasitic capacitance, C1 is best adjusted once in 0.5pFincrements, for best high frequency CMR. Using designated PC pads, productionvalues then would use the trimmed value. Good AC matching is essential toachieving good CMR at high frequencies. C1-C2 should be types similar physically,such as NPO (or other stable) ceramic chip style capacitors.

While the circuit as shown has unity gain, it can be gain-scaled in discrete steps, aslong as the noted resistor ratios are maintained. In practice, this means using tapson a multi-ratio network for gain change, so as to raise both R2 and R4, in identicalproportions. There is no other simple way to change gain in this receiver circuit.Alternately, a scheme for continuous gain control without interaction with CMR is tofollow this receiver with a scaling amplifier/driver with adjustable gain. The similarAD828 dual amplifier allows this with the addition of only two resistors.

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Video gain/phase performance of this stage is dependent upon the device is used forU1 and the operating supply voltages. Suitable voltage feedback amplifiers workbest at supplies of ±10 - ±15V, which maximizes op amp bandwidth. And, whilemany high speed amplifiers function in this circuit, those expressly designed withlow distortion video operation perform best. The circuit as shown can be used withsupplies of ±5 to ±15V, but lowest NTSC video distortion occurs for supplies of ±10Vor more, where differential gain/differential phase errors are less than 0.01%/0.05°.Operating at ±5V the distortion rises somewhat, but the lowest power drain of70mW occurs.

One drawback to this circuit is that it does load a 75ohm video line to some extent,and so should be used with this loading taken into account. On the plus side, it haswide dynamic range for both signal and CM voltages, plus the inherent overvoltageprotection.

Active Feedback Differential Line Receiver

Fully integrating the line receiver function eliminates the resistor-relateddrawbacks of the 4 resistor line receiver, improving CMR performance, ease of use,and overall circuit flexibility. An IC designed for this function is the AD830 activefeedback amplifier (Reference 7,8). Its use as a differential line receiver with gain isillustrated in Figure 2.33.

VIDEO LOOP-THROUGH CONNECTION USING THE AD830

Figure 2.33

The AD830 operates as a feedback amplifier with two sets of fully differentialinputs, available at pins 1-2 and 3-4, respectively. Internally, the outputs of the twostages are summed and drive a buffer output stage. Both input stages have highCMR, and can handle differential signals up to ±2V, and CM voltages can range upto –Vs+3V or +Vs–2.1V, with a ±1V differential input applied. While the AD830 doesnot normally need protection against CM voltages, if sustained transient voltagebeyond the rails is encountered, an optional pair of equal value (approximately200ohms) resistances can be used in series with pins 1-2.

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In this device the overall feedback loop operates so that the differential voltages V1-2 and V3-4 are forced to be equal. Feedback is taken from the output back to oneinput differential pair, while the other pair is driven by a differential input signal.An important point of this architecture is that high CM rejection is provided by thetwo differential input pairs, so CMR isn’t dependent on resistor bridges and theirassociated matching problems. The inherently wideband balanced circuit and thequasi-floating operation of the driven input provide the high CMR, which is typically100dB at DC.

The general expression for the U1 stage’s gain “G” is like a non-inverting op amp, or:

GVOUTVIN

R

R= = +1

2

1

For lowest DC offset, balancing resistor R3 is used (equal to R1|| R2).

In this example of a video “loop-through” connection, the input signal tapped from acoax line and applied to one input stage at pins 1-2, with the scaled output signaltied to the second input stage between pins 3-4. With the R1-R4 feedbackattenuation of 2/1, the net result is that the output of U1, is then equal to 2•VIN,i.e., a gain of 2.

Functionally, the input and local grounds are isolated by the CMR of the AD830,which is typically 75dB at frequencies below 1MHz, 60dB at 4.43MHz, and relativelysupply independent.

With the addition of an output source termination resistor RT, this circuit has anoverall loaded gain of unity at the load termination, RL. It is a ground isolatingvideo repeater, driving the terminated 75ohm output line, delivering a final outputequal to the original input, VIN.

NTSC video performance will be dependent upon supplies. Driving a terminated lineas shown, the circuit has optimum video distortion levels for Vs ±15V, wheredifferential gain is typically 0.06%, and differential phase 0.08°. Bandwidth can beoptimized by the optional 5.1pF (or 12pF) capacitor, CA, which allows a 0.1dBbandwidth of 10MHz with ±15V operation. The differential gain and phase errorsdeteriorate about 2 or more times at ±5V.

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REFERENCES:

1. Walt Kester, Maintaining Transmission Line Impedances on thePC Board, within Chapter 11 of System Applications Guide,Analog Devices, 1993.

2. Joe Buxton, Careful Design Tames High-Speed Op Amps,Electronic Design, April 11, 1991.

3. Walt Jung, Op Amps in Line-Driver and Receiver Circuits, Part 1, Analog Dialogue, Vol. 26-2, 1992.

4. William R. Blood, Jr., MECL System Design Handbook(HB205, Rev.1), Motorola Semiconductor Products, Inc., 1988.

5. Dave Whitney, Walt Jung, Applying a High-Performance VideoOperational Amplifier, Analog Dialogue, 26-1, 1992.

6. Ohmtek, Niagara Falls, NY, (716) 283-4025.

7. Walt Kester, Video Line Receiver Applications Using the AD830Active Feedback Amplifier Topology, within Chapter 11 of SystemApplications Guide, Analog Devices, 1993.

8. Walt Jung, Analog-Signal-Processing Concepts Get More Efficient,Electronic Design Analog Applications Issue, June 24, 1993.

9. Walt Jung, Scott Wurcer, Design Video Circuits Using High-SpeedOp-Amp Systems, Electronic Design Analog Applications Issue,November 7, 1994.

10. Thomas M. Frederiksen, Intuitive Operational Amplifiers,McGraw Hill, 1988.

11. D. Stout, M. Kaufman, Handbook of Operational AmplifierCircuit Design, New York, McGraw-Hill, 1976.

12. J. Dostal, Operational Amplifiers, Elsevier Scientific Publishing,New York, 1981.

13. 1992 Amplifier Applications Guide, 1992, Analog Devices.

14. Walter G. Jung, IC Op Amp Cookbook, Third Edition,SAMS (Division of Macmillan, Inc.), 1986.

15. W. A. Kester, PCM Signal Codecs for Video Applications,SMPTE Journal, No. 88, November 1979, pp. 770-778.

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16. IEEE Standard for Performance Measurements of A/D and D/AConverters for PCM Television Circuits, IEEE Standard 746-1984.

17. Tim Henry, Analysis and Design of the Op Amp Current Source,Application Note AN-587, Motorola, Inc., 1973.