s.e. sem. iii [cmpn] digital logic design and analysis...

1113/Engg/SE/Pre Pap/2013/CMPN/DLDA_Soln 1

Vidyalankar S.E. Sem. III [CMPN]

Digital Logic Design and AnalysisPrelim Question Paper Solution

(i) (0 B C 5)H (A 2 B D)H

(0 B C 5)H (A 2 B D)H = (FFFF 6908)H

(ii) (12.3)4 + (212.3)4 2 1 2 . 3 1 2 . 3 2 3 1 . 2

(12.3)4 + (212.3)4 = (231.2)4

(iii) (77)8 (17)8

Octal Table X 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 2 2 4 6 10 12 14 16 3 3 6 11 14 17 22 25 4 4 10 14 20 24 30 34 5 5 12 17 24 31 36 43 6 6 14 22 30 36 44 52 7 7 16 25 34 43 52 61

77 17 671 + 770 1661 octal addition (7 + 7 = 16)

Note : Add octal addition = octal multiplication table.

Octal Addition Octal Multiplicaiton

+ 0 1 2 3 4 5 6 7 10 0 1 2 3 4 5 6 7 10 0 0 1 2 3 4 5 6 7 10 0 0 0 0 0 0 0 0 0 0 1 1 2 3 4 5 6 7 10 11 1 0 1 2 3 4 5 6 7 10 2 2 3 4 5 6 7 10 11 12 2 0 2 4 6 10 12 14 16 20 3 3 4 5 6 7 10 11 12 13 3 0 3 6 11 14 17 22 25 30 4 4 5 6 7 10 11 12 13 14 4 0 4 10 14 20 24 30 34 40 5 5 6 7 10 11 12 13 14 15 5 0 5 12 17 24 31 36 43 50 6 6 7 10 11 12 13 14 15 16 6 0 6 14 22 30 36 44 52 60 7 7 10 11 12 13 14 15 16 17 7 0 7 16 25 34 43 52 61 70

10 10 11 12 13 14 15 16 17 20 10 0 10 20 30 40 50 60 70 100

1. (a)

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Vidyalankar : S.E. – DLDA


(iv) (1110)2 (110)2

Quotient = (101)2 Reminder = (000)2

(i) A AB ABC ABCD

A + B + AB(C CD) ( A + AB = A + B)

A + B + AB(C D) ( A (B + C) = AB + AC)

A + B + ABC ABDA + ABC B BAD

A + BC B AD A + AD B BC A + D + B + C A + B + C + D

(ii) A [B C(AB AC)]

= A [B + C (AB.AC)] (De-Morgan 2 law = A B AB )

= A [B + C (A B) . (A C)] (De-Morgan 1 law = A B A B )

= A [B + C (A.A A.B A.C B.C)]

= A [B + C (0 A.B A.C B.C)] (A.A 0)

= A [B + C.0 + A.BC A.CC B.CC] (A.0 = 0)

= A [B + 0 + A.BC 0 0]

= AB + A.A.B.C = AB + 0 = AB

1. (b)

110 11110 101 110

110 110

000

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Prelim Question Paper Solution


In all five 1 : 4 Demux ICs are used. S0S1S2S3 are the four select lines. Din is the data input and Y0 …Y15 are the

16 outputs of the 1:16 demux. The truth table of 1:16 Demux is shown in below table.

Select inputs Output S3 S2 S1 S0

0 0 0 0 Y0 = Din S3 S2 = 00 Demux 2 is selected : : :

: : : 0 0 1 1 Y3 = Din


: : : 0 1 1 1 Y7 = Din


: : : 1 0 1 1 Y11 = Din


: : : 1 1 1 1 Y15 = Din

1. (c)1 : 4

Demux 2

1 : 4 Demux 3

1 : 4 Demux 4

1 : 4 Demux 5

Y0

Y3

O/Ps

Y4

Y7

O/Ps

Y8

Y11

O/Ps

Y12

Y15

O/Ps

S1

S0

Din

Din

1 : 4 Demux 1 Din

Din

S3

S2

Data inputDin

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• The "Race Around Condition" that we are going to explain occurs whenJ = K = 1 i.e. when the latch is in the toggle mode.

• Refer figure 1 which shows the waveforms for the various modes, when arectangular waveform is applied to the "Enable" input

Waveforms for various modes of a JK latch.

Interval t0-t1 • During this interval J = 1, K = 0 and E = 0.• Hence the latch is disabled and there is no change in Q.

Interval t1-t2 • During this interval J = 1, K = 0 and E = l.• Hence this is a set condition and Q becomes 1.

Interval t2-t3 : Race Around • At instant t2, J = K = 1 and E = 1 Hence the JK latch is in the toggle mode

and Q becomes low (0) and Q = l. • These changed outputs get applied at the inputs of NAND gates 3 and 4 of

the JK latch. Thus the new inputs to Gates 3 and 4 are : NAND-3 : J = 1, E = l, Q = 1 NAND-4 : K = 1, E = 1, Q = 0.

• Hence R' will become 0 and S' will become 1.• Therefore after a time period corresponding to the propagation delay, the Q

and Q outputs will change to, Q = 1 and Q = 0.• These changed output again get applied to the inputs of NAND-3 and 4 and the

outputs will toggle again.• Thus as long as J = K = 1 and E = 1, the outputs will keep toggling indefinitely as

shown in figure 1. This multiple, toggling in the J-K latch is called as RaceAround condition. It must be avoided.

Interval t3-t4 • During this interval J = 0, K = 1 and E = 1. Hence it is the reset condition.• So Q becomes zero.

1. (d)

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Given F(A, B, C, D) = m (0, 2, 3, 6, 7, 8, 9, 12, 13) = m (1, 4, 5, 10, 11, 14, 15)

Step 1: Arranging minterms in groups of 1’s

Group (No. of 1’s) Minterm A B C D

1 1 4

0 0

0 1

0 0

1 0

2 5 10

0 1

1 0

0 1

1 0

3 11 14

1 1

0 1

1 1

1 0

4 15 1 1 1 1

Step 2: Arranging minterms to form pairs

Group Minterm pairs

A B C D Prime Implicants

1 1 5 4 5

0 0

1

0 0

1

ACD

ABC 2 10 11

10 14 1 1

0

1 1

0

3 11 15 14 15

1 1

1

1 1

1

Step 3: Arranging minterms to form Quads

Groups Quad pairs A B C D Prime implicants 10 11 14 15 10 14 11 15

1 1

1 1

AC

Table of prime implicants

Prime Implicants

Minterm Given minterm

1 4 5 10 11 14 15

ACD 1, 5 ☑

ABC 4, 5 ☑

AC 10, 11, 14, 15 ☑

0 can’t ignore F(A,B,C,D) = ACD ABC AC

= ACD ABC AC

= (ACD)(ABC)(AC)

F(A,B,C,D) = (ACD)(ABC)(AC)

2. (a)

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Implementation using NAND gates

Full Adder using Half Adder

Fig.1 • The full adder circuit can be constructed using two half adders as shown in

fig.1 and the detail circuit is shown in fig.2. • A full adder can be implemented using two half adders and the OR gate as

shown in fig.2.

Fig.2

• Now let us prove that this circuit acts as a full adder.

Truth table

2. (b)

A B C D

ACD

ABC

AC

(ACD)(ABC)(AC) =

F = ACD ABC AC

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Fig. 1 : NOT function using NAND gates

Proof : • Refer Fig. 2 and write the expression for sum output as, S = (A B) Cin = A B Cin

This expression is same as that obtained for the full adder. • Now write the expression for carry output C0 as

C0 = (A B) Cin + AB C0 = in(AB AB)C AB

= in inABC ABC AB

= in in inABC ABC AB(1 C ) = in in inABC ABC AB ABC

= in inBC (A A) ABC AB = in inBC ABC AB

= in in inBC ABC AB(1 C )

= in in inBC ABC AB ABC

= in inBC AB AC (B B)

C0 = in inBC AB AC • This expression is same that for a full adder. Thus we have proved that

circuit shown in fig.2 really behaves like a full adder.

Applications of Full Adder • The full adder acts as the basic building block of the 4 bit/8 bit binary/BCD

adder ICs such as 7483.

The NAND and NOR gates are called as “Universal Gates” Because it ispossible to implement any Boolean expression with the help of only NANDor only NOR gates.

Hence a user can build any combinational circuit with the help of only NANDgates or only NOR gates.

This is a great advantage because a user will have to make a stock of onlyNAND or NOR gate ICs.

Universal Property NAND Gate The NAND gate can be used to generate the NOT function, the AND function, the OR function, and the NOR function.

NOT Function: An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig. 1, for a twoinput gate:

3. (a)

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AND Function : An AND function can be generated using only NAND gates. It is generated by

simply inverting output of NAND gate; i.e. AB = AB. Fig. 2 shows the two input AND gate using NAND gates.

A B AB A B AB AB 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1

Table : Truth Table

OR Function OR function is generated using only NAND gates as follows : We know that Boolean expression for OR gate is

Y = A + B

= A B Rule 9 : [A A]

= A.B DeMorgan’s Theorem 1

The above equation is implemented using only NAND gates as shown in the Fig. 3.

Fig. 3 : OR function using only NAND gates

Note : Bubble at the input of NAND gate indicates inverted input.

A B A+B A B A .B A .B 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1

Table : Truth table

Fig. 2 : AND function using NAND gates

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NOR Function NOR function is generated using only NAND gates as follows : We know that Boolean expression for NOR gate is

Y = A B= A.B

= A.B DeMorgan’s Theorem 2

Rule 9 : [ A A ] The above equation is implemented using only NAND gates, as shown in the fig. 4.

A B A B A B A .B A .B A .B 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 0

Table : Truth Table

NOR Gate Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to generate the NOT, AND, OR and NAND functions.

NOT Function An inverter can be made from a NOR gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig. 5.

Fig. 5 : NOT function using NOR gate

Fig. 4 : NOR function using only NAND gates

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OR Function An OR function can be generated using only NOR gates. It can be generated by

simply inverting output of NOR gate; i.e. A B = A + B. Fig. 6 shows the two input OR gate using NOR gates.

A B A+B A B A B A B 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1

Table : Truth table AND Function AND function is generated using only NOR gates as follows : We know that Boolean expression for AND gate is

Y = A. B

= A .B Rule 9 : [ A A ]

= A B DeMorgan’s Theorem 2

The above equation is implemented using only NOR gates as shown in the Fig. 7.

Fig. 7 : AND function using NOR gates

A B A+B A B A B A B 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1

Table : Truth table

Fig. 6 : OR function using NOR gates

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NAND Function NAND function is generated using only NOR gates as follows : We know that Boolean expression for NAND gate is

Y = A .B = A B DeMorgan’s Theorem 1

= A B Rule 9 : [ A A ] The above equation is implemented using only NOR gates, as shown in the Fig. 8.

Fig. 8 : NAND function using only NOR gates

A B A+B A B A B A B A B 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0

Table : Truth table

Flip-flops required : 2n N N = 6 n = 3 i.e., three flip-flops required.

Fig.1 : MOD-6 synchronous p counter

• FF-A acts as a toggle FF since JA = KA = 1.

• QA output of FF-A is applied to JB as well as KB. Hence if QA = 1 at the instant of triggering, then FF-B will toggle but if QA = 0 then FF-B will not change its state.

• QA and QB are ANDed and the output of AND gate is applied to JC and KC. • Hence when QA and QB both are simultaneously high, then JC = KC = 1 and

FF-C will toggle. Otherwise there is no change in the state of FF-3.

3. (b)

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So in general we can say that each FF should have its J and K inputs connected such that they are high only when the outputs of all lower order FFs are in the high state.

Operation Initially all the FFs are in their rest state. QC QB QA = 0 0 0

1st clock pulse • FF-A toggles and QA changes to 1 from 0. But since QA = 0 at the instant o

application of 1st falling clock edge, JB = KB = 0 and QB does not change state. QB remains 0.

• Similarly QC also does not change state. QC = 0 QC QB QA = 0 0 1 … after 1st clock pulse

2nd clock pulse • FF-A toggles and QA becomes 0.

• But at the instant of application of 2nd falling clock edge QA was equal to 1. Hence JB = KB = 1. Hence FF-B will toggle and QB becomes 1.

• Output of AND gate is 0 at the instant of negative clock edge. So JC = KC = 0. Hence QC remains 0.

QC QB QA = 0 1 0 … after the 2nd clock pulse

3rd clock pulse

• After the 3rd clock pulse, the outputs are QC QB QA = 0 1 1.

4th clock pulse

• Note that QB = QA = 1. Hence output of AND gate = 1 and JC = KC = 1, at the instant of application of 4th negative edge of the clock.

• Hence on application of this clock pulse, FF-C will toggle and QC changes from 0 to 1.

• FF-A toggles as usual and QA becomes 0. • Since QA was equal to 1 earlier, FF-B will also toggle to make QB = 0. QC QB QA = 1 0 0 … after the 4th clock pulse

• Thus the counting progresses. • After the 7th clock pulse the output is 111 and after the 8th clock pulse, all the

flip-flops toggle and change their outputs to 0. Hence QC QB QA = 0 0 0 after the 8th pulse and the operation repeats.

Clock QC QB QA 0 0 0 0

1st () 0 0 1 2nd () 0 1 0 3rd () 0 1 1 4th () 1 0 0 5th () 1 0 1 6th () 1 1 0 7th () 1 1 1

Fig. 2

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Below figure shows the implementation of given Boolean function with 8 : 1 multiplexer.

(i) Design a D flip Flop from a RS Flop (ii) JK to T J and K are the actual inputs of the flip flop and T is taken as the external

input for conversion. Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The conversion table, K-maps, and the logic diagram are given below.

4. (b)

4. (a)

D0 D1 D2 D3 D4 D5 D6 D7

A 0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14 15 A 1 A 0 0 A 0 1

A 1 0

D0 D1 D2 D3 D4 D5 D6 D7

8 : 1 MUX y

Inputs Outputs

D Present state Qn

Next state Qn+1 S R

0 0 0 0 X 1 0 1 1 0 0 1 0 0 1 1 1 1 X 0

Entries from excitation table of D FF Entries from excitation table of SR FF

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J-K Flip Flop to T Flip-Flop

Conversion Table

T input Outputs J-K inputs

Qp Qp + 1 J K 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1

(i) Firstly we have to prepare a table where we have binary (4 bitts, B3 B2 B1 B0)

inputs and gray (4 bits G3 G2 G1 G0) outputs (ii) Truth table is,

(iii) Now the next step is very simple. You draw Kmaps for G3, G2, G1 and G0

separately.

5. (a)

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(iv) Kmaps :

(v) Circuit :

1) A shift register which can shift the data in only one direction is called as a unidirectional shift register.

2) A shift register which can shift the data in both the directions is called as a bi-directional shift register.

3) Applying the same logic, a shift register which can shift the data in both the directions (shift right or left) as well as load it parallely, then it is called as a universal shift register.

5. (b) Vidy

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Figure shows the logic diagram of a universal shift register. This shift register is capable of performing the following operations : 1) Parallel loading (parallel input parallel output) 2) Left shifting 3) Right shifting The Mode control input is connected to Logic 1 for parallel loading operation

whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts

as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to

AND gate-1 in Figure 1. Whereas for the shift right operation, the serial input is applied to D input (input of

AND gate 8). The well-known example of universal shift register in the IC form is IC7495.

Fig. 1: Logic diagram of a universal shift register

4) Universal Shift Register IC 7495 :

General description : IC 7495 is a TTL MSI shift register. It is a 4-bit shift register with serial and parallel synchronous operating

modes. Because of its capability to operate in all the possible modes, it is called as a

universal shift register. Vidy

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Serial Shift Right Operation

The connection diagram for serial shift right mode is shown in Figure 2. Make mode control = 0, therefore AND gates 1, 3, 5, 7 will be enabled and

AND gate 2, 4, 6, 8 will get disabled. Hence the ABCD inputs become don’t care.

The data input to FF-A is now the serial input. Clock 2 input is don’t care. This is because AND gate 9 is enabled and gate

10 is disabled. Apply CLOCK input to clock 1.

A HIGH to low transition on enabled clock 1 input transfers data serially from serial input to QA, QA to QB, QB to QC to QD respectively (right shift).

Serial Shift Left Operation

The connection diagram of 7495 for the shift left operation is shown in figure 3. Note that QD is connected to C, QC to B and QB to A and the serial data is applied at input D.

Mode control is connected to 1. Hence the AND gates 2, 4, 6, 8 are enabled whereas 1, 3, 5 and 7 are disabled.

This will make the serial input (pin no. 1) a don’t care input. The serial data is applied to D which will be routed through the enabled AND

gates 2, 4, 6, 8 to facilitate the right shifting operation. As M = 1, AND gate 10 is enabled and gate 9 is disabled. So clock 1

becomes a don’t care input. Apply clock pulses to CLK 2 (shift left). Each high to low transition of clock will transfer data from D to QD, QD to QC,

QC to QB and QB to QA. Thus the shift left operation is performed.

QA QB QC QD

CLK 2 6

1

9

7495

13 12 11 10

Direction of data shifting

Mode control =0

Serial input

0 1

Fig. 2: 7495 connected for serial right shifting

B QB C QD

CLK 2 1

7495 Mode control = 1

Serial input

0 1

Clock

QB A

D

M

+VCC

Fig. 3: 7495 connected for serial shift left operation Vidyala

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High Speed CMOS The high speed CMOS devices have silicon gates instead of metal gates. This improved version of CMOS ICs has higher switching speeds and higher output current capacity. The high speed CMOS devices are pin compatible and functionally equivalent to TTL ICs with the same device numbers.

Comparison of CMOS and TTL Families

Parameter CMOS TTL

Silicon

gate CMOS

Metal gate

CMOS 74 74LS 74AS 74ALS

VIH (min) 3.5 3.5 2.0 2.0 2.0 2.0 VIL (max) 1.0 1.5 0.8 0.8 0.8 0.8 VOH (min) 4.9 4.95 2.4 2.7 2.7 2.7 VOL (max) 0.1 0.05 0.4 0.5 0.5 0.4

VNH 1.4 1.45 0.4 0.7 0.7 0.7 VNL 0.9 1.45 0.4 0.3 0.3 0.4

Propagation Delay (ns) 8 105 10 10 1.5 4

Power per gate (mW) 0.17 0.1 10 2 8.5 1

Speed power product or figure

or merit 1.4 pJ 10.5 pJ 100 pJ 20 pJ 12.8 pJ 4 pJ

Input connection Input cannot be left open. It has to be connected to 0, or to VDD or to the another input.

Input can be left open. It is treated as logic high input.

Power dissipation

Very less, but increases with increase in switching speed

More than CMOS. It is constant, does not depend on switching speed.

Fan out Fanout is more than TTL typically 50 Fanout for TTL is 10.

Noise More susceptible to noise Less susceptible to noise.

De Morgan's theorem : The two theorems suggested by De-Morgen and which are extremely useful in Boolean algebra are as follows :

Theorem 1 : AB A B : NAND = Bubbled OR • This theorem states that the complement of a product is equal to addition of

the complements. • This rule is illustrated Fig.1. The left hand side (LHS) of this theorem

represents a NAND gate with inputs A and B whereas the right hand side (RHS) of the theorem represents an OR gate with inverted inputs.

• This OR gate is called as "Bubbled OR". Thus we can state De-Morgans first theorem as,

NAND = Bubbled OR

6. (b)

6. (a)

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Fig.1 : Illustration of De-Morgan's first theorem.

This theorem can be verified by writing a truth table as shown in Fig.2. Theorem 2 : A B A.B : NOR = Bubbled AND

• The LHS of this theorem represents a NOR gate with inputs A and B whereas the RHS represents an AND gate with inverted inputs.

• This AND gate is called as "Bubbled AND". Thus we can state De-Morgan's second theorem as :

NOR = Bubbled AND

Fig. 3 : Illustration of De-Morgan's second theorem.

• This theorem can be verified by writing a truth table for both the sides of the

theorem statement. This truth table is shown in Fig. 4, which shows that LHS = RHS.

A B AB A B A B 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0

Fig. 2 : Verification of the theorem AB A B LHS RHS AB A B

A B A B A B A.B

0 0 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 0

Fig.4 : Truth table to verify De-Morgan's theorem

LHS RHS A B A.B Vidyala

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Difference between CPLDs & FPGAs

CPLDs FPGAs Architecture Large, wide fan-in blocks of

AND-OR logic Array of small logic blocks surrounded by I/O

Applications Bus interfaces complex state machines fast memory interfaces wide decoders PAL-device integration

Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces

Key Attributes Fast pin-to-pin performance Predictable timing Easy to use

Very high density lots of I/Os and flip-flops generally lower power SRAM devices are reprogrammable.

Gate Capacity 300-6,000 gates 800-100,000 gates Design Timing Fixed, PAL-like very fast pin-

to-pin performance Application dependent very high shift frequencies

Number of I/Os

30-200 50-400

Number of Flip-flops

30-200 100-5,500

Process Technology

EPROM EEPROM FLASH

SRAM Anti-fuse EEPROM

In-System Programmable

Some EEPROM- and FLASH-based devices

SRAM-based devices and some EEPROM-based devices

One-Time Programmable (OTP)

EPROM devices in plastic packages. Some EEPROM- and FLASH-based devices

All anti-fuse-based devices

Power Consumption

0.5-2.0W static 0.5-4.0W dynamic

Very low static dynamic consumption is application dependent, 0.1-2W typical

(1) Canonical is a word used to describe a condition of a switching equation. In

normal use the work means “conforming to a general rule.” The “rule,” for switching logic, is that each term used in a switching equation must contain all of the available input variables. Two formats generally exist for expressing switching equations in a canonical form: Sums of minterms and products of maxterms.

(2) Canonical sum of products A canonical sum of products is a complete set of minterms that defines when an output variable is a logical 1. Each minterm corresponds to the row in the truth table where the output function is 1; that is, the SOP for the output M is

M = a’bms + ab’ms + abms (3) Canonical product of sums : A canonical product of sums is a complete set

of maxterms that defines when an output is a logical 0. Each maxterm

6. (d)

6. (c)

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corresponds to a row in the truth table where the output is a 0; that is, the POS for the output O1 is

O1 = (C1 + C2 + C3) (C1 + C2 + C3) (C1 + C2 + C3) (C1 + C2 + C3) (C1 + C2 + C3)

(4) To place a SOP equation into canonical form using Boolean algebra, we do the following : (i) Identify the missing variable(s) in each AND term. (ii) AND the missing term and its complement with the original AND term,

xy(Z+Z). Because (Z+Z) = 1, the original AND term value is not changed.

(iii) Expand the term by application of the property of distribution, xyz+xyz.

(5) To place POS equation into canonical form using Boolean algebra, we do this : (i) Identify the mission variable(s) in each OR term. (ii) OR the missing term(s) and its complement with the original OR term,

x+y+zz. Because zz = 0, the original OR term value is not changed. (iii) Expand the term by application of distributive property,

(x+y+z)(x+y+z).

(6) P = f(a, b, c) = ab + ac + bc (SOP) (i) First term, ab, is missing the variable c. So we AND (c+c) with ab:

ab = ab (c + c) = abc + abc

(ii) Second term, ac, is missing the variable b. So we AND (b+b) with ac. ac = ac (b+b) = abc + abc

(iii) Third term is missing the variable a. So we AND (a+a) with bc. bc = bc (a+a) = abc + abc

(iv) The final canonical SOP form is P = abc + abc + abc + abc + abc + abc

Note that two terms, the second and the fourth, are identical. Only one is needed, because any variable or group of variables ORed with itself is redundant : x + x = x (property of idempotency or sameness). The final equation becomes

P = abc + abc + abc + abc + abc

(7) (c) T = f(a,b,c) = (a + b)(b + c) (POS) (i) The variable c is missing from the first term.

a + b + cc = (a + b + c)(a + b + c) (ii) The variable a is missing from the second term.

b + c + aa = (a + b + c)(a + b + c) (iii) The complete equation is

T = f(a, b, c) = (a + b + c)(a + b + c)(a + b + c) Features of VHDL (Derived from Capabilities) VHDL has powerful constructs VHDL language supports hierarchy (i.e modelled using a set of

interconnected components)

6. (e)

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VHDL is not case sensitive VHDL supports both synchronous and asynchronous timing models. Concurrency timing and clocking can be modeled using VHDL VHDL is target independent VHDL supports design library VHDL has flexible design methodologies i.e. TOP DOWN, BOTTOM UP,

MIXED The logical behavior and timing behavior of the design can be modeled using

VHDL. VHDL is not technology specific i.e. VHDL is not dependent on the specific

manufacturer i.e. XILINX or LATTICE.

VHDL’s technology specific feature allows to specify components from various vendors

VHDL also allows the user to specify his own data type and component VHDL is publicly available and has no proprietary.

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s.e. sem. iii [cmpn] digital logic design and analysis...

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