school of engineering themen: variablen architecture-types
TRANSCRIPT
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School ofEngineering
Themen:
Variablen
Architecture-Types
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School ofEngineering
Variablen
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School ofEngineering
Abstimmanlage: version-A
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY abstimm ISPORT ( a,b,c : in std_logic;
y: out std_logic);END abstimm;
ARCHITECTURE comb OF abstimm IS
BEGINy <= (a and b) or (a and c) or (b and c);
END comb;
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School ofEngineering
Abstimmanlage: version-B
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY abstimm_whenelse ISPORT ( a,b,c : in std_logic;
y: out std_logic);END abstimm_whenelse;
ARCHITECTURE comb OF abstimm_whenelse IS SIGNAL x : std_logic_vector (2 DOWNTO 0);
BEGINx <= a & b & c;y <= '1' WHEN ((x="011") or (x="101") or (x="110") or (x="111")) ELSE '0';
END comb;
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School ofEngineering
Abstimmanlage: version-C
ARCHITECTURE rtl OF abstimm_case IS
BEGINcomb_log : process(a,b,c)
variable x : std_logic_vector (2 DOWNTO 0);BEGIN
x := a & b & c;CASE x IS
WHEN "011" => y <= '1';WHEN "101" => y <= '1';WHEN "110" => y <= '1';WHEN "111" => y <= '1';WHEN OTHERS => y <= '0';
END CASE; END PROCESS;
END rtl;
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School ofEngineeringVariablen
Variablen kann man benutzen, um innerhalb eines Prozessesoder eines Unterprogramms einen Wert temporär zu speichern
VARIABLE variablen_name : type [:= initialisierung];
VARIABLE summe : std_logic_vector (2 downto 0) := “101“ ;
Zuweisungsoperator :=
Beispiel:
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School ofEngineering
● Kann man nur in Prozessen oder Unterprogrammen benutzen.
● Werden deshalb zwischen den Zeilen „Prozess“ und „Begin“ definiert.
● Variablen müssen vor Gebrauch initialisiert werden.
● Sind Global nicht verfügbar (ausserhalb des Prozess)
● Will man Variablen ausserhalb eines Prozesses weiterbenutzen, muss man Sie einem Signal zuweisen.
● Sind nach der Zuweisung sofort gültig, nicht erst beim Verlassen des Prozesses.
● Können als Index oder temporärer Speicher innerhalb eines Prozesses benutzt werden.
● Zuweisung durch :=
Variablen
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School ofEngineering
Variablen: weitere Beispiele
Extract from Schaltungsdesign mit VHDL, Lehmann, Wunder, Selz, S.153
ENTITY mult ISPORT (a, b : IN integer := 0; y : OUT integer) ;END mult ;
ARCHITECTURE number_one OF mult ISBEGIN
PROCESS (a,b) -- Aktivierung durch Ereignisse auf a oder b VARIABLE v1, v2 : integer := 0 ; BEGIN v1 := 3 * a + 7 * b ; -- sequent. Variablenzuweisung v2 := a * b + 5 * v1 ; -- sequent. Variablenzuweisung y <= v1 + v2 ; -- sequent. Signalzuweisung END PROCESS ;
END number_one ;
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School ofEngineering
Variablen: weitere Beispiele
Extract from lcddriver.vhd (used in GPS_Uhr project)…type CHAR_RAM_TYPE is array(0 to 79) of std_logic_vector(7 downto 0);signal charRAM : CHAR_RAM_TYPE := (others=>x"00");
…CharRAMWrite : process(clk)
variable add : integer range 0 to 79;begin
if (clk'event and clk='1') thenif (wen='1') then
add := to_integer(unsigned(charNum));charRAM(add) <= dIn;
end if;end if;
end process;…
Achtung: Eine Variable muss vor Gebrauch zugewiesen werden!
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School ofEngineering
Variablen
exp_var: PROCESS (clk, reset)
variable correct_v : std_logic;
beginIF reset = '1' then
a <= '0';b <= '0';
ELSIF clk’event AND clk = 1 THENcorrect_v := c and d;a <= e or correct_v;b <= f or correct_v;
END IF;END PROCESS exp_var;
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School ofEngineering
Variable korrekt benutzt
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
a~0 a~reg0
b~0 b~reg0correct_v~0
clk
reset
cd
e
f
a
b
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School ofEngineering
exp_var: PROCESS (clk, reset)variable incorrect_v : std_logic;BEGIN
IF reset = '1' THENa <= '0';b <= '0';
ELSIF clk'event AND clk='1' THENa <= e or incorrect_v;b <= f or incorrect_v;incorrect_v := c and d;
END IF;END PROCESS exp_var;
Eine Variable muss vor Gebrauch zugewiesen werden!
Falsche Benutzung einer Variablen (1)
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School ofEngineering
Variable falsch benutzt
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
D
ENA
QPRE
CLR
\exp_var:incorrect_v
a~0 a~reg0
b~0 b~reg0incorrect_v~0
clkreset
cd
ef
a
b
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School ofEngineering
Schlechtes Beispiel
Extract from lcddriver.vhd (used in GPS_Uhr project)…-- Tick Generationsubtype TICK_COUNTER_TYPE is integer range 0 to tickNum;signal tick: std_logic;…TickGen : process(clk)
variable tickCounter : TICK_COUNTER_TYPE;begin
if (clk'event and clk='1') thenif (tickCounter = 0) then
tickCounter := TICK_COUNTER_TYPE'high-1;tick <= '1';
elsetickCounter := tickCounter - 1;tick <= '0';
end if;end if;
end process;
Generiert Speicher, da Variable vor Initialisierung gebraucht
Für dieses Beispiel nimmt man besser ein Signal
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School ofEngineering
Synthese Tick Counter
A[3..0]
B[3..0]
OUT[3..0]
ADDER
A[2..0]
B[2..0]OUT
EQUAL
D
ENA
QPRE
CLR
D QPRE
ENA
CLR
SELDATAA
DATABOUT0
MUX21
Equal0
3' h0 --
clk
tick
tick~reg0\TickGen:tickCounter[2..0]
Add0
1' h1 --
4' hD --
tickCounter~[2..0]
3' h3 --
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School ofEngineering
Signale vs. Variablen
Signale VariablenExistieren global in der gesamten Architektur
Nur lokal im Prozess lesbar
Werden am Ende des Prozesses aktualisiert.
Werden immer sofort aktualisiert
Werden zwischen „Architectur“ und „Begin“ deklarieret
Werden zwischen „Process“ und „Begin“ deklarieret
Zuweisung v <= ‘1‘ Zuweisung v := ‘1‘
Achtung: Eine Variable muss vor Gebrauch zugewiesen werden!
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School ofEngineering
Architecture Types- rtl (register-transfer-logic: synthesisable)- behav (behavioural: testbench )- struct (structural: hierarchy)
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School ofEngineering
Architecture examples: rtl
…extracts of counter.vhd Ueb5-Auf2…architecture rtl of counter is signal next_countL: unsigned(3 downto 0); signal countL: unsigned(3 downto 0);begin comb_increment: process (load,enable,data,countL) begin if (load = '1') then next_countL <= unsigned(data); elsif (enable = '1') then next_countL <= countL + 1; else next_countL <= countL; end if; end process; reg_increment: process (clk,reset) begin if (reset = '1') then countL <= "0000"; elsif(clk'event and clk = '1') then countL <= next_countL; end if; end process; count <= std_logic_vector(countL);end rtl;
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School ofEngineering
Architecture examples: behav
…extracts of testbench_wuerfel.vhd…
ARCHITECTURE behav OF testbench_wuerfel ISCOMPONENT wuerfel_ifelse
PORT ( Q2, Q1, Q0 : IN std_logic; A, B, C, D : OUT std_logic );
END COMPONENT;…BEGIN…STIMULUS: PROCESS BEGIN tin <= "000" ; WAIT FOR 10 ns;
tin <= "001" ; WAIT FOR 10 ns; ASSERT (tout_if = "0001") REPORT "expected tout_if = 0001 " SEVERITY error;
WAIT FOR 100 ns; tin <= "010" ; WAIT FOR 10 ns;
ASSERT (tout_if = "1000") REPORT "expected tout_if = 1000 " SEVERITY error; WAIT FOR 100 ns;
ASSERT false REPORT " --- ALL TESTS PASS ---" SEVERITY failure; WAIT;
END PROCESS; END behav;
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School ofEngineering
Architecture examples: behav
…extracts of testbench_abstimm_case.vhd…
ARCHITECTURE behav OF testbench_abstimm_case ISCOMPONENT abstimm
PORT ( a,b,c : IN std_logic; y : OUT std_logic );
END COMPONENT;…
SIGNAL tin : std_logic_vector(2 DOWNTO 0);SIGNAL tout : std_logic_vector(2 DOWNTO 0);
BEGIN-- Block Instantiationsdut1: abstimm
PORT MAP( a => tin(2), b => tin(1), c => tin(0), y => tout(2));
…
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School ofEngineering
Architecture examples: behav
…extracts of testbench_abstimm_case.vhd…
STIM_CHK: PROCESS -- DECLARE PROCEDURE TO AVOID REPEATING TEST STATEMENTS PROCEDURE single_test (tin_test : IN std_logic_vector; tout_test: IN std_logic) IS BEGIN tin <= tin_test; WAIT FOR 10 ns; ASSERT ((tout(2) = tout_test) AND (tout(1) = tout_test) AND (tout(0) = tout_test)) REPORT "test failed for 1 or more duts!" SEVERITY error; WAIT FOR 40 ns; END PROCEDURE single_test;
BEGINsingle_test("000",'0');single_test("001",'0');single_test("010",'0');single_test("011",'1');…-- END SIMULATIONASSERT false REPORT " --- ALL TESTS PASS ---" SEVERITY failure;
END PROCESS; END behav;
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School ofEngineering
Architecture examples: struct
…extracts of top_max.vhd…
ARCHITECTURE struct OF top_max IS---------------------------- COMPONENT DECLARATIONS--------------------------COMPONENT count_updown
GENERIC(n : natural; ov_value : unsigned );
PORT ( clock : in std_logic; reset_n : in std_logic; cntup : in std_logic;
count : out std_logic_vector(n-1 downto 0));END COMPONENT;
COMPONENT sieben_seg_ctrlPORT(…)
END COMPONENT;---------------------------- SIGNAL & CONSTANT DECLARATIONS-------------------------- CONSTANT Low : std_logic := '0'; CONSTANT High : std_logic := '1'; CONSTANT breite : natural :=26; CONSTANT ueberlauf : unsigned := TO_UNSIGNED(49999999,N); SIGNAL m_count : std_logic_vector(N-1 DOWNTO 0);
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School ofEngineering
Architecture examples: struct
…extracts of top_max.vhd……BEGIN---------------------------- DUT INSTANTIATIONS--------------------------dut_count: count_updown
GENERIC MAP(n => breite,ov_value => ueberlauf)
PORT MAP( clock => clock, reset_n => reset_n, cntup => ctrl, count => m_count);
dut_sseg : sieben_seg_ctrlPORT MAP(…)
END struct;
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School ofEngineering
VHDL Fallen
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School ofEngineering
Sauber_so: process(s)BEGIN If s = '1' THEN x <= '1' ; ELSE x <= '0'; END IF;
END PROCESS;
autsch: process(s)BEGIN If s = '1' THEN x <= '1' ; END IF;
END PROCESS;
elegant: process(s)BEGIN x <= '0'; If s = '1' THEN x <= '1' ; END IF;
END PROCESS;
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VHDL Fallen
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School ofEngineering
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3
>1
SX
XS
XS
Process: sauber_so
Process: autsch
Process: elegant Latch
VHDL Fallen