Sandip Bhadani SUMMARY: 3.5 years of experience in ASIC verification including development of Verification IPs, test Plan definition, test cases and verification environment development & SoC verification. Experience in SystemVerilog based verification IP, BFM development and functional coverage. Experience of working as team member for MIPI, I2C, AMBA AHB and AXI VIP development using OVM, UVM and Pure System Verilog environment. Working Experience in SoC verification Experience in working with FPGA full chip verification.Skills:NameDescription

HDL / HVLSystemVerilog , Verilog, C++, SystemC

Protocols & InterfacesLPDDR4, MIPI DSI, AMBA AXI, AHB/APB, I2C, SPI

Scripting LanguagesPerl , shell

EDA ToolsMentor QuestaSim, Cadence IUS

Verification MethodologyOVM , UVM

Educational Qualification:B.E. (Electronics & Communication), Dharmsinh Desai University, Nadiad, India (2012)

Experience Details:Arastu Systems:Dec 2014 Till date Sibridge Technologies: Dec 2011 Nov 2014

Project Details:1. Verification of LPDDR4 controller - JEDEC standard JESD209-4 Developed AXI slave design using SystemC Developed LPDDR4 Bus monitor and checkers according to JEDEC standard JESD209-4 Monitor, Checkers are developed in SystemVerilog using UVM methodology

2. MIPI DSI Verification IP development Developed MIPI's Display Serial Interface (DSI) protocol verification IP in SystemVerilog for UVM methodology. Responsible for defining test plan Responsible for development of MIPI DSI host driver and data class

3. Functional verification of FPGA configuration logicIt was verification of base logic to configure FPGA device. FPGS fabric contains different interfaces like Master SPI, Slave SPI, JTAG, I2C etc. standard interface as well as one custom interface to configure a bit stream file using this interface. At the target side there is SRAM, embedded block RAM, EFUSE memory to store bit stream data, memory configuration & one-time programmable information. And this base FPGA logic contains instruction decoder, decryption & decompression logic. Responsible for development of Verification environment in UVM Responsible for development of SPI & EFUSE Verification IP to use as configuration interface Responsible for scoreboard development for verification environment in UVM

4. Developed Integrated AMBA AHB, AXI & APB protocols Responsible for development of AMBA VIP in SystemVerilog that contains instance of either of AHB, AXI or APB agent. This module converts AMBA data class to appropriate AHB, AXI or APB data class and drives using existing VIP agents. Developed VIP-VIP verification environment for same in UVM

5. SPI Verification IP Responsible for development of SPI drivers (master, slave) & monitor using UVM methodology Responsible for development of test cases of multi-slave configuration of verification IP Responsible for checkers development in SystemVerilog

6. Functional and Full Chip Verification of subsystem design including PCS SerDesThis chip contains 2 parts, ASIC and FPGA. The ASIC part contains PCS and SerDes for different protocols like PCIe, Ethernet, CPRI etc. Our task was to verify clock domain crossings from hard macro (ASIC part) to soft logic (FPGA part) 1. Developed verification environment and scoreboard including protocol independent subsystem IO agent using UVM methodology.1. Actively involved in RTL verification which includes the hard macro (PCS + SerDes) and soft logic. Also worked on the gate-level simulation1. Responsible to run the simulation for full chip using the bit stream generated for FPGA1. Debugged and reported the issues in full chip simulation (simulation with bit stream)

7. AMBA AHB and AXI Verification IP Responsible for development of complete verification test suits for AMBA AHB and AXI-3 VIP-VIP and VIP to Design IP verification using OVM and UVM Responsible for debugging of master and slave BFM in case of failure of test cases due to protocol violation Responsible for development of checks using procedural statement for AMBA AXI-3 design Responsible for integrating AHB/AXI verification IP with other design IP for verification

8. I2C Verification IP Responsible for development of I2C monitor using OVM methodology Responsible for development of test cases for multi-master & multi-slave configuration of verification IP and debugging in case of any failure of test cases Responsible for checkers development in SystemVerilog