sama5d2 dynamic memory implementation...

AN2717 SAMA5D2 Dynamic Memory Implementation Guidelines

Scope

This application note provides design recommendations for SAMA5D2 series microprocessors regardingPCB layout and software settings to ensure proper device functionality with multiple SDRAM devicetypes.

Reference Documents

• SAMA5D2 Series datasheet (Lit. No. DS60001476). Available on www.microchip.com.• Technical Note TN-46-14: Hardware Tips for Point-to-Point System Design Introduction – Micron

Technology Inc. Available on http://www.micron.com.• Standard IPC-2141: Controlled Impedance Circuit Boards and High Speed Logic Design, 1996 –

Institute for Interconnection and Packaging Electronic Circuits, 2215 Sanders Road, Northbrook, IL60062, 847-509-9700

Software Used

• IAR Embedded Workbench for ARM 7.80.1.11873• SAM-BA 3.2.1• Altium Designer 18.0.2

Hardware Used

• SAMA5D2-XULT (official demo kit)• SAMA5D2-PTC-EK (official demo kit)• MPUx-DRAMx (internal R&D board)

© 2018 Microchip Technology Inc. DS00002717A-page 1

http://www.microchip.comhttp://www.micron.com

Table of Contents

Scope.............................................................................................................................. 1

Reference Documents.....................................................................................................1

Software Used.................................................................................................................1

Hardware Used................................................................................................................1

1. SAMA5D2 DDR Controller Capabilities.....................................................................3

2. Our Approach............................................................................................................ 4

3. Hardware Aspects..................................................................................................... 73.1. SAMA5D2-XULT Development Kit............................................................................................... 83.2. SAMA5D2-PTC-EK Development Kit.........................................................................................143.3. SAMA5D24/BGA256 Custom Test Board.................................................................................. 21

4. Software Aspects.....................................................................................................474.1. On-board SDRAM Device(s) Initialization Sequence.................................................................474.2. SDRAM Controller Configuration............................................................................................... 53

5. Setting Recommendations...................................................................................... 75

6. Conclusion...............................................................................................................77

7. Revision History.......................................................................................................787.1. Rev. A - 06/2018.........................................................................................................................78

The Microchip Web Site................................................................................................ 79

Customer Change Notification Service..........................................................................79

Customer Support......................................................................................................... 79

Microchip Devices Code Protection Feature................................................................. 79

Legal Notice...................................................................................................................80

Trademarks................................................................................................................... 80

Quality Management System Certified by DNV.............................................................81

Worldwide Sales and Service........................................................................................82

AN2717


1. SAMA5D2 DDR Controller CapabilitiesThe SAMA5D2 series MPU features a Multiport DDR-SDRAM Controller (MPDDRC).

The MPDDRC is a high-bandwidth scrambleable 16-bit or 32-bit Double Data Rate (DDR) multiportmemory controller supporting up to 512-Mbyte 8-bank DDR2, DDR3, DDR3L, LPDDR1, LPDDR2 andLPDDR3 devices. Data transfers are performed through a 16/32-bit data bus on one chip select.

The controller operates with the following power supplies:

• DDR2, LPDDR1: 1.8V• DDR3: 1.5V• DDR3L: 1.35V• LPDDR2, LPDDR3: 1.2V

This application note covers the implementation of the above-mentioned devices providing layoutexamples and software support.

AN2717SAMA5D2 DDR Controller Capabilities


2. Our ApproachThe essential objective of this application note is to provide SAMA5D2 adopters with practicalimplementation guidelines and software settings, inferred from actual hardware and extensive testsperformed on that hardware:

Figure 2-1. Obtaining Optimal Hardware and Software Implementation

Design a board

Perform basic functionalverification

Determine “functional” low level settings

Perform preliminary tests (and refine low level settings)

Develop stress test algorithm (multipattern

+ temperature conditionvariation)

Perform extensivetesting campaign,

confirm validparameters

PCB design filesand layout recommendations

Memory controller settingsdata and procedure

Confirm valid parameters+ proof of some invalid parameters

Collect datato “feed” the

application note

To ensure proper functionality of all SDRAM devices supported by the external memory controller(MPDDRC), numerous hardware and software considerations must be taken into account. While lowspeed circuits have few physical constraints on the PCB, circuits featuring high speed signals do haveconstraints that must be applied regarding trace length, width and clearance, PCB stacking and lengthmatching. These rules were applied when designing previously released development kits likeSAMA5D2-XULT and SAMA5D2-PTC-EK. In addition, a custom board has been designed and producedfor the purpose of further testing to ensure proper compatibility of SAMA5D2 MPUs with all supportedSDRAM devices, from different manufacturers.

Apart from the boards, several pieces of testing software were developed. See the figure below.

AN2717Our Approach


Figure 2-2. Stress Test Algorithm

Run all available testcases at roomtemperature

Set climatechamberat 0°C

Run all testcases

Continuouslymonitor results

Testedat 70°C?

Yes

No

Stop testing cycle

Increment testingtemperature

by 10°C

The table below describes the testing cases.

Table 2-1. Testing Cases

Test Case No. Description Purpose

1 Performs pin stuck at high/low testWrites sequential data patterns

Checks data integrity

2 Generates and writes random data Checks data mismatch, unaligned access

3 Generates and transfers large data buffers Checks data transfers in memory via DMAcontroller

All SDRAM devices are tested at a clock frequency of 166 MHz (clock period is 6 ns).

AN2717Our Approach


Important: The board that we used for the tests was designed for use in a commercialtemperature range, therefore our study is limited to the 0 to +70°C range. This does in no waymean that the components involved - SAMA5D2 and DDR memory – are limited to function inthat range. On the contrary, industrial grades are available and work equally well in theextended -40/+85°C range.

We performed such tests using a programmable climatic chamber.

During testing, all test results returned were logged for further analysis.

AN2717Our Approach


3. Hardware AspectsFormerly released development kits containing SDRAM devices can be used as references whendesigning a new board. Layout examples for SDRAM implementation are provided.

Also, some general guidelines must be followed when routing such devices. Most SDRAM manufacturersprovide application notes concerning high speed signal routing, usually offering minimum andrecommended constraints for trace width, clearance, length matching, etc. The distances are measuredin mils, the usual metric for PCB design, where 1 mil = 0.0254 mm.

The SDRAM controller interface includes:

• Four data byte lanes (see Note 1): DQS[3:0], DQSN[3:0], DQM[3:0], D[31:0]• ADDR/CMD/CTL signals: BA[2:0], A[13:0], RAS/CAS, CS, CKE, WE, RESETN• Clock signals: CK/CKn

Here is an exhaustive list of design guidelines for SDRAM signals, grouped by signal types (refer toTechnical Note TN-46-14):

• All SDRAM signals:– Trace width (see Note 2) for all signals should be 4 mils minimum (0.101 mm) and nominal

width should be 6 mils (0.152 mm).– The reference power planes must have no splits across any high-speed signal.– The impedance of any single-ended signal trace should be 50 ±10% Ω.– The impedance of any differential signal trace should be 100 ±10% Ω.

• Data lane signals recommendations:– Clearance between two adjacent data signals (includes D, DQS, DQM) should be 8 mils

minimum and 12 mils nominal (see Note 2).– Signals belonging to the same data byte lane should be routed on the same layer.– Trace length difference between signals from the same data byte lane should not exceed 50

mils.– Different D byte lanes should be matched within 0.5 inch of each other.– DQS/DQSN signal pairs should be routed as differential signals with the length difference

between traces not exceeding 20 mils.– The length difference between any data byte lane signal and CK/CKn should not exceed 400

mils.• Address/Control/Clock signals recommendations (see Note 2):

– Clearance between command/control signals should be 6 mils minimum and 15 mils nominal.– Clearance between address signals should be 6 mils minimum and 12 mils nominal.– Clearance between address/control and data signals should be at least 20 mils.– Clearance between clock signals of the same differential pair should be 4 mils minimum and 6

mils nominal.– Clearance between the differential CK/CKn signal and any other signal should be 8 mils

minimum and 12 mils nominal.– This type of signals should be routed on the same layer.– CK/CKn should be routed as differential signals with the length difference between traces not

exceeding 20 mils.

AN2717Hardware Aspects


– The length difference between any address/control signal and CK/CKn should not exceed 200mils.Note:

1. A data byte lane is a group of SDRAM signals which ensures that byte-formatted dataare properly transferred between the SDRAM device and controller. It features 8 datasignals (D[7:0]), one data mask signal (DQM) and a pair of data strobe signals (DQS/DQSN). An 8-, 16- or 32-bit SDRAM device has one, two or four data byte lanes,respectively.

2. The trace width and clearance values from these recommendations are chosen in orderto match the desired impedance of each signal trace in relation with manufacturablePCB parameters, e.g. dielectric height. Consult the PCB manufacturer to accuratelyoptimize these values.

Refer to Micron technical note TN-46-14 “Hardware Tips for Point-to-Point System Design Introduction”for more details.

3.1 SAMA5D2-XULT Development KitThe SAMA5D2-XULT development kit is built on a 6-layer PCB. The board features a SAMA5D27/BGA289 MPU and two 2-Gbit Micron DDR3L-SDRAM devices (Part No: MT41K128M16JT-125:K).



Figure 3-1. SAMA5D2C-XULT Development Kit rotatethispage90

DDR_VREF

DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15DDR_D16DDR_D17DDR_D18DDR_D19DDR_D20DDR_D21DDR_D22DDR_D23DDR_D24DDR_D25DDR_D26DDR_D27DDR_D28DDR_D29DDR_D30DDR_D31

DDR_DQM0DDR_DQM1DDR_DQM2DDR_DQM3

DDR_DQS0+DDR_DQS0-

DDR_DQS1+DDR_DQS1-

DDR_DQS2+DDR_DQS2-

DDR_DQS3+DDR_DQS3-

DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12DDR_A13

DDR_BA0DDR_BA1

DDR_RASDDR_CAS

DDR_BA2

DDR_CSDDR_WE

DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15




DDR_BA0DDR_BA1DDR_BA2

DDR_BA0DDR_BA1DDR_BA2

DDR_RESETN DDR_RESETN

DDR_CLK+DDR_CLK-DDR_CKEDDR_CSDDR_RASDDR_CASDDR_WE

DDR_CLK+DDR_CLK-DDR_CKEDDR_CSDDR_RASDDR_CASDDR_WE

DDR_DQS0-DDR_DQS0+

DDR_DQS1-DDR_DQS1+

DDR_DQS2+DDR_DQS2-

DDR_DQS3-DDR_DQS3+

DDR_DQM1DDR_DQM0

DDR_DQM3DDR_DQM2

DDR_VREF DDR_VREF

DDR_VREF

DDR_RESETN

DDR_CLK+DDR_CLK-DDR_CKE

VDD_1V35

VDD_1V35

VDD_1V35

VDD_1V35

VDD_1V35

VDD_1V35

VDD_1V35

VDDIODDRL14 10uH_150mA

R242100K

R250

23.2K 1%

C564.7uF

C834.7uF

R243100K

C106

22pF

R178 0R R258 0R

R1806.8K 1%

R179 DNP(1K)

U8

MT41K128M16JT-125:K

CKJ7

CK#K7

CKEK9

CS#L2

RAS#J3

CAS#K3

WE#L3

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BC#N7

A13T3

A14T7

BA0M2

BA1N8

BA2M3

DQ0E3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

ODTK1

VSS1A9

VSS2B3

VSS3E1

VSS4G8

VSSQ4D8VSSQ3D1VSSQ2B9VSSQ1B1

VSSQ5E2

VDDQ1A1

VDDQ2A8

VDDQ3C1

VDDQ4C9

VDDQ5D2

VDD1B2

VDD2G7

UDQS#B7

UDMD3

LDME7

LDQS#G3

UDQSC7

LDQSF3

DQ8D7

DQ10C8

DQ11C2

DQ14B8

DQ12A7

DQ15A3

DQ13A2

VDD9D9

VSSQ6E8

VDDQ6E9

VDDQ7F1

VSSQ7F9

VSSQ8G1

VSSQ9G9

VREFDQH1

VDDQ8H2

VDDQ9H9

NC1J1

NC2J9

VSS5J2

VSS6J8

VDD4K2

VDD5K8

NC3L1

ZQL8

NC4L9

VSS7M1

A15M7

VREFCAM8

VSS8M9

VDD6N1

VDD7N9

VSS9P1

VSS10P9

VDD8R1

VDD3R9

VSS11T1

RESET#T2

VSS12T9

DQ9C3

C55100nF

C121100nF

U4

MT41K128M16JT-125:K

CKJ7

CK#K7

CKEK9

CS#L2

RAS#J3

CAS#K3

WE#L3

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BC#N7

A13T3

A14T7

BA0M2

BA1N8

BA2M3

DQ0E3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

ODTK1

VSS1A9

VSS2B3

VSS3E1

VSS4G8


VSSQ5E2

VDDQ1A1

VDDQ2A8

VDDQ3C1

VDDQ4C9

VDDQ5D2

VDD1B2

VDD2G7

UDQS#B7

UDMD3

LDME7

LDQS#G3

UDQSC7

LDQSF3

DQ8D7

DQ10C8

DQ11C2

DQ14B8

DQ12A7

DQ15A3

DQ13A2

VDD9D9

VSSQ6E8

VDDQ6E9

VDDQ7F1

VSSQ7F9

VSSQ8G1

VSSQ9G9

VREFDQH1

VDDQ8H2

VDDQ9H9

NC1J1

NC2J9

VSS5J2

VSS6J8

VDD4K2

VDD5K8

NC3L1

ZQL8

NC4L9

VSS7M1

A15M7

VREFCAM8

VSS8M9

VDD6N1

VDD7N9

VSS9P1

VSS10P9

VDD8R1

VDD3R9

VSS11T1

RESET#T2

VSS12T9

DQ9C3

C72100nF

C91100nF

R254 DNP(1K)

C54100nF

R238

240R 1%

R124

240R 1%

C145100nF

SAMA5D27C-CU (MRLC)

U6E

DDR_A0F12

DDR_A1C17

DDR_A10C15

DDR_A11A16

DDR_A12A17

DDR_A13G11

DDR_A2B17

DDR_A3B16

DDR_A4C16

DDR_A5G14

DDR_A6F14

DDR_A7F11

DDR_A8C14

DDR_A9D13

DDR_BA0H12

DDR_BA1H13

DDR_BA2F17

DDR_CALE13

DDR_CASG12

DDR_CKEF16

DDR_CLKE17

DDR_CLKND17

DDR_CSG13

DDR_D0B12

DDR_D1A12

DDR_D10H17

DDR_D11K17

DDR_D12K16

DDR_D13J13

DDR_D14K14

DDR_D15K15

DDR_D16B8

DDR_D17B9

DDR_D18C9

DDR_D19A9

DDR_D2C12

DDR_D20A10

DDR_D21D10

DDR_D22B11

DDR_D23A11

DDR_D24J12

DDR_D25H10

DDR_D26J11

DDR_D27K11

DDR_D28L13

DDR_D29L11

DDR_D3A13

DDR_D30L12

DDR_D31M17

DDR_D4A14

DDR_D5C13

DDR_D6A15

DDR_D7B15

DDR_D8G17

DDR_D9G16

DDR_DQM0C11

DDR_DQM1G15

DDR_DQM2C8

DDR_DQM3H11

DDR_DQS0B13

DDR_DQS1J17

DDR_DQS2C10

DDR_DQS3L17

DDR_DQSN0B14

DDR_DQSN1J16

DDR_DQSN2B10

DDR_DQSN3L16

DDR_RASF13

DDR_RESETNE16

DDR_VREFCMD16 DDR_VREFB0H16

DDR_WEF15

R1821R 1%

C100100nF

C99100nF

R1816.8K 1%

AN

2717H

ardware A

spects

© 2018 M

icrochip Technology Inc.

DS00002717A-page 9

Figure 3-2. SAMA5D2-XULT Layer 1 (Top)

Control/command signalsTrace width = 5 milsTrace clearance = 11 mils

Address signalsTrace width = 5 milsTrace clearance = 9 mils

Data signalsTrace width = 5 milsTrace clearance = 9 mils

CK/CKn signalsTrace width = 4 milsTrace clearance = 8 mils

The layout example in the above figure shows the top layer of the board focused on the DDR3-SDRAMrouting. Part of the address signals and the differential clock is present on the top layer, with thementioned trace width and minimum clearance. These values are equal to or above the minimumrequired. There is also a 30 mils clearance between the control/command and data signals, above theminimum required.



Figure 3-3. SAMA5D2-XULT Layer 6 (Bottom)

Data lane 2 (D16-D23)Trace width = 5 milsTrace clearance = 11 mils


The above figure shows the bottom layer of the DDR3-SDRAM layout. Signals from two data lanes arebeing routed on the bottom layer, belonging to data lane 2 (D16-D23) and data lane 0 (D0-D7), includingtheir respective DQS/DQSn and DQM signals. Trace width used is 5 mils, and the smallest clearance is 9mils, both values exceeding the minimum required. These traces are tightly matched, the maximummismatch length not exceeding 7 mils, well below the maximum allowed.



Figure 3-4. SAMA5D2-XULT Layer 5 (VDD)

The above figure shows layer 5 of the board, used as power plane. The highlighted region covers thetraces belonging to the DDR3-SDRAM routing and serves as reference plane for the impedancematching of the bottom traces. Also, it contains no splits across any high-speed signal.

The trace impedance for top or bottom layers is calculated using the impedance formula (according toStandard IPC-2141) for a microstrip line:

Equation 1

Z0(Ω)=87��+ 1.41 �� 5.98�0.8�+ �

Where εr is the dielectric constant, H is the dielectric height, W is the trace width and T the tracethickness.

In our case (available in Table SAMA5D2-XULT Detailed PCB Stack-up):

• εr = 3.95 for FR-4 dielectric• H = 3.8207 mils between bottom layer (layer 6) and power plane (layer 5)• W = 5 mils width for bottom traces• T = 1.87 mils copper thickness.



Using the above parameters, the trace impedance is calculated to be Z0 = 51.18 Ω, covered by the ±10%tolerance.Figure 3-5. SAMA5D2-XULT PCB Stacking

Table 3-1. SAMA5D2-XULT Detailed PCB Stack-up

Layer Name Type Material Thickness[mm]

Thickness[mil]

DielectricMaterial

DielectricConstant

Top Overlay Overlay – – – – –

Top Solder SolderMask/Coverlay

SurfaceMaterial

0.01016 0.4 Solder Resist 3.5

TOP Signal Copper 0.0475 1.87 – –

Dielectric1 Dielectric Core 0.09705 3.8207 FR-4 3.95

GND2 Signal Copper 0.03048 1.2 – –


INT3 Signal Copper 0.03048 1.2 – –


INT4 Signal Copper 0.03048 1.2 – –


VCC5 Signal Copper 0.03048 1.2 – –


BOTTOM Signal Copper 0.0475 1.87 – –




Thickness[mil]

DielectricMaterial

DielectricConstant

Bottom Solder SolderMask/Coverlay

SurfaceMaterial


BottomOverlay

Overlay – – – – –

3.2 SAMA5D2-PTC-EK Development Kit



Figure 3-6. SAMA5D2-PTC-EK Development Kitrotatethispage90

DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15DDR_D16DDR_D17DDR_D18DDR_D19DDR_D20DDR_D21DDR_D22DDR_D23DDR_D24DDR_D25DDR_D26DDR_D27DDR_D28DDR_D29DDR_D30DDR_D31

DDR_DQM0DDR_DQM1DDR_DQM2DDR_DQM3

DDR_DQS0+DDR_DQS0-

DDR_DQS1+DDR_DQS1-

DDR_DQS2+DDR_DQS2-

DDR_DQS3+DDR_DQS3-


DDR_BA0DDR_BA1

DDR_RASDDR_CAS

DDR_BA2

DDR_CSDDR_WE

DDR_VREF

DDR_RESETN

DDR_CLK+DDR_CLK-DDR_CKE

DDR_VREF

DDR_VREFDDR_VREF

DDR_DQM0DDR_DQM1

DDR_DQM2DDR_DQM3

DDR_DQS0-DDR_DQS0+

DDR_DQS1+DDR_DQS1-

DDR_DQS2+DDR_DQS2-DDR_DQS3+DDR_DQS3-

DDR_BA1DDR_BA0

DDR_BA1DDR_BA0

DDR_WE DDR_WEDDR_CSDDR_CS

DDR_CLK-DDR_CLK+

DDR_CLK-DDR_CLK+

DDR_CKE DDR_CKE

DDR_CASDDR_RAS

DDR_CASDDR_RAS



DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12

DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12

DDR_BA2 DDR_BA2

DDR_A13DDR_A13

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

VDDIODDR

GND_POWER

VDD_1V8GND_POWER

VDD_1V8

GND_POWER

GND_POWER

VDD_1V8GND_POWER

VDD_1V8

GND_POWER

VDDIODDR

R23100KR0402

R25100KR0402

C63100nFC0402

C6422pF

C0402

C67100nFC0402

R2421K-1%

R0402

R32 0R R0402

C951nFC0402

C66100nFC0402

R30 0R R0402

C654.7uFC0805

C751nFC0402

R31 DNP R0402

R272.2K-1%R0402

U7

W972GG6KB-25bga84-32-1509e

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

A11P7

A12R2

A13R8

BA0L2

BA1L3

BA2L1

CKEK2

CK_PJ8

CK_NK8

RASK7

CASL7

WEK3

CSL8

DQ0G8

DQ1G2

DQ2H7

DQ3H3

DQ4H1

DQ5H9

DQ6F1

DQ7F9

DQ8C8

DQ9C2

DQ10D7

DQ11D3

DQ12D1

DQ13D9

DQ14B1

DQ15B9

LDQS_PF7

NU/LDQS_NE8

UDQS_PB7

NU/UDQS_NA8

LDMF3

UDMB3

ODTK9

NC1A2 NC2E2 NC3R3 NC4R7

VDD1A1

VDD2E1

VDD3J9

VDD4M9

VDD5R1

VDDQ1A9

VDDQ2C1

VDDQ3C3

VDDQ4C7

VDDQ5C9

VDDQ6E9

VDDQ7G1

VDDQ8G3

VDDQ9G7

VDDQ10G9

VDDLJ1

VREFJ2

VSS1A3

VSS2E3

VSS3J3

VSS4N1

VSS5P9

VSSQ1A7

VSSQ2B2

VSSQ3B8

VSSQ4D2

VSSQ5D8

VSSQ6E7

VSSQ7F2

VSSQ8F8

VSSQ9H2

VSSQ10H8

VSSDLJ7

C94100nFC0402

ATSAMA5D27C-CN

U6E

bga289p8

DDR_A0F12

DDR_A1C17

DDR_A10C15

DDR_A11A16

DDR_A12A17

DDR_A13G11

DDR_A2B17

DDR_A3B16

DDR_A4C16

DDR_A5G14

DDR_A6F14

DDR_A7F11

DDR_A8C14

DDR_A9D13

DDR_BA0H12

DDR_BA1H13

DDR_BA2F17

DDR_CALE13

DDR_CASG12

DDR_CKEF16

DDR_CLKE17

DDR_CLKND17

DDR_CSG13

DDR_D0B12

DDR_D1A12

DDR_D10H17

DDR_D11K17

DDR_D12K16

DDR_D13J13

DDR_D14K14

DDR_D15K15

DDR_D16B8

DDR_D17B9

DDR_D18C9

DDR_D19A9

DDR_D2C12

DDR_D20A10

DDR_D21D10

DDR_D22B11

DDR_D23A11

DDR_D24J12

DDR_D25H10

DDR_D26J11

DDR_D27K11

DDR_D28L13

DDR_D29L11

DDR_D3A13

DDR_D30L12

DDR_D31M17

DDR_D4A14

DDR_D5C13

DDR_D6A15

DDR_D7B15

DDR_D8G17

DDR_D9G16

DDR_DQM0C11

DDR_DQM1G15

DDR_DQM2C8

DDR_DQM3H11

DDR_DQS0B13

DDR_DQS1J17

DDR_DQS2C10

DDR_DQS3L17

DDR_DQSN0B14

DDR_DQSN1J16

DDR_DQSN2B10

DDR_DQSN3L16

DDR_RASF13

DDR_RESETNE16

DDR_VREFCMD16 DDR_VREFB0H16

DDR_WEF15

C62100nFC0402

R29 DNP R0402

C72100nFC0402

U8

W972GG6KB-25bga84-32-1509e

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

A11P7

A12R2

A13R8

BA0L2

BA1L3

BA2L1

CKEK2

CK_PJ8

CK_NK8

RASK7

CASL7

WEK3

CSL8

DQ0G8

DQ1G2

DQ2H7

DQ3H3

DQ4H1

DQ5H9

DQ6F1

DQ7F9

DQ8C8

DQ9C2

DQ10D7

DQ11D3

DQ12D1

DQ13D9

DQ14B1

DQ15B9

LDQS_PF7

NU/LDQS_NE8

UDQS_PB7

NU/UDQS_NA8

LDMF3

UDMB3

ODTK9


VDD1A1

VDD2E1

VDD3J9

VDD4M9

VDD5R1

VDDQ1A9

VDDQ2C1

VDDQ3C3

VDDQ4C7

VDDQ5C9

VDDQ6E9

VDDQ7G1

VDDQ8G3

VDDQ9G7

VDDQ10G9

VDDLJ1

VREFJ2

VSS1A3

VSS2E3

VSS3J3

VSS4N1

VSS5P9

VSSQ1A7

VSSQ2B2

VSSQ3B8

VSSQ4D2

VSSQ5D8

VSSQ6E7

VSSQ7F2

VSSQ8F8

VSSQ9H2

VSSQ10H8

VSSDLJ7

R262.2K-1%R0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 15

The SAMA5D2-PTC-EK is a development kit built on an 8-layer PCB. The board features a SAMA5D27/BGA289 MPU and two 2-Gbit Winbond DDR2-SDRAM devices (Part No.: W972GG6KB-25).

Figure 3-7. SAMA5D2-PTC-EK Layer 1 (Top)




The layout example in the above figure shows the top layer of the board focused on the DDR2-SDRAMrouting. Some of the address signals and the differential clock are present on the top layer, with thementioned trace width and minimum clearance. These values are equal to or above the minimumrequired. There is also a 10 mils clearance between the CK/CKn signals and any other signal, above theminimum required.



Figure 3-8. SAMA5D2-PTC-EK Layer 8 (Bottom)



The layout example in the above figure shows the bottom layer of the DDR2-SDRAM layout. Signals fromtwo data lanes are being routed on the bottom layer, belonging to data lane 2 (D16-D23) and data lane 0(D0-D7), including their respective DQS/DQSn and DQM signals. Trace width used is 5 mils, and theclearance is 10 mils, both values exceeding the minimum required. On very short distances (typically theroute a path needs to take to escape a dense BGA area), the clearance may go slightly below theminimum required. This is acceptable for dense designs only and shall be applied only if no other solutionexists. These signals are also length-matched.



Figure 3-9. SAMA5D2-PTC-EK Layer 5 (VDD)

The above figure shows layer 5 of the board, used as power plane. The highlighted region covers thetraces belonging to the DDR2-SDRAM routing and serves as reference plane for the impedancematching of the signals from layer 6 (see layer stack-up). Also, it contains no splits across any high-speedsignal.

The trace impedance for inner layer 6 (see the figure below), which is used as signal layer, is calculatedusing the impedance formula (according to Standard IPC-2141) for an asymmetric stripline:

Equation 2

Z0(Ω)=80�� 1.9 2�+ �0.8�+ � 1− �4�1

Where εr is the dielectric constant, H1 is the dielectric height below the signal layer, H is the dielectricheight above the signal layer, W is the trace width and T the trace thickness.

In our case (available in Table SAMA5D2-PTC-EK Detailed PCB Stack-up):

• εr = 4.5 for FR-4 dielectric• H1 = 13.8 mils below layer 6• H = 5.12 mils above layer 6• W = 5 mils trace width• T = 1.38 mils copper thickness.

Using the above parameters, the trace impedance is calculated to be Z0 = 48.26 Ω, covered by the ±10%tolerance.

Applying Equation 1 for traces on top or bottom layer, for the above parameters and a dielectric height H= 3.63 mils, results in a near perfect 49.92 Ω trace impedance.



Figure 3-10. SAMA5D2-PTC-EK Layer 6




All trace widths and clearances shown in the above figure are in accordance with the general designrules.



Figure 3-11. SAMA5D2-PTC-EK PCB Stacking

Table 3-2. SAMA5D2-PTC-EK Detailed PCB Stack-up


Thickness[mil]

DielectricMaterial

DielectricConstant


Top Solder SolderMask/Coverlay

SurfaceMaterial






ART03 Signal Copper 0.035052 1.38 – –


PWR04 Signal Copper 0.035052 1.38 – –







Thickness[mil]

DielectricMaterial

DielectricConstant






Bottom Solder SolderMask/Coverlay

SurfaceMaterial


BottomOverlay

Overlay – – – – –

3.3 SAMA5D24/BGA256 Custom Test BoardThis is a custom board solely designed for testing multiple MPU+SDRAM configurations. It features fiveindividual sets of SAMA5D24 MPU paired with 2xDDR3L-SDRAM, 2xDDR2-SDRAM, 2xLPDDR1-SDRAM, 2xLPDDR2-SDRAM and 1xLPDDR3-SDRAM devices. Each set has its own powermanagement integrated circuit (PMIC).

The layer stack-up is shown in the following figure and table. Since all five sets are on the same board,they share the same stack-up.



Figure 3-12. SAMA5D24/BGA256 Custom Test Board Layer Stack-up

Notice the use of blind vias. Considering the very fine 0.4 mm ball pitch of the SAMA5D24, microvias inMPU pads were used. Large through-hole vias were not used in the fan-out of the MPU.

Table 3-3. Detailed Test Board Layer Stack-up

Layer Name Type Material Thickness[mm]Thickness[mil]

DielectricMaterial

DielectricConstant


Top SolderSolderMask/Coverlay

SurfaceMaterial 0.02 0.79 Solder Resist 3.5


Dielectric1 Dielectric Prepreg 0.105 4.13 FR-4 4.5










Layer Name Type Material Thickness[mm]Thickness[mil]

DielectricMaterial

DielectricConstant







Bottom SolderSolderMask/Coverlay

SurfaceMaterial 0.02 0.79 Solder Resist 3.5

BottomOverlay Overlay

– – – – –

3.3.1 SAMA5D24/BGA256/DDR3L-SDRAM Devices



Figure 3-13. MPUx-DRAMX DDR3L SDRAM Device rotatethispage90

A_DDR_D0A_DDR_D1A_DDR_D2A_DDR_D3A_DDR_D4A_DDR_D5A_DDR_D6A_DDR_D7A_DDR_D8A_DDR_D9A_DDR_D10A_DDR_D11A_DDR_D12A_DDR_D13A_DDR_D14A_DDR_D15

A_DDR_D16A_DDR_D17A_DDR_D18A_DDR_D19A_DDR_D20A_DDR_D21A_DDR_D22A_DDR_D23A_DDR_D24A_DDR_D25A_DDR_D26A_DDR_D27A_DDR_D28A_DDR_D29A_DDR_D30A_DDR_D31

A_DDR_A0A_DDR_A1A_DDR_A2A_DDR_A3A_DDR_A4A_DDR_A5A_DDR_A6A_DDR_A7A_DDR_A8A_DDR_A9A_DDR_A10A_DDR_A11A_DDR_A12A_DDR_A13

A_DDR_BA0A_DDR_BA1A_DDR_BA2

A_DDR_RESETN A_DDR_RESETN

A_DDR_CLK+A_DDR_CLK-A_DDR_CKEA_DDR_CSA_DDR_RASA_DDR_CASA_DDR_WE

A_DDR_CLK+A_DDR_CLK-A_DDR_CKEA_DDR_CSxA_DDR_RASA_DDR_CASA_DDR_WE

A_DDR_DQS0-A_DDR_DQS0+


A_DDR_DQS2+A_DDR_DQS2-


A_DDR_DQM1A_DDR_DQM0

A_DDR_DQM3A_DDR_DQM2

A_DDR_VREF

A_DDR_VREF

A_DDR_D0A_DDR_D1A_DDR_D2A_DDR_D3A_DDR_D4A_DDR_D5A_DDR_D6A_DDR_D7A_DDR_D8A_DDR_D9A_DDR_D10A_DDR_D11A_DDR_D12A_DDR_D13A_DDR_D14A_DDR_D15A_DDR_D16A_DDR_D17A_DDR_D18A_DDR_D19A_DDR_D20A_DDR_D21A_DDR_D22A_DDR_D23A_DDR_D24A_DDR_D25A_DDR_D26A_DDR_D27A_DDR_D28A_DDR_D29A_DDR_D30A_DDR_D31

A_DDR_DQM0A_DDR_DQM1A_DDR_DQM2A_DDR_DQM3






A_DDR_BA0A_DDR_BA1

A_DDR_RASA_DDR_CAS

A_DDR_BA2

A_DDR_CSA_DDR_WE

A_DDR_CKE

A_DDR_VREF

A_DDR_RESETN

A_DDR_CLK+A_DDR_CLK-


A_DDR_BA0A_DDR_BA1A_DDR_BA2

A_DDR_VREF

A_DDR_CS

A_DDR_CSx

GND_POWER

GND_POWER GND_POWERGND_POWER GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER GND_POWER

GND_POWER

A_VDD_DRAMA_VDD_DRAM

A_VDD_DRAMA_VDD_DRAM

A_VDD_DRAM

A_VDD_DRAMA_VDD_DRAMA_VDD_DRAM

A_VDD_DRAM

R57100KR0402

R58240R-1%R0402

R51 1K-NC R0402

C115100nFC0402

C91100nFC0402

C8822pFC0402

U5

IS43TR16640B-15GBLBGADDR96p8b90x140

CKJ7

CK#K7

CKEK9

CS#L2

RAS#J3

CAS#K3

WE#L3

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BC#N7

A13T3

A14T7

BA0M2

BA1N8

BA2M3

DQ0E3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

ODTK1

VSS1A9

VSS2B3

VSS3E1

VSS4G8


VSSQ5E2

VDDQ1A1

VDDQ2A8

VDDQ3C1

VDDQ4C9

VDDQ5D2

VDD1B2

VDD2G7

UDQS#B7

UDMD3

LDME7

LDQS#G3

UDQSC7

LDQSF3

DQ8D7

DQ10C8

DQ11C2

DQ14B8

DQ12A7

DQ15A3

DQ13A2

VDD9D9

VSSQ6E8

VDDQ6E9

VDDQ7F1

VSSQ7F9

VSSQ8G1

VSSQ9G9

VREFDQH1

VDDQ8H2

VDDQ9H9

NC1J1

NC2J9

VSS5J2

VSS6J8

VDD4K2

VDD5K8

NC3L1

ZQL8

NC4L9

VSS7M1

A15M7

VREFCAM8

VSS8M9

VDD6N1

VDD7N9

VSS9P1

VSS10P9

VDD8R1

VDD3R9

VSS11T1

RESET#T2

VSS12T9

DQ9C3

U6

IS43TR16640B-15GBLBGADDR96p8b90x140

CKJ7

CK#K7

CKEK9

CS#L2

RAS#J3

CAS#K3

WE#L3

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BC#N7

A13T3

A14T7

BA0M2

BA1N8

BA2M3

DQ0E3

DQ1F7

DQ2F2

DQ3F8

DQ4H3

DQ5H8

DQ6G2

DQ7H7

ODTK1

VSS1A9

VSS2B3

VSS3E1

VSS4G8


VSSQ5E2

VDDQ1A1

VDDQ2A8

VDDQ3C1

VDDQ4C9

VDDQ5D2

VDD1B2

VDD2G7

UDQS#B7

UDMD3

LDME7

LDQS#G3

UDQSC7

LDQSF3

DQ8D7

DQ10C8

DQ11C2

DQ14B8

DQ12A7

DQ15A3

DQ13A2

VDD9D9

VSSQ6E8

VDDQ6E9

VDDQ7F1

VSSQ7F9

VSSQ8G1

VSSQ9G9

VREFDQH1

VDDQ8H2

VDDQ9H9

NC1J1

NC2J9

VSS5J2

VSS6J8

VDD4K2

VDD5K8

NC3L1

ZQL8

NC4L9

VSS7M1

A15M7

VREFCAM8

VSS8M9

VDD6N1

VDD7N9

VSS9P1

VSS10P9

VDD8R1

VDD3R9

VSS11T1

RESET#T2

VSS12T9

DQ9C3

C90100nFC0402

C92100nFC0402

SAMA5D24_BGA256

U4E

TFBGA256_0p4_8x8mm

DDR_A0D17

DDR_A1A17

DDR_A10H11

DDR_A11J10

DDR_A12D15

DDR_A13J11

DDR_A2A18

DDR_A3F15

DDR_A4G12

DDR_A5H12

DDR_A6F13

DDR_A7H10

DDR_A8A16

DDR_A9E12

DDR_BA0H13

DDR_BA1K12

DDR_BA2H17

DDR_CALG17

DDR_CASE17

DDR_CKEF18

DDR_CLKC18

DDR_CLKNC17

DDR_CSJ12

DDR_D0B12

DDR_D1B13

DDR_D10J13

DDR_D11H15

DDR_D12J15

DDR_D13J14

DDR_D14K13

DDR_D15K18

DDR_D16A8

DDR_D17B9

DDR_D18D9

DDR_D19A9

DDR_D2D13

DDR_D20B11

DDR_D21D10

DDR_D22A11

DDR_D23A12

DDR_D24L18

DDR_D25K15

DDR_D26K14

DDR_D27M18

DDR_D28N17

DDR_D29M14

DDR_D3A13

DDR_D30M15

DDR_D31N18

DDR_D4A15

DDR_D5D14

DDR_D6B15

DDR_D7B16

DDR_D8G18

DDR_D9K17

DDR_DQM0D11

DDR_DQM1H14

DDR_DQM2B8

DDR_DQM3L13

DDR_DQS0A14

DDR_DQS1H18

DDR_DQS2A10

DDR_DQS3M17

DDR_DQSN0B14

DDR_DQSN1J18

DDR_DQSN2B10

DDR_DQSN3L17

DDR_RASE18

DDR_RESETNF17

DDR_VREFCMD12 DDR_VREFB0J17

DDR_WED18

C954.7uFC0603

JP3Header 1X2h2p20

12

R53 0R R0402

R60240R-1%R0402

R37210KR0402

R612.2K-1%R0402

R54 0R R0402

R5622K-1%R0402

R622.2K-1%R0402

C93100nFC0402C96100nF

C0402

C89100nFC0402

R52 1K-NC R0402

C94100nFC0402

R55100KR0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 24

This set features a SAMA5D24/BGA256 MPU and two 1-Gbit ISSI DDR3L-SDRAM devices (Part No.:IS43TR16640B-15GBL).

Figure 3-14. SAMA5D24/BGA256/DDR3L-SDRAM Layer 3

Address/control/command signalsTrace width = 5 milsTrace clearance = 6 mils




Traces with 3 mils width/clearance

The layout example in the above figure shows layer 3 of the test board focused on the DDR3L-SDRAMconfiguration. It is used as a signal layer and contains traces for data lane 0..2 and address/control/command signals. Trace width and clearance are in accordance with the minimum required for most ofthese signals. There are, however, exceptions in the region underneath the MPU, where the 0.4 mm ballpitch does not allow routing of traces wider than 3 mils. In this case, we must violate the 4 mils minimumwidth rule due to physical constraints.




Layer 5 of the test board serves as power plane and is also used as impedance matching reference forthe neighboring signal layers (layers 4 and 6). The highlighted region shown in the above figure powersthe SDRAM device. It covers a large surface and it does not feature any splits over any high-speedsignal, in order to ensure a good signal integrity.





DQS3/DQS3nTrace width = 4 milsTrace clearance = 8 mils

Layer 6 contains signals (see the above figure) belonging to data lane 3. All traces belonging to data lane3 are tightly matched, with a mismatch of only 15 mils.

To calculate the trace impedance for differential signals located in inner layers, like the DQS/DQSn pair,we recommend using impedance calculators/solvers to speed up the design process. For maximumaccuracy, make sure that these tools are in accordance with the IPC-2141 standard.

Using the parameters from Table Detailed Test Board Layer Stack-up, and having the trace width of 4mils and 8 mils clearance, the trace impedance of differential pair DQS3/DQS3n is calculated to be 94.83Ω, which is within tolerance.

In the same manner, the CK/CKn differential clock trace impedance can be calculated. The clock signal isrouted on the top layer (see the figure below), has a 4 mils width, an 8 mils clearance and 4.13 milsdielectric height, resulting in a 101.73 Ω impedance.



Figure 3-17. SAMA5D24/BGA256/DDR3L-SDRAM Layer 1 (Top)


3.3.2 SAMA5D24/BGA256/DDR2-SDRAM Devices



Figure 3-18. MPUx-DRAMx DDR2 Device rotatethispage90

B_DDR_A10B_DDR_A11

B_DDR_DQM0

B_DDR_DQM2B_DDR_DQM3

B_DDR_DQM1

B_DDR_DQS0+B_DDR_DQS0-




B_DDR_BA1B_DDR_BA0

B_DDR_CASB_DDR_RAS

B_DDR_CSB_DDR_WE

B_DDR_CKE

B_DDR_CLK+B_DDR_CLK-

B_DDR_VREF

B_DDR_VREF

B_DDR_RESETN

B_DDR_A0B_DDR_A1B_DDR_A2B_DDR_A3B_DDR_A4B_DDR_A5B_DDR_A6B_DDR_A7B_DDR_A8B_DDR_A9

B_DDR_A12

B_DDR_A10B_DDR_A11


B_DDR_A12

B_DDR_A10B_DDR_A11


B_DDR_A12

B_DDR_D0B_DDR_D1B_DDR_D2B_DDR_D3B_DDR_D4B_DDR_D5B_DDR_D6B_DDR_D7B_DDR_D8B_DDR_D9B_DDR_D10B_DDR_D11B_DDR_D12B_DDR_D13B_DDR_D14B_DDR_D15B_DDR_D16B_DDR_D17B_DDR_D18B_DDR_D19B_DDR_D20B_DDR_D21B_DDR_D22B_DDR_D23B_DDR_D24B_DDR_D25B_DDR_D26B_DDR_D27B_DDR_D28B_DDR_D29B_DDR_D30B_DDR_D31

B_DDR_D0B_DDR_D1B_DDR_D2B_DDR_D3B_DDR_D4B_DDR_D5B_DDR_D6B_DDR_D7B_DDR_D8B_DDR_D9B_DDR_D10B_DDR_D11B_DDR_D12B_DDR_D13B_DDR_D14B_DDR_D15

B_DDR_D16

B_DDR_D18B_DDR_D17

B_DDR_D19B_DDR_D20B_DDR_D21B_DDR_D22B_DDR_D23B_DDR_D24B_DDR_D25B_DDR_D26B_DDR_D27B_DDR_D28B_DDR_D29B_DDR_D30B_DDR_D31

B_DDR_BA1B_DDR_BA0

B_DDR_BA1B_DDR_BA0

B_DDR_WE B_DDR_WEB_DDR_CSxB_DDR_CS

B_DDR_CLK-B_DDR_CLK+

B_DDR_CLK-B_DDR_CLK+

B_DDR_CKE B_DDR_CKE

B_DDR_CASB_DDR_RAS

B_DDR_CASB_DDR_RAS

B_DDR_VREFB_DDR_VREF



B_DDR_DQS0-B_DDR_DQS0+


B_DDR_DQS2+B_DDR_DQS2-B_DDR_DQS3+B_DDR_DQS3-

B_DDR_CS

B_DDR_CSx

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

B_VDD_DRAM

B_VDD_DRAM

GND_POWER

GND_POWER

B_VDD_DRAMGND_POWER

B_VDD_DRAM

GND_POWER

GND_POWER

B_VDD_DRAMGND_POWER

B_VDD_DRAM

GND_POWER

B_VDD_DRAM

SAMA5D24_BGA256

U9E

TFBGA256_0p4_8x8mm

DDR_A0D17

DDR_A1A17

DDR_A10H11

DDR_A11J10

DDR_A12D15

DDR_A13J11

DDR_A2A18

DDR_A3F15

DDR_A4G12

DDR_A5H12

DDR_A6F13

DDR_A7H10

DDR_A8A16

DDR_A9E12

DDR_BA0H13

DDR_BA1K12

DDR_BA2H17

DDR_CALG17

DDR_CASE17

DDR_CKEF18

DDR_CLKC18

DDR_CLKNC17

DDR_CSJ12

DDR_D0B12

DDR_D1B13

DDR_D10J13

DDR_D11H15

DDR_D12J15

DDR_D13J14

DDR_D14K13

DDR_D15K18

DDR_D16A8

DDR_D17B9

DDR_D18D9

DDR_D19A9

DDR_D2D13

DDR_D20B11

DDR_D21D10

DDR_D22A11

DDR_D23A12

DDR_D24L18

DDR_D25K15

DDR_D26K14

DDR_D27M18

DDR_D28N17

DDR_D29M14

DDR_D3A13

DDR_D30M15

DDR_D31N18

DDR_D4A15

DDR_D5D14

DDR_D6B15

DDR_D7B16

DDR_D8G18

DDR_D9K17

DDR_DQM0D11

DDR_DQM1H14

DDR_DQM2B8

DDR_DQM3L13

DDR_DQS0A14

DDR_DQS1H18

DDR_DQS2A10

DDR_DQS3M17

DDR_DQSN0B14

DDR_DQSN1J18

DDR_DQSN2B10

DDR_DQSN3L17

DDR_RASE18

DDR_RESETNF17


DDR_WED18

JP6Header 1X2h2p20

12

C210100nFC0402

U11

IS43DR16320Ebga84-32-1509e

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

A11P7

A12R2

A13R8

BA0L2

BA1L3

BA2L1

CKEK2

CK_PJ8

CK_NK8

RASK7

CASL7

WEK3

CSL8

DQ0G8

DQ1G2

DQ2H7

DQ3H3

DQ4H1

DQ5H9

DQ6F1

DQ7F9

DQ8C8

DQ9C2

DQ10D7

DQ11D3

DQ12D1

DQ13D9

DQ14B1

DQ15B9

LDQS_PF7

NU/LDQS_NE8

UDQS_PB7

NU/UDQS_NA8

LDMF3

UDMB3

ODTK9


VDD1A1

VDD2E1

VDD3J9

VDD4M9

VDD5R1

VDDQ1A9

VDDQ2C1

VDDQ3C3

VDDQ4C7

VDDQ5C9

VDDQ6E9

VDDQ7G1

VDDQ8G3

VDDQ9G7

VDDQ10G9

VDDLJ1

VREFJ2

VSS1A3

VSS2E3

VSS3J3

VSS4N1

VSS5P9

VSSQ1A7

VSSQ2B2

VSSQ3B8

VSSQ4D2

VSSQ5D8

VSSQ6E7

VSSQ7F2

VSSQ8F8

VSSQ9H2

VSSQ10H8

VSSDLJ7

R1332.2K-1%R0402

C209100nFC0402

R129100KR0402

R37310KR0402

R125 1K-NC R0402

U10

IS43DR16320Ebga84-32-1509e

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

A11P7

A12R2

A13R8

BA0L2

BA1L3

BA2L1

CKEK2

CK_PJ8

CK_NK8

RASK7

CASL7

WEK3

CSL8

DQ0G8

DQ1G2

DQ2H7

DQ3H3

DQ4H1

DQ5H9

DQ6F1

DQ7F9

DQ8C8

DQ9C2

DQ10D7

DQ11D3

DQ12D1

DQ13D9

DQ14B1

DQ15B9

LDQS_PF7

NU/LDQS_NE8

UDQS_PB7

NU/UDQS_NA8

LDMF3

UDMB3

ODTK9


VDD1A1

VDD2E1

VDD3J9

VDD4M9

VDD5R1

VDDQ1A9

VDDQ2C1

VDDQ3C3

VDDQ4C7

VDDQ5C9

VDDQ6E9

VDDQ7G1

VDDQ8G3

VDDQ9G7

VDDQ10G9

VDDLJ1

VREFJ2

VSS1A3

VSS2E3

VSS3J3

VSS4N1

VSS5P9

VSSQ1A7

VSSQ2B2

VSSQ3B8

VSSQ4D2

VSSQ5D8

VSSQ6E7

VSSQ7F2

VSSQ8F8

VSSQ9H2

VSSQ10H8

VSSDLJ7

C2111nFC0402

R126 1K-NC R0402

C212100nFC0402

R131DNPR0402

C2264.7uFC0603

C20722pFC0402

R1342.2K-1%R0402

C2131nFC0402

R128 0R R0402R127 0R R0402

C228100nFC0402

C208100nFC0402

C227100nFC0402

R13021K-1%R0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 29

This set features a SAMA5D24/BGA256 MPU and two 512-Mbit ISSI DDR2-SDRAM devices (Part No.:IS43DR16320E-25DBL).

Figure 3-19. SAMA5D24/BGA256/DDR2-SDRAM Layer 3

Address/control/commandsignalsTrace width = 5 milsTrace clearance = 6 mils




Traces with 3-mil width/clearance

The above figure shows layer 3 of the test board focused on the DDR2-SDRAM configuration. It is usedas a signal layer, contains traces for data lane 0..2 and address/control/command signals. Trace widthand clearance are in accordance with the minimum required for most of these signals. There are,however, exceptions in the region underneath the MPU, where the 0.4 mm ball pitch did not allow to routetraces wider than 3 mils or a larger than 3 mils clearance. In this case we must violate the 4 mils minimumwidth rule due to physical constraints.







To calculate the trace impedance for differential signals located in inner layers, like the DQS/DQSn pair,we recommend using impedance calculators/solvers to speed up the design process. For maximumaccuracy, make sure that these tools are in accordance with the IPC-2141 standard.

Using the parameters from Table Detailed Test Board Layer Stack-up, and having the trace width of 4mils and 8 mils clearance, the trace impedance of differential pair DQS3/DQS3n is calculated to be 94.83Ω, which is within tolerance.

In the same manner, the CK/CKn differential clock trace impedance can be calculated. The clock signal isrouted on the top layer (see the figure below), has a 4 mils width, an 8 mils clearance and a 4.13 milsdielectric height, resulting in a 101.73 Ω impedance.



Figure 3-22. SAMA5D24/BGA256/DDR2-SDRAM Layer 1 (Top)

CK/CKnTrace width = 4 milsTrace clearance = 8 mils

3.3.3 SAMA5D24/BGA256/LPDDR1-SDRAM Devices



Figure 3-23. MPUx-DRAMx LPDDR1 Device rotatethispage90

C_DDR_A10C_DDR_A11

C_DDR_DQM0

C_DDR_DQM2C_DDR_DQM3

C_DDR_DQM1

C_DDR_DQS0+C_DDR_VREF

C_DDR_DQS1+

C_DDR_DQS2+

C_DDR_DQS3+

C_DDR_BA1C_DDR_BA0

C_DDR_CASC_DDR_RAS

C_DDR_CSC_DDR_WE

C_DDR_CKE

C_DDR_CLK+C_DDR_CLK-

C_DDR_VREF

C_DDR_VREF

C_DDR_RESETN

C_DDR_D0C_DDR_D1C_DDR_D2C_DDR_D3C_DDR_D4C_DDR_D5C_DDR_D6C_DDR_D7C_DDR_D8C_DDR_D9C_DDR_D10C_DDR_D11C_DDR_D12C_DDR_D13C_DDR_D14C_DDR_D15C_DDR_D16C_DDR_D17C_DDR_D18C_DDR_D19C_DDR_D20C_DDR_D21C_DDR_D22C_DDR_D23C_DDR_D24C_DDR_D25C_DDR_D26C_DDR_D27C_DDR_D28C_DDR_D29C_DDR_D30C_DDR_D31

C_DDR_A0C_DDR_A1C_DDR_A2C_DDR_A3C_DDR_A4C_DDR_A5C_DDR_A6C_DDR_A7C_DDR_A8C_DDR_A9



C_DDR_DQS0+C_DDR_DQS1+

C_DDR_DQS2+C_DDR_DQS3+

C_DDR_D0C_DDR_D1C_DDR_D2C_DDR_D3C_DDR_D4C_DDR_D5C_DDR_D6C_DDR_D7C_DDR_D8C_DDR_D9C_DDR_D10C_DDR_D11C_DDR_D12C_DDR_D13C_DDR_D14C_DDR_D15

C_DDR_D16

C_DDR_D18C_DDR_D17

C_DDR_D19C_DDR_D20C_DDR_D21C_DDR_D22C_DDR_D23C_DDR_D24C_DDR_D25C_DDR_D26C_DDR_D27C_DDR_D28C_DDR_D29C_DDR_D30C_DDR_D31

C_DDR_A12

C_DDR_A10C_DDR_A11


C_DDR_A12

C_DDR_A10C_DDR_A11


C_DDR_A12

C_DDR_BA1C_DDR_BA0

C_DDR_BA1C_DDR_BA0

C_DDR_WE C_DDR_WE

C_DDR_CS C_DDR_CSx

C_DDR_CASC_DDR_RAS

C_DDR_CASC_DDR_RAS

C_DDR_CKE


C_DDR_CKE


C_DDR_CS

C_DDR_CSx

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

C_VDD_DRAM

C_VDD_DRAM

GND_POWER

C_VDD_DRAM

GND_POWER

C_VDD_DRAM

C_VDD_DRAM

C334100nFC0402

U15

IS43LR16160Gbgalpddr60p8b80x100

A0J8

A1J9

A2K7

A3K8

A4K2

A5K3

A6J1

A7J2

A8J3

A9H1

A10J7

A11H2

A12H3

DQ0A8

DQ1B7

DQ2B8

DQ3C7

DQ4C8

DQ5D7

DQ6D8

DQ7E7

DQ8E3

DQ9D2

DQ10D3

DQ11C2

DQ12C3

DQ13B2

DQ14B3

DQ15A2

LDQSE8

UDQSE2

LDMF8

UDMF2

CKG2

CK#G3

WE#G7

CAS#G8

RAS#G9

CS#H7

CKEG1

VSS1A1

VSS2F1

VSS3K1

VSSQ1A3

VSSQ2C1

VSSQ3B9

VSSQ4D9

VSSQ5E1

VDD1A9

VDD2F9

VDD3K9

VDDQ1B1

VDDQ2D1

VDDQ3A7

VDDQ4C9

VDDQ5E9

NC1F3

NC2F7

BA0H8

BA1H9

C315100nFC0402 C335

100nFC0402

R19821K-1%R0402

SAMA5D24_BGA256

U14E

TFBGA256_0p4_8x8mm

DDR_A0D17

DDR_A1A17

DDR_A10H11

DDR_A11J10

DDR_A12D15

DDR_A13J11

DDR_A2A18

DDR_A3F15

DDR_A4G12

DDR_A5H12

DDR_A6F13

DDR_A7H10

DDR_A8A16

DDR_A9E12

DDR_BA0H13

DDR_BA1K12

DDR_BA2H17

DDR_CALG17

DDR_CASE17

DDR_CKEF18

DDR_CLKC18

DDR_CLKNC17

DDR_CSJ12

DDR_D0B12

DDR_D1B13

DDR_D10J13

DDR_D11H15

DDR_D12J15

DDR_D13J14

DDR_D14K13

DDR_D15K18

DDR_D16A8

DDR_D17B9

DDR_D18D9

DDR_D19A9

DDR_D2D13

DDR_D20B11

DDR_D21D10

DDR_D22A11

DDR_D23A12

DDR_D24L18

DDR_D25K15

DDR_D26K14

DDR_D27M18

DDR_D28N17

DDR_D29M14

DDR_D3A13

DDR_D30M15

DDR_D31N18

DDR_D4A15

DDR_D5D14

DDR_D6B15

DDR_D7B16

DDR_D8G18

DDR_D9K17

DDR_DQM0D11

DDR_DQM1H14

DDR_DQM2B8

DDR_DQM3L13

DDR_DQS0A14

DDR_DQS1H18

DDR_DQS2A10

DDR_DQS3M17

DDR_DQSN0B14

DDR_DQSN1J18

DDR_DQSN2B10

DDR_DQSN3L17

DDR_RASE18

DDR_RESETNF17


DDR_WED18

R197100KR0402

R2012.2K-1%R0402

R37410KR0402

U16

IS43LR16160Gbgalpddr60p8b80x100

A0J8

A1J9

A2K7

A3K8

A4K2

A5K3

A6J1

A7J2

A8J3

A9H1

A10J7

A11H2

A12H3

DQ0A8

DQ1B7

DQ2B8

DQ3C7

DQ4C8

DQ5D7

DQ6D8

DQ7E7

DQ8E3

DQ9D2

DQ10D3

DQ11C2

DQ12C3

DQ13B2

DQ14B3

DQ15A2

LDQSE8

UDQSE2

LDMF8

UDMF2

CKG2

CK#G3

WE#G7

CAS#G8

RAS#G9

CS#H7

CKEG1

VSS1A1

VSS2F1

VSS3K1

VSSQ1A3

VSSQ2C1

VSSQ3B9

VSSQ4D9

VSSQ5E1

VDD1A9

VDD2F9

VDD3K9

VDDQ1B1

VDDQ2D1

VDDQ3A7

VDDQ4C9

VDDQ5E9

NC1F3

NC2F7

BA0H8

BA1H9

C316100nFC0402

C3334.7uFC0603

R199DNPR0402

JP9Header 1X2h2p20

12

C31422pFC0402

R2022.2K-1%R0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 34

This set features a SAMA5D24/BGA256 MPU and two 256-Mbit ISSI LPDDR1-SDRAM devices (PartNo.: IS43LR16160G-6BLI).

Figure 3-24. SAMA5D24/BGA256/LPDDR1-SDRAM Layer 6


The layout example in the above figure shows layer 6 of the layout centered on the LPDDR1-SDRAM set.On this layer, the data lane 3 (D24-D31) signals have been routed, with the commented trace width andclearance, in accordance with the general routing rules. The route length mismatch within the data lane is17 mils, well below the maximum 50 mils mismatch.



Figure 3-25. SAMA5D24/BGA256/LPDDR1-SDRAM Layer 8 (Bottom)




The above figure shows the bottom layer of the test board, centered on the LPDDR1-SDRAM device withthe indicated trace width and clearance.




D_DDR_DQM0

D_DDR_DQM2D_DDR_DQM3

D_DDR_DQM1

D_DDR_DQS0+D_DDR_DQS0-




D_DDR_CS

D_DDR_CKE

D_DDR_CLK+D_DDR_CLK-

D_DDR_VREF

D_DDR_VREF

D_DDR_RESETN

D_DDR_D0D_DDR_D1D_DDR_D2D_DDR_D3D_DDR_D4D_DDR_D5D_DDR_D6D_DDR_D7D_DDR_D8D_DDR_D9D_DDR_D10D_DDR_D11D_DDR_D12D_DDR_D13D_DDR_D14D_DDR_D15D_DDR_D16D_DDR_D17D_DDR_D18D_DDR_D19D_DDR_D20D_DDR_D21D_DDR_D22D_DDR_D23D_DDR_D24D_DDR_D25D_DDR_D26D_DDR_D27D_DDR_D28D_DDR_D29D_DDR_D30D_DDR_D31

D_DDR_A0D_DDR_A1D_DDR_A2D_DDR_A3D_DDR_A4D_DDR_A5D_DDR_A6







D_DDR_DQS3-D_DDR_DQS3+D_DDR_DQS2-D_DDR_DQS2+

D_DDR_D0D_DDR_D1D_DDR_D2D_DDR_D3D_DDR_D4D_DDR_D5D_DDR_D6D_DDR_D7D_DDR_D8D_DDR_D9D_DDR_D10D_DDR_D11D_DDR_D12D_DDR_D13D_DDR_D14D_DDR_D15

D_DDR_D16

D_DDR_D18D_DDR_D17

D_DDR_D19D_DDR_D20D_DDR_D21D_DDR_D22D_DDR_D23D_DDR_D24D_DDR_D25D_DDR_D26D_DDR_D27D_DDR_D28D_DDR_D29D_DDR_D30D_DDR_D31

D_DDR_VREFD_DDR_VREF

D_DDR_CS

D_DDR_CKE

D_DDR_CSx

D_DDR_CKE

D_DDR_A1D_DDR_A0

D_DDR_A4D_DDR_A3D_DDR_A2

D_DDR_A6D_DDR_A5

D_DDR_A1D_DDR_A0

D_DDR_A4D_DDR_A3D_DDR_A2

D_DDR_A6D_DDR_A5

D_DDR_RASD_DDR_CASD_DDR_WE

D_DDR_RASD_DDR_CASD_DDR_WE

D_DDR_RASD_DDR_CAS

D_DDR_WE

D_DDR_CS

D_DDR_CSx

D_VDD18_LPDDR2

D_VDD_DRAMGND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

D_VDD_DRAM

D_VDD_DRAM

D_VDD18_LPDDR2

GND_POWER GND_POWER

GND_POWER GND_POWER

GND_POWER GND_POWER

D_VDD_DRAM

D_VDD_DRAM

C414100nFC0402

C419100nFC0402

R26624K-1%R0402

C422100nFC0402

R265100KR0402

C417100nFC0402

R269240R-1%R0402

R2712.2K-1%R0402

C415100nFC0402

R268240R-1%R0402

U20

bgalpddr134p65b100x115IS43LD16320A

CA0P3

CA1N3

CA2M3

CA3M2

CA4M1

CA5G2

CA6F2

CA7F3

CA8E3

CA9E2

DQ0N8

DQ1M8

DQ2M7

DQ3M9

DQ4M6

DQ5L7

DQ6L8

DQ7L9

DQ8G9

DQ9G8

DQ10G7

DQ11F6

DQ12F9

DQ13F7

DQ14F8

DQ15E8

DQS0_tL6

DQS0_cL5

DQS1_tG6

DQS1_cG5

DM0K5

DM1H5

NC0A1

NC1A2

NC2A9

NC3A10

NC4B1

NC5B2

NC6B3

NC7B7

NC8B8

NC9B9

NC10B10

NC11C3

NC12C8

NC13D6

NC14D7

NC15D8

NC16D9

NC17E5

NC18E6

NC19E7

NC20J2

NC21K2

NC22K3

NC23L2

NC24L3

NC25N5

NC26N6

NC27N7

NC28P6

NC29P7

NC30P8

NC31P9

NC32R3

NC33R8

NC34T1

NC35T2

NC36T3

NC37T7

NC38T8

NC39T9

NC40T10

NC41U1

NC42U2

NC43U9

NC44U10

VDD1_0B6

VDD1_1C1

VDD1_2R1

VDD1_3T6

VDD2_0B5

VDD2_1D2

VDD2_2G1

VDD2_3J7

VDD2_4P2

VDD2_5T5

VDDCA_0F1

VDDCA_1H1

VDDCA_2N2

VDDQ_0C7

VDDQ_1C10

VDDQ_2D5

VDDQ_3E9

VDDQ_4F10

VDDQ_5H6

VDDQ_6J6

VDDQ_7K6

VDDQ_8M10

VDDQ_9N9

VDDQ_10P5

VDDQ_11R7

VSS_0C2

VSS_1C5

VSS_2D1

VSS_3H2

VSS_4J8

VSS_5P1

VSS_6R2

VSS_7R5

VSSCA_0E1

VSSCA_1J1

VSSQ_0C6

VSSQ_1C9

VSSQ_2D10

VSSQ_3E10

VSSQ_4F5

VSSQ_5G10

VSSQ_6J5

VSSQ_7L10

VSSQ_8M5

VSSQ_9N10

VSSQ_10P10

VSSQ_11R6

ZQD3

VREFCAG3

CK_tJ3

CK_cH3

CS0_nL1

CKE0K1

VREFDQJ9

VDDQ_12R10

VSSCA_2N1

VSSQ_12R9

C4204.7uFC0603

R37510KR0402

R267DNPR0402

SAMA5D24_BGA256

U19E

TFBGA256_0p4_8x8mm

DDR_A0D17

DDR_A1A17

DDR_A10H11

DDR_A11J10

DDR_A12D15

DDR_A13J11

DDR_A2A18

DDR_A3F15

DDR_A4G12

DDR_A5H12

DDR_A6F13

DDR_A7H10

DDR_A8A16

DDR_A9E12

DDR_BA0H13

DDR_BA1K12

DDR_BA2H17

DDR_CALG17

DDR_CASE17

DDR_CKEF18

DDR_CLKC18

DDR_CLKNC17

DDR_CSJ12

DDR_D0B12

DDR_D1B13

DDR_D10J13

DDR_D11H15

DDR_D12J15

DDR_D13J14

DDR_D14K13

DDR_D15K18

DDR_D16A8

DDR_D17B9

DDR_D18D9

DDR_D19A9

DDR_D2D13

DDR_D20B11

DDR_D21D10

DDR_D22A11

DDR_D23A12

DDR_D24L18

DDR_D25K15

DDR_D26K14

DDR_D27M18

DDR_D28N17

DDR_D29M14

DDR_D3A13

DDR_D30M15

DDR_D31N18

DDR_D4A15

DDR_D5D14

DDR_D6B15

DDR_D7B16

DDR_D8G18

DDR_D9K17

DDR_DQM0D11

DDR_DQM1H14

DDR_DQM2B8

DDR_DQM3L13

DDR_DQS0A14

DDR_DQS1H18

DDR_DQS2A10

DDR_DQS3M17

DDR_DQSN0B14

DDR_DQSN1J18

DDR_DQSN2B10

DDR_DQSN3L17

DDR_RASE18

DDR_RESETNF17


DDR_WED18

R2722.2K-1%R0402

C41322pFC0402

C418100nFC0402

JP13Header 1X2h2p20

12

U21

bgalpddr134p65b100x115IS43LD16320A

CA0P3

CA1N3

CA2M3

CA3M2

CA4M1

CA5G2

CA6F2

CA7F3

CA8E3

CA9E2

DQ0N8

DQ1M8

DQ2M7

DQ3M9

DQ4M6

DQ5L7

DQ6L8

DQ7L9

DQ8G9

DQ9G8

DQ10G7

DQ11F6

DQ12F9

DQ13F7

DQ14F8

DQ15E8

DQS0_tL6

DQS0_cL5

DQS1_tG6

DQS1_cG5

DM0K5

DM1H5

NC0A1

NC1A2

NC2A9

NC3A10

NC4B1

NC5B2

NC6B3

NC7B7

NC8B8

NC9B9

NC10B10

NC11C3

NC12C8

NC13D6

NC14D7

NC15D8

NC16D9

NC17E5

NC18E6

NC19E7

NC20J2

NC21K2

NC22K3

NC23L2

NC24L3

NC25N5

NC26N6

NC27N7

NC28P6

NC29P7

NC30P8

NC31P9

NC32R3

NC33R8

NC34T1

NC35T2

NC36T3

NC37T7

NC38T8

NC39T9

NC40T10

NC41U1

NC42U2

NC43U9

NC44U10

VDD1_0B6

VDD1_1C1

VDD1_2R1

VDD1_3T6

VDD2_0B5

VDD2_1D2

VDD2_2G1

VDD2_3J7

VDD2_4P2

VDD2_5T5

VDDCA_0F1

VDDCA_1H1

VDDCA_2N2

VDDQ_0C7

VDDQ_1C10

VDDQ_2D5

VDDQ_3E9

VDDQ_4F10

VDDQ_5H6

VDDQ_6J6

VDDQ_7K6

VDDQ_8M10

VDDQ_9N9

VDDQ_10P5

VDDQ_11R7

VSS_0C2

VSS_1C5

VSS_2D1

VSS_3H2

VSS_4J8

VSS_5P1

VSS_6R2

VSS_7R5

VSSCA_0E1

VSSCA_1J1

VSSQ_0C6

VSSQ_1C9

VSSQ_2D10

VSSQ_3E10

VSSQ_4F5

VSSQ_5G10

VSSQ_6J5

VSSQ_7L10

VSSQ_8M5

VSSQ_9N10

VSSQ_10P10

VSSQ_11R6

ZQD3

VREFCAG3

CK_tJ3

CK_cH3

CS0_nL1

CKE0K1

VREFDQJ9

VDDQ_12R10

VSSCA_2N1

VSSQ_12R9

C421100nFC0402

C416100nFC0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 38

This set features a SAMA5D24/BGA256 MPU and two 512-Mbit ISSI LPDDR2-SDRAM devices (PartNo.: IS43LD16320A-25BLI).


Traces with 3-milwidth/clearance


Address/control/commandsignalsTrace width = 5 milsTrace clearance = 7 mils



The above figure shows layer 3 of the test board focused on the LPDDR2-SDRAM configuration. It isused as a signal layer, contains traces for data lane 0..2 and address/control/command signals. Tracewidth and clearance are in accordance with the minimum required for most of these signals. There are,however, exceptions in the region underneath the MPU, where the 0.4 mm ball pitch does not allow toroute traces wider than 3 mils or a larger than 3 mils clearance. In this case, we must violate the 4 milsminimum width rule due to physical constraints.







To calculate the trace impedance for differential signals located in inner layers, like the DQS/DQSn pair,impedance calculators/solvers are recommended to be used to speed up the design process. Formaximum accuracy, make sure that these tools are in accordance with the IPC-2141 standard.

Using the parameters from Table Detailed Test Board Layer Stack-up, and having the trace width of 4mils and a 8 mils clearance, results for differential pair DQS3/DQS3n in a trace impedance of 94.83 Ω,which is within tolerance.

In the same manner, the CK/CKn differential clock trace impedance can be calculated. The clock signal isrouted on the top layer (see Figure SAMA5D24/BGA256/DDR2-SDRAM Layer 1 (Top)), has a 4 milswidth, 8 mils clearance and 4.13 mils dielectric height, resulting in a 101.73 Ω impedance.





E_DDR_D0E_DDR_D1E_DDR_D2E_DDR_D3E_DDR_D4E_DDR_D5E_DDR_D6E_DDR_D7E_DDR_D8E_DDR_D9E_DDR_D10E_DDR_D11E_DDR_D12E_DDR_D13E_DDR_D14E_DDR_D15E_DDR_D16E_DDR_D17E_DDR_D18E_DDR_D19E_DDR_D20E_DDR_D21E_DDR_D22E_DDR_D23E_DDR_D24E_DDR_D25E_DDR_D26E_DDR_D27E_DDR_D28E_DDR_D29E_DDR_D30E_DDR_D31

E_DDR_A0E_DDR_A1E_DDR_A2E_DDR_A3E_DDR_A4E_DDR_A5E_DDR_A6

E_DDR_D0E_DDR_D1E_DDR_D2E_DDR_D3E_DDR_D4E_DDR_D5E_DDR_D6E_DDR_D7E_DDR_D8E_DDR_D9E_DDR_D10E_DDR_D11E_DDR_D12E_DDR_D13E_DDR_D14E_DDR_D15E_DDR_D16E_DDR_D17E_DDR_D18E_DDR_D19E_DDR_D20E_DDR_D21E_DDR_D22E_DDR_D23E_DDR_D24E_DDR_D25E_DDR_D26E_DDR_D27E_DDR_D28E_DDR_D29E_DDR_D30E_DDR_D31

E_DDR_DQM0

E_DDR_DQM2E_DDR_DQM3

E_DDR_DQM1

E_DDR_DQS0+E_DDR_DQS0-




E_DDR_DQM0

E_DDR_DQM2E_DDR_DQM3

E_DDR_DQM1

E_DDR_DQS0-E_DDR_DQS0+




E_DDR_CS

E_DDR_CKE

E_DDR_CLK+E_DDR_CLK-

E_DDR_VREF

E_DDR_RESETN

E_DDR_CLK+E_DDR_CLK-

E_DDR_CKE

E_DDR_CS

E_DDR_VREF

E_DDR_VREF

E_DDR_A0E_DDR_A1E_DDR_A2E_DDR_A3E_DDR_A4E_DDR_A5E_DDR_A6

E_DDR_RASE_DDR_CASE_DDR_WE

E_DDR_RASE_DDR_CAS

E_DDR_WE

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

GND_POWER

E_VDD18_LPDDR3

GND_POWER

GND_POWER

GND_POWER

E_VDD_DRAM

E_VDD_DRAM

E_VDD_DRAM

E_VDD_DRAM

C534100nFC0402

C531100nFC0402

MT52L256M32D1PF-107WT

U25B

bgalpddr178p8b110x115

VDD1_0A3

VDD1_1A4

VDD1_2A5

VDD1_3A6

VDD1_4U3

VDD1_5U4

VDD1_6U5

VDD1_7U6

VDD1_8A10

VDD1_9U10

VDD2_0D4

VDD2_1D5

VDD2_2D6

VDD2_3G5

VDD2_4H5

VDD2_5H6

VDD2_6J5

VDD2_7J6

VDD2_8K5

VDD2_9K6

VDD2_10L5

VDD2_11P4

VDD2_12P5

VDD2_13P6

VDD2_14A8

VDD2_15A9

VDD2_16H12

VDD2_17K12

VDD2_18U8

VDD2_19U9

VDDQ_0A11

VDDQ_1C12

VDDQ_2E8

VDDQ_3E12

VDDQ_4G12

VDDQ_5H8

VDDQ_6H9

VDDQ_7H11

VDDQ_8J9

VDDQ_9J10

VDDQ_10K8

VDDQ_11K11

VDDQ_12L12

VDDQ_13N8

VDDQ_14N12

VDDQ_15R12

VDDQ_16U11

VSS_0B2

VSS_1B5

VSS_2C5

VSS_3E4

VSS_4E5

VSS_5F5

VSS_6H2

VSS_7J12

VSS_8K2

VSS_9L6

VSS_10M5

VSS_11N4

VSS_12N5

VSS_13R4

VSS_14R5

VSS_15T2

VSS_16T3

VSS_17T4

VSS_18T5

VSSQ_0B6

VSSQ_1B12

VSSQ_2C6

VSSQ_3D12

VSSQ_4E6

VSSQ_5F6

VSSQ_6F12

VSSQ_7G6

VSSQ_8G9

VSSQ_9H10

VSSQ_10K10

VSSQ_11L9

VSSQ_12M6

VSSQ_13M12

VSSQ_14N6

VSSQ_15P12

VSSQ_16R6

VSSQ_17T6

VSSQ_18T12 NC0

A1

NC1A2

NC2A12

NC3A13

NC4B1

NC5B13

NC6C4

NC7K9

NC8R3

NC9T1

NC10T13

NC11U1

NC12U2

NC13U12

NC14U13

VDDCA_0F2

VDDCA_1G2

VDDCA_2H3

VDDCA_3L2

VDDCA_4M2

VSSCA_0C3

VSSCA_1D3

VSSCA_2F4

VSSCA_3G3

VSSCA_4G4

VSSCA_5J4

VSSCA_6M4

VSSCA_7P3

VREFCAH4VREFDQJ11

R340100K-NCR0402

C535100nFC0402

R336 1K-NC R0402

C532100nFC0402

C52822pFC0402

R3422.2K-1%R0402

MT52L256M32D1PF-107WT

U25A

bgalpddr178p8b110x115

DQ0P9

DQ1N9

DQ2N10

DQ3N11

DQ4M8

DQ5M9

DQ6M10

DQ7M11

DQ8F11

DQ9F10

DQ10F9

DQ11F8

DQ12E11

DQ13E10

DQ14E9

DQ15D9

DQ16T8

DQ17T9

DQ18T10

DQ19T11

DQ20R8

DQ21R9

DQ22R10

DQ23R11

DQ24C11

DQ25C10

DQ26C9

DQ27C8

DQ28B11

DQ29B10

DQ30B9

DQ31B8

DM0L8

DM1G8

DM2P8

DM3D8

DQS0_TL10

DQS0_CL11

DQS1_TG10

DQS1_CG11

DQS2_TP10

DQS2_CP11

DQS3_TD10

DQS3_CD11

CA0R2

CA1P2

CA2N2

CA3N3

CA4M3

CA5F3

CA6E3

CA7E2

CA8D2

CA9C2

ZQ0B3

ZQ1B4

CKE0K3

CKE1K4

CK_CJ2CK_TJ3

CS0_NL3

CS1_NL4

ODTJ8

C529100nFC0402

R33924K-1%R0402

R337 0R R0402

SAMA5D24_BGA256

U24E

TFBGA256_0p4_8x8mm

DDR_A0D17

DDR_A1A17

DDR_A10H11

DDR_A11J10

DDR_A12D15

DDR_A13J11

DDR_A2A18

DDR_A3F15

DDR_A4G12

DDR_A5H12

DDR_A6F13

DDR_A7H10

DDR_A8A16

DDR_A9E12

DDR_BA0H13

DDR_BA1K12

DDR_BA2H17

DDR_CALG17

DDR_CASE17

DDR_CKEF18

DDR_CLKC18

DDR_CLKNC17

DDR_CSJ12

DDR_D0B12

DDR_D1B13

DDR_D10J13

DDR_D11H15

DDR_D12J15

DDR_D13J14

DDR_D14K13

DDR_D15K18

DDR_D16A8

DDR_D17B9

DDR_D18D9

DDR_D19A9

DDR_D2D13

DDR_D20B11

DDR_D21D10

DDR_D22A11

DDR_D23A12

DDR_D24L18

DDR_D25K15

DDR_D26K14

DDR_D27M18

DDR_D28N17

DDR_D29M14

DDR_D3A13

DDR_D30M15

DDR_D31N18

DDR_D4A15

DDR_D5D14

DDR_D6B15

DDR_D7B16

DDR_D8G18

DDR_D9K17

DDR_DQM0D11

DDR_DQM1H14

DDR_DQM2B8

DDR_DQM3L13

DDR_DQS0A14

DDR_DQS1H18

DDR_DQS2A10

DDR_DQS3M17

DDR_DQSN0B14

DDR_DQSN1J18

DDR_DQSN2B10

DDR_DQSN3L17

DDR_RASE18

DDR_RESETNF17


DDR_WED18

R335240R-1%R0402

C5334.7uFC0603

R3432.2K-1%R0402

C530100nFC0402

R338100KR0402

AN

2717H

ardware A

spects

© 2018 M


DS00002717A-page 42

This set features a SAMA5D24/BGA256 MPU and one 8-Gbit Micron LPDDR3-SDRAM device (Part No.:MT52L256M32D1PF-107WT).




The above figure shows layer 3 of the test board focused on the LPDDR3-SDRAM configuration. It isused as a signal layer, and contains traces for data lanes 1 and 2. Trace width and clearance are inaccordance with the minimum required for most of these signals. There are, however, exceptions in theregion underneath the MPU, where the 0.4-mm ball pitch does not allow to route traces wider than 3 mils.In this case, it is allowed to go below the 4 mils minimum because of high signal density.

Traces belonging in each data lane are tightly matched, with a 14-mils length mismatch for data lane 1and a 34-mils mismatch for data lane 2. The DQS1/DQS1n and DQS2/DQS2n differential signals are alsovery precisely matched with a mismatch between signals from the same pair of 1 mil, respectively 3.2mils.






The above figure shows layer 4 of the test board, centered on the LPDDR3-SDRAM device. It is used assignal layer and contains both address and control/command signals. The trace width and clearance sizeare in accordance with the general routing rules.

The trace impedance can be calculated using the stripline impedance formula (Equation 2) or using aspecialized calculator. Applying the formula results in a trace impedance Z0 = 48.17 Ω.



Figure 3-34. SAMA5D24/BGA256/LPDDR3-SDRAM Layer 1 (Top)

CK/CKnTrace width = 4 milsTrace clearance = 8 mils

The above figure shows the top layer of the test board centered on the LPDDR3-SDRAM device. Thedifferential CK/CKn signals are routed on this layer, with the commented trace width and clearance. Thedifferential pair impedance is 101.73 Ω, very close to the 100 Ω target.






The above figure shows layer 6, where data lanes 0 and 3 from the LPDDR3-SDRAM are routed.

The target impedance for DQS0/DQS0n and DQS3/DQS3n differential pairs is 100 Ω. Using animpedance calculator resulted in a value of 98.16 Ω. All power layers provide an unslotted referenceplane to maintain a good signal integrity.



4. Software Aspects

4.1 On-board SDRAM Device(s) Initialization SequenceEvery DDR-SDRAM type has a specific initialization sequence that must be performed after systempowerup. The required steps are a sequence of electrical patterns, executed by software by themicroprocessor and applied to the memory device through the embedded DRAM controller (“MPDDRC”).

These settings are detailed in section “Multiport DDR-SDRAM Controller (MPDDRC)” of the SAMA5D2series datasheet. They are explained in a straightforward sequential manner below, for each kind ofmemory device. After the last step in the initialization sequence is issued, the SDRAM device is fullyfunctional.

The tables in the following subchapters describe each initialization step with the necessary action (whatneeds to be done), the registers involved in that action, and the settings (values) to be written in theregister fields.

Software support is provided with drivers and examples in the form of a software package.

4.1.1 DDR3-SDRAM/DDR3L-SDRAM InitializationThe initialization sequence is performed by software. The DDR3-SDRAM devices are initialized by thesequence described in the table below.

Note: These settings were verified as functional for the Micron MT52L256M32D1PF-107WT device.Application to other brands should be verified against their respective datasheets.

Table 4-1. DDR3-SDRAM/DDR3L-SDRAM Initialization

Step Action Register Setting

1 Program the memory devicetype

MPDDRC_MD MD = 4 (for DDR3), DBW = 0(32 bits)

2 Program the shift samplingvalue

MPDDRC_RD_DATA_PATHSection 4.2 SDRAM ControllerConfiguration provides valuesfor these fields. These valuesdepend on the DDR clock.

3 Program DDR3-SDRAMfeatures

MPDDRC_CR MPDDRC_TPR0MPDDRC_TPR1

MPDDRC_TPR2

4 Issue a NOP command(4) MPDDRC_MR MODE = 1

5 500 μs delay(1) – –


7 Issue an EMRS2 cycle(2) MPDDRC_MR MODE = 5



10 Write a ‘1’ to the DLL bit MPDDRC_CR DLL = 1

AN2717Software Aspects


https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=SAMA5D2%20Software%20Package


11 Issue a Mode Register Set(MRS) cycle(3)

MPDDRC_MR MODE = 3

12 Issue a Calibration command(MRS) (3)

MPDDRC_MR MODE = 6

13 Provide a Normal Modecommand(4)

MPDDRC_MR MODE = 0

14 Write the refresh rate inCOUNT field

MPDDRC_RTR COUNT = Trefi/Tck

Note: 1. To issue a delay:

– disable interrupts;– compute a deadline = ROUND_INT_DIV((timer_channel_freq/1000)*count, 1000), where

count is the delay in µs;– start a timer and wait for the timer to reach the deadline;– enable interrupts.

2. To issue an Extended Mode Register Set (EMRS) cycle, after setting the MODE field to 5, readMPDDRC_MR and add a memory barrier assembler instruction just after the read. Then perform awrite access to the DDR3-SDRAM device so that the BA[2:0] signals are set as follows:

– BA[2] is set to 0, BA[1] is set to 0, BA[0] is set to 1 for EMRS1.– BA[2] is set to 0, BA[1] is set to 1, BA[0] is set to 0 for EMRS2.– BA[2] is set to 0, BA[1] is set to 1, BA[0] is set to 1 for EMRS3.

The address at which the write access is issued in order to acknowledge the command needsto be calculated so that the BA[2:0] signals are in the right state for an EMRS cycle.

3. After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instructionjust after the read. Perform a write access to acknowledge the command so that BA[2:0] signals areset to 0 (write at BASE_ADDRESS_DDR).

4. After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instructionjust after the read. Perform a write access at any address to acknowledge the command.

Refer to chapter ”Multiport DDR-SDRAM Controller (MPDDRC)” of the SAMA5D2 series datasheet formore information.

4.1.2 DDR2-SDRAM InitializationThe initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by thefollowing sequence:

Table 4-2. DDR2-SDRAM Initialization


1 Program the memory devicetype

MPDDRC_MD MD = 6 (for DDR2), DBW = 0(32 bits)

2 Program the shift samplingvalue

MPDDRC_RD_DATA_PATH Section 4.2 SDRAMController Configurationprovides values for these




3fields. These values dependon the DDR clock.

Program DDR2-SDRAMfeatures

MPDDRC_CR MPDDRC_TPR0MPDDRC_TPR1

MPDDRC_TPR2


5 200 μs delay(1) – –


7 Issue an All Banks Prechargecommand(4)

MPDDRC_MR MODE = 2




11 2 μs delay(1) – –



MPDDRC_MR MODE = 3

14 Issue an All Banks Prechargecommand(4)

MPDDRC_MR MODE = 2

15 Provide two autorefresh (CBR)cycles(4)

MPDDRC_MR MODE = 4



MPDDRC_MR MODE = 3

18 Configure the OCD field to 7 MPDDRC_CR OCD = 7


20 Configure the OCD field to 0 MPDDRC_CR OCD = 0


22 Provide a Normal Modecommand(4)

MPDDRC_MR MODE = 0

23 Write the refresh rate in COUNTfield

MPDDRC_RTR COUNT = Trefi/Tck

Note: 1. To issue a delay:

– disable interrupts;– compute a deadline = ROUND_INT_DIV((timer_channel_freq/1000)*count, 1000), where

count is the delay in µs;



– start a timer and wait for the timer to reach the deadline;– enable interrupts.

2. To issue an Extended Mode Register Set (EMRS) cycle, after setting the MODE field to 5, readMPDDRC_MR and add a memory barrier assembler instruction just after the read. Then perform awrite access to the DDR2-SDRAM device so that the BA[1:0] signals are as follows:

– BA[1] is set to 0, BA[0] is set to 1 for EMRS1;– BA[1] is set to 1, BA[0] is set to 0 for EMRS2;– BA[1] is set to 1, BA[0] is set to 1 for EMRS3.

The address at which the write access is issued in order to acknowledge the command needsto be calculated so that the BA[1:0] signals are in the right state for an EMRS cycle.

3. After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instructionjust after the read. Perform a write access to acknowledge the command so that BA[2:0] signals areset to 0 (write at BASE_ADDRESS_DDR).

4. After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instructionjust after the read. Perform a write access at any address to acknowledge the command.

Refer to chapter ”Multiport DDR-S