sacr: scheduling-aware cache reconfiguration for real-time embedded systems

21
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems Weixun Wang and Prabhat Mishra Embedded Systems Lab Computer and Information Science and Engineering University of Florida Ann Gordon-Ross Electrical and Computer Engineering University of Florida

Upload: raymond-osborne

Post on 03-Jan-2016

37 views

Category:

Documents


1 download

DESCRIPTION

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. Weixun Wang and Prabhat Mishra Embedded Systems Lab Computer and Information Science and Engineering University of Florida Ann Gordon-Ross Electrical and Computer Engineering University of Florida. Outline. - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time

Embedded Systems

Weixun Wang and Prabhat MishraEmbedded Systems Lab

Computer and Information Science and Engineering

University of Florida

Ann Gordon-RossElectrical and Computer Engineering

University of Florida

Page 2: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Outline

Introduction

Related Work

Scheduling-Aware Cache Reconfigurations

Phase-based Optimal Cache Selection

Scheduling-Aware Dynamic Reconfigurations

Experiments

Conclusion

Page 3: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

IntroductionReal-time embedded systems

Energy constraints (battery operated) Time constrained

Hard task deadlines– Safety-critical systems

Soft task deadlines– Gaming, multimedia, housekeeping devices have soft deadlines

– Deadline miss results in temporary service/quality degradation

Dynamic cache reconfigurations Promising for improving energy and performance Not applicable in real-time systems

Dynamic computation is expensive Dynamic reconfiguration leads to timing uncertainty 3

Propose a scheduling-aware dynamic cache reconfiguration technique to generate significant energy savings in soft real-time systems by exploiting static analysis during runtime.

Page 4: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Outline

Introduction

Related Work

Scheduling-Aware Cache Reconfigurations

Phase-based Optimal Cache Selection

Scheduling-Aware Dynamic Reconfigurations

Experiments

Conclusion

Page 5: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Related Work Energy-aware task scheduling techniques

Early Deadline First (EDF) and Rate Monotonic (RM)Dynamic Voltage Scaling (DVS)

Jejurikar et al. [IEEE TCAD 06’], Quan et al. [ACM TECS 07’]

Caches in Real-Time SystemsCache locking and Cache Partitioning

Puant [RTSS 02’] and Wolfe [IWRCS 1993]Cache-related preemption delay analysis

Tan et al. [ACM TECS 2007]

Reconfigurable Cache Architectures Reconfigurable cache architecture

Zhang et al. [ACM TECS 05’] Application-based vs. Phase-based tuning

Gordon-Ross et al. [ISLPED 05] vs. Sherwood et al. [Micro 03] 5

Page 6: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Outline

Introduction

Related Work

Scheduling-Aware Cache Reconfigurations

Phase-based Optimal Cache Selection

Scheduling-Aware Dynamic Reconfigurations

Experiments

Conclusion

Page 7: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Overview

7

Task 1 Task 2

In traditional real-time systems

In our approach

Page 8: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Phase-based Optimal Cache Selection

8

Task Execution Time

C1

C2

C3

Cn

phase 1 (0/n)

phase 2 (1/n)

phase 3 (2/n)

phase n (n-1/n)

P1 P20 Pn-1

A task is divided by n potential preemption points

A phase is the period of time between a predefined potential preemption point and task completion

Each phase has its optimal cache configuration Performance-optimal and energy-optimal

A static profile table is generated for each task

Page 9: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Phase-based Optimal Cache Selection

9

Potential preemption points may not be the same as actual preemption points. They are used for cache configuration selection.

Partition factor determines the potential preemption points and resulting phases Large partition factor leads to large look-up table

Not feasible due to area constraints

Large partition factor may not save more energy

Partition factor around 4 to 7 is profitable

Page 10: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Outline Introduction

Related Work

Scheduling-Aware Cache Reconfigurations Phase-based Optimal Cache Selection Scheduling-Aware Dynamic Reconfigurations

Statically Scheduled Systems Dynamically Scheduled Systems

Experiments

Conclusion

Page 11: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Scheduling-Aware Cache Reconfiguration

Statically scheduled systemsArrival times, execution times, and deadlines are

known a priori for each task

Statically profile energy-optimal configurations for every execution period of each task without violating any task deadlines

Dynamically scheduled systemsTask preemption points are unknown

New tasks can enter the system at any time Conservative approach Aggressive approach

11

Page 12: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Conservative Approach

12

Energy-optimal cache configuration with equal or higher performance than base cache

Nearest-neighborUse the nearest partition point to decide which cache

configuration to tune to

Static Profile tableDeadline-aware energy-

optimal configurations

Task list entryRuntime information

Page 13: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Aggressive Approach

13

Static Profile tableEnergy-opt configurationPerf.-optimal configuration

Task list entryRuntime information

Energy-optimal cache configuration & Performance-optimal cache configuration Includes their execution time as well.

Ready task list (RTL) Contains all the tasks currently in the system

Page 14: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Outline

Introduction

Related Work

Scheduling-Aware Cache Reconfigurations

Phase-based Optimal Cache Selection

Scheduling-Aware Dynamic Reconfigurations

Experiments

Conclusion

Page 15: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Experimental Setup

15

SimpleScalar to obtain simulation statisticsUsed external I/O (eio) trace file, checkpointing

and fastforwarding to generate static profile tableEnergy model

Zhang et al. and CACTI 4.2 Benchmarks

EEMBC MediaBench

Page 16: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Energy Savings (Instruction Cache)

16

51% average energy saving using aggressive approach

28% average energy savings using conservative approach

Page 17: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Energy Savings (Data Cache)

17

22% average energy saving using aggressive approach

17% average energy savings using conservative approach

Page 18: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Hardware Overhead

18

Profile Table stores 18 cache configurations Synthesized using Synopsys Design Compiler Assumed lookup frequency of one million nanoseconds

Table lookup every 500K cycles using 500 MHz CPU

Average energy penalty is 450 nJ Less than 0.02% of overall savings (2825563 nJ)

Page 19: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

ConclusionDynamic cache reconfiguration is a promising

approach to improve both energy consumption and overall performance.

Developed a scheduling aware dynamic cache reconfiguration technique On average 50% reduction in overall cache

energy consumption in soft real-time systems

Future workHard real-time systemsMulti-core and multi-processor systems

19

Page 20: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Thank you !

Page 21: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Aggressive Approach

21

When task T is the only task in the system Always tune to energy-optimal cache if possible

When task T preempts another task Run schedulability check

Discard the lowest priority task if absolutely necessary

Tune to energy-optimal cache

if all other tasks in RTL can meet their deadlines using their performance-optimal caches

When task T is preempted by another task Calculate and store runtime information (RIN, CP)