s7 - frequency response design 2

7/31/2019 S7 - Frequency Response Design 2

1/44

Characteristics of Lead and

Lag Compensators

Lead Compensator

uses phase advance at

the zero-crossing

increases high

frequency gain and

shifts wc to the right

increases bandwidth

limited amount of

compensation possible

Lag Compensator

uses gain reduction to

shift the zero-crossing

to the left

introduces phase lag at

frequencies below wc

reduces bandwidth

very large amount of

compensation possible


2/44

Characteristics of Lead-Lag

Compensators Ks

G c

c=

)

(

s

s

t

a

+

+

1

1''

'

t

s

s

t

a

+

+

1

1 t

t= 0.4472a= 5

at= 2.236

t= 22.36a= 8

at= 178.9qm = 40

wm == 1

a

t

1

lead lag

For a constrained

implementation, a= aFrequency (rad/sec)

Phase(

deg)

Ma

gnitude(dB)

Lead-Lag Compensator Characteristics

-15

-10

-5

0

10-3 10-2 10-1 100 10

1 102

-40

-20

0

20

40

t

1

ta

1

t

1'ta

1''

m

q

dB

dB

aa 2

11'

+dBa

'

1

at

1


3/44

Lead-Lag Compensator

Implementation (a = a)

eie

o

R1 R2

C1

C2

)

(

11

1

)

(

2

2

11

1

2

2

s

E

C

sR

C

R

s

R

C

sR

s

E i

o

+++

+=

)

'1

)(1

(

)

'1

)(1

(

)

()(

1

)1

)(1

(

)

(

'

22211212211

2211

ss

ss

s

E

s

C

R

C

RsC

RC

RC

R

s

C

Rs

C

R

s

E i

o

tt

tt

a

a

++

+

+=

++++

+

+=

where . . .

(constrained)


4/44

These three equations are

used to determine the

circuit components from

the specified t, t, and a.

An unconstrained lead-lag

network, aa can be

implemented as separatelead and lag networks

buffered by an op-amp.

Lead-Lag Compensator

Implementation

212211

C

RC

RC

R ++

=

'

=+22

11

C

RC

R +

aa

a

tt

22

'

C

R

=

t11

C

R

=a

t

where

This results in a

constrained lead-lag

network, a= a.


5/44

Bode Plot Design of Lead-Lag

Compensators

Five parameters to be chosen in the design.

Kc:amplifier gain, low-frequency gain requirements.

a : the desired phase advance, qm.

t: lead time constant, to place qm at the designzero- crossing frequency,wc.

a : the required high frequency gain reduction.

t : lag time constant to place the lag zero, onedecade below wc .

Ks

G c

c=

)

(

s

s

t

a

+

+

1

1''

'

t

s

s

t

a

+

+

1

1 t


6/44

1. Loop gain requirement:

Determine the loop gain required to meet the steady-

state error specifications.

2. Bode plot: Plot the loop transfer function including the required

gain increase from step 1.

3. Desired Phase Advance (calculate a) Select a desirable amount of phase advance qm and

calculate the corresponding a .


Compensators: Design Steps


7/44

4.Required Gain Reduction (calculate a)

Determine the frequency, wc where the design

phase margin would be achieved, accounting for thephase advance, qm and the 5 of the tail of the lag.

fm(uncomp) = fm(spec)qm+ 5

Determine the gain reduction required to make wcthe zero-crossing frequency and calculate a.

| gain reduction |dB = |1/a|dB + | a|dB




8/44

5. Required tand t:

Select t to place the qm at wc ; wc=

Select t

such that the zero, 1/t

is onedecade below wc ;

6. Required Kc :

Select Kc to give the required low-frequencygain increase.

7. Implement:



1

at

10'

1'

t=wc

KsG cc =)(s

s

ta++

1

1''

'ts

s

ta

++

1

1 t


9/44

For the constrained design(a= a )steps 3

and 4 may require some iteration similar to

the lead design.

In this case the gain reduction is

| 1/a|dB + |a|dB= |a|dB


Compensators: (a= a )

wc ,fm qm a | a|dBspecs.

+ 5 1

1sin+-=

a

aqm

gain

reductionBode

plot


10/44

Lead-Lag Design Example 1

The plant

Specifications:

steady-state error 45

The first part of the

design is the same as

the phase-lead design.

Steady-state error:

Draw the Bode plot of

( )21

)(+

=ss

sGp

40>K

05.02/

1)(lim

0


11/44

Chooseqm= 20 , then

a= 2.0, | a|dB = 3dB. f

m(uncomp)=

4520+ 5= 30

wc = 3.5 rad/s

Gain reduction = -9dB

= | 1/a|dB+| a|dB| 1/a|dB = -12dB

and a= 4


Frequency (rad/sec)

Phase

(deg)

Magnitude(dB)

Lead-Lag Design (unconstrained)

0

20

40

60

10-2 10-1 100 101

-160

-140

-120

-100

-150

9 dB

3.5


12/44

Lead time constant

wc= 3.5 =

t= 0.20 Lag time constant

t= 2.86

Controller gain

Kc = 40

Final Controller


1

2t

10'

1'

t =wc

= 0.35 s

s

s

s

sGc 44.111

86.21

2.01

4.01

40)( ++

++

=


13/44

Frequency (rad/sec)

Phase(deg)

Magnitude(dB)

qm = 45 wc = 3.5 rad/s

-40

-20

0

20

40

60

10-2 10-1 100 101 102-180

-160

-140

-120

-100

-135

3.5

uncompensated

compensated



14/44

For qm= 20 , a= 2.0

a= 4

Chooseqm= 27 , then

a= 2.7 a= 2.7 The gain reduction is

| a|dB =4.3 dB

The new zero-crossingis wc = 4.7 rad/s

The phase margin is

25 + 27 5 = 47


Constrained (a= a )

Frequency (rad/sec)

Phase

(deg)

Magnitude(dB)

Lead-Lag Design (unconstrained)

0

20

40

60

10-2 10-1 100 101

-160

-140

-120

-100

-150

9 dB

3.5


15/44

Lead time constant

wc= 4.7 =


t= 2.13

Controller gain

Kc = 40

Final Controller

1

2.7t

10'

1'

t =wc

= 0.47


Constrained (a= a )

s

s

s

ssGc 75.51

13.21

129.01

350.0140)( +

+

++

=


16/44

Frequency (rad/sec)

Phase(d

eg)

M

agnitude(dB)

Lead-Lag Constrained Design

-40

-20

0

20

40

60

10-2 10-1 100 101 102-180

-160

-140

-120

-100

-133

4.7

compensated

uncompensated


Constrained (a= a )


17/44

Closed-Loop Step Responses

Time (sec.)

Amplitude

Step Response

0 1 2 3 4 5

0

0.2

0.4

0.6

0.8

1

1.2

___ lead compensator

___ lag compensator

___ lead-lag compensator

(constrained)

___ lead-lag compensator(unconstrained)


18/44

Compensator Design Example 2

)255)(2.0(

50)(

2 +++=

ssssGp

The plant

Specifications:

steady-state error 60

Steady-state error:

Draw the Bode plotof

9.4K

02.0101

1)(lim

0

+==

Kss Ee

sss

)(

1)(

)(1

1)(

+=

+=

ssKGssR

sKGsE

pp

)255)(2.0(

245)(

2 +++=

ssssGp


19/44

fm(uncomp) = 27at

wc = 6.7 rad/s

A lead compensator

would need toprovide > 87phase

advance.

A lag compenstor

needs to introduce a

high frequency gain

reduction of13dB.Frequency (rad/sec)

Phase(deg)

Magnitude(dB)

Bode Diagram for Example 2

-10

-50

5

10

15

20

100 101

-220

-200

-180

-160

-140

-120

-100-115

fm = 27

13dB

2.3 6.7

Compensator Design Example 2


20/44

Lag Compensator Design

Example 2

The gain reduction at

wc= 2.3 rad/s to make

this the zero crossing is13dB. The phase at

this frequency is 115.

(180 + 60 + 5)

|1/a|dB = 13dBa = 4.6

The time constant is

1/t = wc/10 = 0.23

t = 4.35 The gain is

Kc = 4.9

The final controller is

s

ssGc

0.201

35.419.4)(

++

=


21/44

Frequency (rad/sec)

Phase(de

g)

Magnitude(dB)

Lag Design for Example 2

-20

-10

0

10

20

100 101-240

-220

-200

-180

-160

-140

-120

-100

fm =

60

13dB

2.3

Lag Compensator Design

Example 2


22/44

Lead-Lag Compensator Design

Example 2

Frequency (rad/sec)

Phase(deg)

Magnitude(dB)


-10

-50

5

10

15

20

100 101

-220

-200

-180

-160

-140

-120

-100-115

fm = 27

5.5dB

2.3 6.75.1

Chooseqm= 65 , then

a= 20.3, and

| a|dB = 13.1dB.

fm(uncomp) =60 65+ 5= 0

wc = 5.1 rad/s

Gain reduction =

5.5dB= | 1/a|dB + | a|dB

| 1/a|dB = 18.6dB

and a= 8.5


23/44

Lead time constant

wc= 5.1 =


t= 1.96

Controller gain

Kc = 4.9

Final Controller

1

20.3t

10'

1'

t =wc

= 0.51 s

s

s

s

sGc 66.161

96.11

0435.01

883.01

4.9)( ++

++

=


Example 2


24/44


Example 2

Frequency (rad/sec)

Phase(de

g)

Magnitude(dB)

Lead-Lag Design for Example 2

-10

-5

0

5

10

15

20

100

101-240

-220

-200

-180

-160

-140

-120

-100

-80

fm = 60

5.1

uncompensated

compensated


25/44

Design Comparison

Example 2

Frequency (rad/sec)

Phase(deg)

Mag

nitude(dB)

Bode Diagrams for Example 2

-80

-60

-40

-20

0

20

10-2 10-1 100 101 102

-250

-200

-150

-100

-50

0

uncompensated

lead-lag designlag design

-120

6.55.12.3


26/44

Design Comparison

Example 2

Time (sec.)

Amplitude

Step Responses for Example 2

0 2 4 6 8 10

0

0.2

0.4

0.6

0.8

1

___ uncompensated

___ lead-lag design

___ lag design


27/44

Lead-Lead Compensation Design

One of the limitations of lead compensators

is that the phase advance is limited to about

70 - 80.

To overcome this limit, consider cascading

two lead compensators.

The design follows as with a single lead

except the phase advance is doubled, to 2qm

and the gain increase at the new zero

crossing is also doubled, to | a|dB .


28/44

Lead-Lead Design for Example 2

Initial fm= 27 , so

choose 2qm = 60 + 27

+ 23 = 110 , qm = 55

Then a= 10

The gain increase is

| a|dB = 20 dB .

The new predictedwc= 14 rad/s and

fm(uncomp)= 69

fm= 69+110= 41

Frequency (rad/sec)

Phase(deg)

Magnitude(dB)


-60

-40

-20

0

20

100 101 102

-250

-200

-150

-100

-50

14

-249


29/44

Second iteration:

choose 2qm = 60 + 69

+ 11 = 140 , qm = 70

Then a= 32 The gain increase is

| a|dB =30 dB .

The new predictedwc

= 20 rad/s andfm(uncomp)= 75

fm= 75+140= 65

OK

Calculate t

Calculate the gain Kc

The final compenstor

00884.0

3220

1 == t

120 ===

t aww

cm

Two lead networks in series.


70.84.94.91 === aa2 cc

KK2

2

00884.01

283.01

32

18.70)(

+

+=

s

ssGc


30/44


Frequency (rad/sec)

Phase(deg)

Mag

nitude(dB)


-60

-40

-20

0

20

100 101 102

-250

-200

-150

-100

-50

-115

fm = 65

20

uncompensated

lead-lead compensated


31/44

Time (sec.)

Amplitude

Step Response Comparison

0 1 2 3 4 5

0

0.2

0.4

0.6

0.8

1

___ lag design

___ lead-lag design

___ lead-lead design

Closed-loop System


PID C l D i I Th


32/44

PID Control Design In The

Frequency Domain

Treat the PD controller as a special case of a

lead compensator, the PI as a special case of

the lag compensator and the PID controlleras a special case of the lead-lag

compensator.

Design with slightly modified frequencyresponse procedures and then fine tune on-

line.


33/44

PD Frequency Domain Design

PD Controller

This is a lead

compensator with the

pole at w .

The low frequency

gain is Kp .

The gain and phase

angle at frequency, w

p

dp

K

KsK =+= tt where)1(

p

dp

dpc

sKKK

sKKsG

+=

+=

)1(

)(

)(tan)(1 ww t-= jGc

1)( 22ww t+=KjG pc

)1()( ww t+= jKjG pc


34/44

PD controller with a

high frequency cut-off.

s

sK

s

sKsKKs

sKKsG

d

p

d

ddpp

d

dpc

tt

ttt

+

+=

+

++=

++=

1

1

1

1

)(

Frequency (rad/sec)

Phase(d

eg)

Ma

gnitude(dB)

PD Controller Reference Plot : Kd= 1 , Kp= 1

0

10

20

30

40

10-1

100 101 102

20

40

60

80

1/td1/td

__ ideal

__ 1/ d two decades above

__ 1/ d one decade above

|Kp|dB

K

K

p

ddt+ )(t=where

1/t



35/44

The design process is

similar to the lead

compensator design.

Choose the phaseadvanceq and determine

wt from

Determine the gainincrease from

Check the new zero

crossing frequency, wc

and the corresponding

phase margin (iterate). Determine t from

Determine Kp from thelow frequency gain

requirements.

1/td= 100 1/t


)(tan1 wct

-=q)(tan 1 wt-=q

1)(22ww t+=KjG pc


36/44

PI Frequency Domain Design

PI Controller

This is a lag

compensator with the

pole at w= 0 and the

zero at

Note that the PI

compensator introduces

a pole at the originwhich increases the

system type by 1.

The high frequency

gainKp .

s

sK

s

sK

K

Ks

KKsG

ii

i

p

ii

pc

)1(

)1(

)(

t+=

+=+=

i

p

iK

K=t


37/44

The design is similar to

the lag compensator.

Select Kp to give the

required wc that willsatisfy the fm + 5

.

Select Ki such that the

zero is one decadebelow wc .

PI Frequency Domain Design

Frequency (rad/sec)

Phase(

deg)

Magnitude(dB)

PI Controller : Ki= 1 , Kp= 1

0

10

20

30

40

10-2 10-1 100 101

-80

-60

-40

-20

|Kp|dB

1/ti

c

p

i

i K

K w

t

==110


38/44

PID Frequency Domain Design

PID Controller

)1(

)1)(1( 21

ss

ssK

d

i

ttt

+++=

)1(

))(1)(1(

)1(

1)(

2

22

ss

sKKKsKKK

ss

sKsKKsKsK

s

sK

s

KKsG

d

ddpidipi

d

ddiidpp

d

dipc

t

ttt

tt

t

+

++++=

+++++=

+++=

dip

iddp

KK

KKK

tttttt

+=+

+=

21

21 )(where,


39/44

The PID controller is

similar to a lead-lag

compensator, with

the lag pole at zeroand the lead pole at

1/td .

w2 represents afrequency relative to

1/t2 for a phaseadvance of70 .


Frequency (rad/sec)

Phase(d

eg)

Magnitude(dB)

PID Controller: 1 =10 , 2 = 1 , Ki= 1

20

30

40

50

60

10-3 10-2 10-1 100 101

-50

0

50

1/t1 1/t2 w2|Kp|dB


40/44

For the PID design, first

choose a phase advanceq

and calculate wt2 from

Then determine the

frequency, wcwhere

fm(uncomp) = fm(spec)

q+ 5

. Calculate t2 from wcand q. Select 1/t1one decade

below1/t2 .

Select 1/tdtwo decadesabove1/t2 .

Plot the compensated

system with Ki = 1 anddetermine the gain

reduction required to

make wc the zero

crossing frequency.


)(tan 1 wt2-=q

PID F

D i D i


41/44

Chooseq= 70 . Fromthe PID characteristics,

this occurs at

wt2 = tan(70

) = 2.75. Find the frequency

where, fm(uncomp) =6070+ 5= 5

wc = 5.2 rad/s

Find t2 from wct2 =2.75 t2 = 0.529

PID Frequency Domain Design:

Example 2

Frequency (rad/sec)

Phase

(deg)

Magnitude(dB)


-10

-50

5

10

15

20

100 101

-220

-200

-180

-160

-140

-120

-100

-185

5.2

PID F D i D i


42/44

Choose 1/t1 one

decade below 1/t2 .

1/t1 = 1/10t2t1= 5.29.

Choose 1/tdtwo

decades above 1/t2 .1/td= 100/t2

td= 0.00529.

Plot the systems with

the compensator

where Ki = 1 .


Example 2

)00529.01()529.01)(29.51()(

ssssKsG ic + ++=

PID F D i D i


43/44

Check the zero crossing

frequency for the phase

margin of 60. wc = 5.2

rad/s Find the required gain

reduction to make this

the zero crossing

frequency. 28.5dB

Set Ki= the gain

reduction. Ki= 0.0376


Example 2

Frequency (rad/sec)

Phase(

deg)

Magn

itude(dB)

PID Compensated System

-10

0

10

20

30

100 101

-200

-150

-100

-120

28.5dB

5.2

uncompensated

compensated, Ki = 1

compensated, Ki = 0.0376

PID F D i D i


44/44

Time (sec.)

Amplitude

Step Responses for PID and Lead-Lag

0 1 2 3 4 5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

__ PID

__ Lead-Lag



s7 - frequency response design 2

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