s~1 sic tc j jir u.-ejj adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable...

13
s~1 SIC TC J JIr U.-eJJ A rp. fYLd4-h-S - '1lL. 2q! II lIT \ o: !ClII1 Oc:t.12 294 Con. 7340-12. N.B. (1) Question No.1 is compulsory. (2) Attempt any four out of the remaining six questions. (3) Non-programmable calculator are allowed. 1. (a) A = +[ ~ -; ~] 3 2 -6 Show that- (i) IAI=1 (ii) .adj A = A' (b) Show that the Fouriar cQsine transfonn of- 1 l' f(x) = .JX is .JS (c) Show thatL -1 'tan~l Jt)= sii at ) (d) Show that i e-l sin (t~sin h( 1 1 )dt ··f 2. (a) If z is any non zero complex number show that- ·A '" $1 zl [; -:] is a unitary matrix. (b) Find the Fourier series expansion of f(x) = x 2 in (0, 2x] 7 sln2t + sin 3t dt _ .3&. (c) Show that ~ tel - 4. 00 3. (a) Find the half range sine series for f(x) = roc- x 2 in [ 0, 1t]. hence find n~1'(2~='1)6'. 6 s3 (b) Show that l (cos at cos hat) = s4 +4a 4 . 6 (c) Ifa. b•.care distinct real numberssuch that a i-b+c~O. Show that the vectors (a, b, c), 8 (b. c. a) and (c. a. b) are linearly independent.

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Page 1: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

s~1 SIC TC J JIr U.-eJJArp. fYLd4-h-S - '1lL.

2q! II lIT\

o : !ClII1 Oc:t.12 294Con. 7340-12.

N.B. (1) Question No.1 is compulsory.(2) Attempt any four out of the remaining six questions.(3) Non-programmable calculator are allowed.

1. (a) A = +[ ~ -; ~]3 2 -6

Show that-(i) IAI=1

(ii) .adj A = A'(b) Show that the Fouriar cQsinetransfonn of-

1 l'f(x) = .JX is .JS

(c) Show thatL -1 'tan~lJt)= siiat

)

(d) Show that ie-l sin (t~sin h ( 11)dt ··f

2. (a) If z is any non zero complex number show that-

·A '" $1 zl [; -:] is a unitary matrix.

(b) Find the Fourier series expansion of f(x) = x2 in (0, 2x]

7 sln2t + sin 3t dt _ .3&.(c) Show that ~ tel - 4.

00

3. (a) Find the half range sine series for f(x) = roc- x2 in [ 0, 1t]. hence find n~1'(2~='1)6'. 6

s3(b) Show that l (cos at cos hat) = s4 +4a4 . 6

(c) If a. b•.care distinct real numberssuch that a i-b+c~O. Show that the vectors (a, b,c), 8(b. c. a) and (c. a. b) are linearly independent.

Page 2: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

D : scan Oct.l2 295

Con. 7340-KR-3098-12.

{

X,

f{x) = 0,x--t.

-1t <..x <.: 0

O<x < -t~< x.< 1t

(b) Find all the possible ranks of the matrix

[k -3 -3 ]

A = -3 k -3 where k is any real number.-3 -3 k

se-1tS

(c) Find - (i) L-1 S2+3s+2 ; (ii) L [ t. H{t - 4) + t2 oCt- 4) ]

5. (a) Solve the system of equation using the Gauss-Seidel method:3x +. 4y + 6z = 62x + 5y + 4z = 112x+y+z=5

(b) Find L-1 s 2 using the convolution theorem.(s2+2) . - "

(c) Show that z [cos "(a k)] = z2 -z cos a .- " Z2 - 2(cos a)z + 1

6. (a) Find L f(t) where f(t) = cost, 0 < t < 7t

sin t ~ 7t.using the Heaviside unit step function.

(b) Find Z-l (Z_2)l(Z_3) "for 2 < I z 1<3 using resjpues.

. [ ~~~:)(~nS~)acooP -(sin p)(cosa)](c) Express the matnx A = ( A) (. ). A ( ) (, A) as a product of two. - cOSp Slna sin •.• COSa \cos •.•

l

7. (a) Solve the DE . Y+ Jydt ~ 1 -e-I using laplace ~ransforms. _ 6

(b) " If 0 :ix :i 7t show that- 6

2 2 [( 7t2 4)' ( 7t

2) . 2 ( 1t

2 4)' 3 ]x = 1i. -r- - 13 sin x - 2 sin x + -T-- 33 sin x + . . .. .

(c) Show that { cos n x}n > 1 is an orthogonal family of functions in [-7t, 1t]. Also find the 8corresponding orthon-ormal set.

Page 3: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

s -G· - $F If} 1D- (Fy-rL)~~~ ~{)t.-:L

KR-3203ITotlal Mnl"lct : 100

N. B.: (1) Question No.1 and 2 are compulsory.(2). Attempt any three questi~ns out of remaining questions.(3) In all five qUc:&1ionsto be attempted.

- (X.) Flg~res to the right indicate run marks.

I. 1\ Design for Supply voltage Yo:. Collector resistor RC, Emitter resistor RE.voltage divider biasing resistor R I & R2 of a single stage RC coupled CE audioamplifier for peak output voltuge oDV ot 5kO lond, Av ~ 100 and Slt'O~ 10.

I. b, Answer the following question related to design of' single stage CE audiofrequency voltage amplifie.'

i. Upper limit Rnd lower Iimil on choice of power supply vohuge VCCii. Upper limit on the choice of collector resistor RCHi. Lower limit on seleetiori of' emjtter resistor RE .iv. Experimcntally hmv will you determine input impedance and output

impedance orCE w!thout measuring inpu't Rnd output curI'Cnt

•2. a, Design single stage· RC coupled common source (CS) audio amplifier

employing WET type BF~II t)'picalto provide a voltage gain of Av ~ 10 litpeak output voltage of. Vo = 4.5V. loud resistor of 120kO • supply voltage of20V with biasing circuit to providc IDQ ~ 3 mA . '

2. b. For lhe above dl:signed ci.'cuit with source resistor "RS' unbypassed. determinevoltaye gain. input impedance. output impedance lInd output voltllge for inputvoltllge of20Vpp.

Design l\ full wuve rectifier de supply usilig center \lIpped. transformer with twodiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. Theload current expected is 50 ± 10 mA \vith ripple factor not to excet;d 0,07, UseLC tiller

. Explain operalion of the circuit shown in Figure A with detailed function ofresistor 'R'. Zener diode 'D', and BJT 'Q' in above drcuit

Page 4: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

i. The bestlocatiolrfor selling II Q-point on d.c. load line of an FET amplifier is .It PI-a) Saturation point b) Cut-on' pointc) Mid-point d) None (if these

ii. When transistors lire used in digital circuits they usually opcrate in the: 12)a) Active region b) BrCdk down regionc) Saturation region d) Saturntio,i & cut-otf region

iii. When an input delta l.lf 2 V produces a transconductance or 1.5 ms, what is the (21dl"ain current deltll?

0) 666 mA • b) J mAc) 0.75 mA d) 0.5 mA

iv.. Introducing Q resistor in the emitler of a common emitter amplifier stabilizes (2)the dc operating point against variations in: . . .

u) Only the temperature b) Only' the P of the transistorc) Both temperatufC and ~ d) Nonc of the above

v. A voltllge regulator has II no-load output of 18 V aud a. full-load outpyt of 17.3 12)V. The percent loud regulation' is

u) 0.25 % b) 96.1 %c) 4.05 % d) 1.04 %

4. b. Explain the lollowi~lg (Any two): [Sx2)i. . Gmphical determination of FET parametersii. Felllllres of IGBTiii. BJT as a switchiv. Power MOSFET

5. R. Discuss. using the concept of a lond line -superimposed Oil the transistor (101charllcteristics. how a simple common em iller circuit can amplify a timevarying signal

5. b. The tollowing parameters are obtained from certain JFET data sheet: VGSurr= (10)- 8 V and Ios.'l ••• 5 mA. Determine the volues of lu, tor each value of V(jsranging from 0 V to - 8 Vin 1V steps: Plot the transfer characteristic curve torthe slime data

Page 5: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

6. n. for the network shown in Figure n, determine the following with 12xSIIVBEonl == (}7 Vand P = iOO

i. Ice) Ilod 'ei)ii. Input&.Output impedanceiii. Voltage gainiv. Cun-ent gainv. List disadvantages of circuii shown

6. b. Detcl1nine the small signal voltage gain of a MOSFET circuit with VGSQ - 11012.12 V, VDD - 5 V, Rd '" 2.5 kG. VT/\(= 1 V. Kn '" 0.8 mAIVz dnd )..&: 0.02V·, (body eercet coefficient). Assume transistor (Figure C) is billSed in thesnturatiun region.

7. Explain in brief and sketch experimental setup to determine -i. Output chllracteristic ofCE BJT voltage amplifierii. Lille regulation of BJT shunl regulatoriii. Forward characteristic of SeR

. iv. Tnll1sler chal1lcteristic.or JFETv. UJT churacterislic

Page 6: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

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Page 7: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

~XrL~Re~ . (\f ) [)-'2-0 }'--~__

DJ·.:-J)

N.S. : (1) Question No.1 is compulsory.(2) Out of remaining six questions solve any four.(3) Each question ca'rries 20 marks. Equal marks for the ·sub-questions.(4) Assume suitable data if required.

1. (a) Perform the following operations :(i) 1010·1 x 101·1

(ii) (AA)H x (55)H(iii) Convert (77)a into Decimal number system(iv) Find (22-31 )10 using 2's complement number system(v) Convert (1110101100000111)2 into Hexa-decimal number system

(b) Draw state diagram of sequence detector to detect a non-overlapping sequence10001. Write its state table. Find the equivalent states if they are present.

Que (2) (A) Design Ic;>ckoutfree Mod 13 up synchronous counter using JKMS flip flops.(B) Do the following conversions of flip flops;

(I) JKMS to T. -(II) D to T. -

Que (3) (A) Draw CMOS inverter circuit, discuss its operation and draw its transfercharacteristic.

(B) For the following function implement the SOP and POS circuit.F (A,B,C,D) = Lm (2,3,5,7) + Ld (6,13,14,15)

Que (4) (A) For the following function find the reduced Boolean equation using QuineMcClusky method; •F (A,B,C,D) = Lm ( 1,3,4,6,9,11,12) + Id (5,8,15 )

(B) Draw JKMS flip flop and explain its operation.

Que (5) (A) Design full adder using decoder with active high output.(B) Explain following characteristics of logic families;

(I) Propagation delay (II) Noise margin (III) Current parameters(lV) Temperature range (V) Fan out.

Que (6) (A) Design a PROM which will convert BCD numbers into Gray code.(B) Use 5 Input, 3 Product, 4 OutPl!t PAL to realize foHo'wing 3 functions.

FI(A,B,C,D' = Im( 2,3,4,8,9,13,14)F2(A,B,C,D) = L:m( 2,3,5,8,9,14,15)F3(A,B,C,D) = Im( 2,3,4,8,9,14,15).

(I) FPGA, (II) Asynchronous counters, (III) Eel, logic family

(lV) Weighted and non-weighted codes, (V) ROM.

Page 8: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

s· E.. ~'IlTc It.-rn..!..LL- C~) U/!)f-C - ~IL-

5'1 h-'- - G J:- .65: 2nd half.12-shilpa(e}

Con. 10287-12. KR-3437

N.S.: (1) Question No.1 is compulsory.(2) Solve any four questions from the remaining questions.(3) Assume suitable data.

1. Solve any four questions :-(a) Classify transducer.(b) Explain the significance of rise time arid bandwidth of CRO.(c) True RMS meters is always specified by crest factor. Justify.(d) Compare different types of ADCs.(e) On what principle does a digital frequency meter operate?"(f) State advantages and disadvantages of land line telemetry .

."2. (a) Compare following temperature transducers with respect to their characteristics, 10

measurement range applications RTD, thermocouple and thermistors".(b) What is the basic principle of wave analyser ? Explain hetrodyne wave analyser 10

with application.

3. (a) What is the role of a time base generator? What are the time base requirements. 10(b) Explain the principle of operation of dual slope DVM. 10

4. (a) Explain the significance of 31and 4 ~ digit displays. 102(b) Explain modulation methods used for A. F. telemetry system. 10

~5. (a) Explain the modes of operation of DSO. 10-- (b) Write a note on applications of Q meter. 10

6. (a) How is the displacement measured? State different transducers used for 10displacement measurement.

(b) Explain the performance characteristics of D/A converters. 10

7. (a) Explain pulSie code modulation' technique. 10(b) Explain different types of measurement errors witli frequency counters. 10

Page 9: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

/. S. E - ~ f;·'f.Tc g~ jll.- C etll)

'~ ~.b ..• ~ E: ND Scan Pea 1 71

Con. 11036-12. KR-3659

(3 Hours) [ Total Marks: 100N.S. (1) Question No.1 is compulsory.

(2) Attempt any four questions from the remaining six questions.(3) All questions carry equal marks.

1. Attempt any four :- 20(a) For maximum power transfer find the value of ZL if

(i) ZL is impedance(ii) ZL is pure resistance.

(b) Find initial value of,f(t) = 20 - 1Ot - e-251

. verify using initial value theorem.(c) In network given below, initial value of II-=.4A and V c = 100V. Find Ie (0+).

'XL

L ',o.n-C

(d) Currents 11and ~ entering at Port 1 and Port 2 respectively of two port net-work are given by following equation.

11= 0·5 V1 - 0·2 V212= - 0·2 V1 + V2

Obtain T and 1t(pi) representation.

(e) For network shown, find ~ and draw pole-zero plot.

48+ :I- T-

l'l' g. Vc ~-V.j.~

s

-- ~

[TURNOVER

Page 10: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

D Scan Pra 1 72

Con. 11036- KR-3659-12.

2. (a) Usingmeshanaiysisfind the powersuppliedby dependentvoltagesource. 10

·.50

SA

~ (b) Find current supplied by source .

. 3. (a) Write Band Q matrix for the Graph shown.

. 11I

4~-I

J

I"'"

II

+2-,}

I

Page 11: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

o Scan Pea I 73

Con. 11036- KR-3659-12.

(b) Draw Bode Plot for the function G(s). Find gain margin, phase margin and 10comment on stability.

G s - _ 2(s+0·25)( )- s2(s+1)(s+0.5)

4. (a) For the network below, switch is opened at t = 0 with initial conditions shown. Find 10dV1 dV2 • +

V1' dt ' dt at tIme 0

J..H

fOJl10Jl.'

(b) Find Y parameter using interconnection.

t- :(1

'\I, 1

Page 12: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

o Scan Pra 1 74

Con. 11036- KR-3659-12.

5. (a) In the network below, key is closed at t = 0, Find i1

(0+), i2

(0+) and i3

(0+). 10

LHC2... a-SF·

(b) Find i(t).

-1;::'01"' -;:z,-t:.

{\.J " (-r) = e.1H

iF

6. (a) Tha clrcuRattaina staady stale wiIh switch al poaitlon (a) and Is movad 10 poaitIon 10 ;;I(b) at t = O. Find vet) for t ~ O. .

V(VLv

Page 13: s~1 SIC TC J JIr U.-eJJ Adiodes to 'give dc output ~volt(\ge at 150 volts to 8 variable .resistive load. The load current expected is 50 ± 10 mA \vith ripple factor not to excet;d

D Scan Pra 1 75

Con. 11036- KR-3659-12. 5

(b) Find Z11' Z21 and G2110

QF QI=-\ ""-1 tt

V.Q.V1 T1F

J~ .•..

7. (a) Realize following function in Foster" form10

Z s _ (s2+1) (S2+3)()- S(S2+2)(S2+4)

(b) Check following polynomials for Hurtwitz :_10

(i) p(s) = S4+ 4s2 + 8-----(ii) p(s) = S4+ S3+ 5s2 + 3s + 4.