s-c circuits microelectronic… · associate prof. dr. soliman mahmoud electronics and electrical...

1

Winter 2007 1

Microelectronics

Chapter 7:

Switched- Capacitor Circuits(S-C Circuits)

( Discrete- Time Circuits)

Associate Prof. Dr. Soliman MahmoudElectronics and Electrical Engineering Department

ELCT 703, MicroelectronicsWinter 2007 2

S-C CircuitsObjectives and outlines:

1. Introduction2. Resistor Realization Using S-C3. S-C Resistor4. Applications of S-C Resistor: Analysis in Discrete-Time (DT)

5. Parasitic- Insensitive Integrators6. Signal –Flow Graph Analysis7. Implementing-Analyzing 1st Order Filters

2



1. Introduction

S-C circuits depends on the following idea:

The Equivalence of RESISTOR with periodically switchedCapacitor

S-C circuits operates as a discrete-time signal processor. As a results, these circuits are most easily analyzed with the use of Z-Transformtechniques and typically require Anti-aliasing and smoothing filters.



1. Introduction

Advantages of S-C circuits

1. Accurate frequency Response, since the filter coefficients are determined by Capacitor Ratios which can be set quite precisely in integrated circuits (IC’s). But filter coefficients of active filters are determined by RC [ Accuracy in S-C on the order of 99.9 %, Accuracy in Active-RC on the order of 80%].

2. Good linearity and dynamic range.

3



2. Resistor Realization Using S-C The resistor realization contain : (1) Capacitors (2) Switches ( MOS Transistors) (3) Non-overlapping clocks

Two Phase Non-overlapping clocks used to switch the MOS Transistors:

S-C circuits simulate the continuous-time resistor very well as long as fclock > 2 fmax of analog signal processed by the S-C circuits (Sampling Theory).



Parallel – Switch Capacitor3. S-C Resistor

During 1 (0 Tc/2) During 2 (Tc/2 Tc)

Q1[0 Tc/2] = C V1 Q2[Tc/2 Tc] = C V2

4



3. S-C ResistorDuring 1 (0 Tc/2) During 2 (Tc/2 Tc)

Q1[0 Tc/2] = C V1 Q2[Tc/2 Tc] = C V2

Therefore, the change over one clock cycle, Q is given by:Q = C (V1 - V2)

Since the charge transfer is repeated every clock period, we can find average current Iav as follow:

RVV

Cf

VVVVCf

TVVC

TQ

I

c

CCc

av

)(1

)()(

)( 212121

21 −=−=−=−=∆=

cCfR

1=



3. S-C ResistorExample: What is the equivalent resistance of a 5 pF capacitance sampled at clock frequency of 100 KHz ?

Ω=== − MCf

Rc

2)10*100)(10*5(

11312

Therefore, very large resistance of 2 M can be realized on the IC through the use of Two MOS transistors, two non-overlapping clocks and a relatively small capacitances. Such a large resistance typically requires a large amount of CMOS silicon area if it realized as a resistor without any special processing fabrication steps.

5



4. Applications of S-C ResistorDiscrete-Time (DT) Integrator

Continuous-Time (CT)Integrator

Discrete-Time (DT)Integrator

ωω

ω jRCjSRCVV o

i

o −=−=−=22

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Analysis in Discrete-Time (DT)

At the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant

Charge on C1 = C1 vi(n-1) Charge on C1 = C1 * 0 = 0

Charge on C2 = C2 vo(n-1) Charge on C2 = C2 vo(n-0.5)

When 1 goes high, the input signal is sampled resulting in charge on C1 equal to C1Vi(n-1)

When 2 goes high, its switch forces C1 to discharge since VC1 =0. This discharging pass through C2 and hence the charge on C1 is added to the charge on C2

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Analysis in Discrete-Time (DT)At the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant



We can Write the charge equation:[ charge Conservation eq.]

)1()1()5.0( 122 −−−=− nvCnvCnvC ioo

Charge on C2 at theend of (n-0.5)

[2]

Charge on C2 in thestart of (n-0.5)Or end of (n-1)

Discharge of C1in C2

1



Analysis in Discrete-Time (DT)At the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant



We would like to find charge on C2 at the end of 1or at [n]

)5.0()( 22 −= nvCnvC oo

Charge on C2 at theend of (n)

Charge on C2 in thestart of (n)

Or end of (n-0.5)

2

vi(n) vo(n)2

1

7



Analysis in Discrete-Time (DT))1()1()5.0( 122 −−−=− nvCnvCnvC ioo 1

)5.0()( 22 −= nvCnvC oo 2 By substituting from (2) in (1) :

)1()1()( 122 −−−= nvCnvCnvC ioo

By taking the Z-Transform of both sides

)()()( 11

122 ZVZCZVZCZVC ioo

−− −=

]1[1

]1[)(

)()(

2

11

1

2

1

−−=

−−== −

−

ZCC

ZZ

CC

ZHZVZV

i

o



Analysis in Discrete-Time (DT)Note : The transfer function H(Z) can be written as :

][]1[1

)( 5.05.0

5.0

2

1

2

1−

−

−−=

−−=

ZZZ

CC

ZCC

ZH

To find the frequency response, we use the transformation:

CC TjST eeZ ω==

)2

sin(2][)(

2

2

1

22

2

2

1

C

Tj

TjTj

Tj

Tj

eCC

ee

eCC

H

C

CC

C

ωω

ω

ωω

ω −

−

−

−=−

−=

22

2

2

2

12

2

1 1

)2

(2)(

CC

CCTj

oTj

Tj

c

C

Tj

ej

eRCjj

eC

fCT

j

eCC

Hωω

ωω

ωω

ωωωω−−

−−

−=−=−=−≅

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Analysis in Discrete-Time (DT)Summary

Continuous-Time (CT)Integrator

Discrete-Time (DT)Integrator

2)(CT

jo e

jH

ω

ωωω

−−=

ωωωj

H o−=)(

Phase error term



NoteIn the previous analysis, we have ignored the effect of the parasitic capacitances associated with S-C circuits

change charge on C1 in charging & discharging

No effectS.C at all the time

No effectOn the O/P

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5. Parasitic- Insensitive Integrators

For the shown S-C integrator:(1) Find the transfer function H(Z)(2) Show that this integrator is stray - insensitive



5. Parasitic- Insensitive Integrators

At the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant



+-

10



5. Parasitic- Insensitive IntegratorsAt the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant



We can Write the charge equation:[ charge Conservation eq.]

)1()1()5.0( 122 −+−=− nvCnvCnvC ioo

Charge on C2 at theend of (n-0.5)

[2]

Charge on C2 in thestart of (n-0.5)Or end of (n-1)

Discharge of C1in C2

1

+-



5. Parasitic- Insensitive IntegratorsAt the end of 2 : (n-0.5)- instantAt the end of 1 : (n-1)- instant



We would like to find charge on C2 at the end of 1or at [n]

)5.0()( 22 −= nvCnvC oo

Charge on C2 at theend of (n)

Charge on C2 in thestart of (n)

Or end of (n-0.5)

2

2

1+-

vi(n) vo(n)

11



5. Parasitic- Insensitive Integrators)1()1()5.0( 122 −+−=− nvCnvCnvC ioo 1

)5.0()( 22 −= nvCnvC oo 2 By substituting from (2) in (1) :

)1()1()( 122 −+−= nvCnvCnvC ioo

By taking the Z-Transform of both sides

)()()( 11

122 ZVZCZVZCZVC ioo

−− +=

]1[1

]1[)(

)()(

2

11

1

2

1

−+=

−+== −

−

ZCC

ZZ

CC

ZHZVZV

i

o Non-InvertingIntegrator



5. Parasitic- Insensitive IntegratorsTo investigate the behavior of this non-inverting integrator w.r.t. parasitic capacitances, consider the same circuit drawn with parasitic capacitances as shown:

Notes: 1. CP3 and CP4 don’t affect the operation of the circuit as before.2. During 1 and 2, CP2 is s.c .3. During 1, CP1 is continuously charged by vi and discharged to

the ground during 2 and don’t affect on the charge on C1duringcharging or discharging. Stray insensitive integrator

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Parasitic Insensitive- Delay free Inverting Integrator

Report: For the shown Inverting Integrator, Show that:

]1[]1[1

)()()(

2

11

2

1

−−=

−−== − Z

ZCC

ZCC

ZHZVZV

i

o(1)

(2) This integrator is stray insensitive and delay free



6. Signal –Flow Graph Analysis Signal – Flow Graph is a method used to implement / analyze larger circuits in Z- domain.

Consider, the 3 – input integrator shown :

!"#

13



6. Signal –Flow Graph Analysis

By using the superposition:

)(1

1)(

12

)()( 313

21

1

11 ZV

ZCC

ZVZ

ZCC

ZVCC

ZVAAA

o −−

−

−−

−+−=

)(1

1)(

12

)(11

)( 313

21

1

11

11 ZV

ZCC

ZVZ

ZCC

ZVZZ

CC

ZVAAA

o −−

−

−

−

−−

−+

−−−=



6. Signal –Flow Graph Analysis

)(1

1)(

12

)(11

)( 313

21

1

11

11 ZV

ZCC

ZVZ

ZCC

ZVZZ

CC

ZVAAA

o −−

−

−

−

−−

−+

−−−=

Note that: the block : exists in all terms, this block

can be used to represent the op-amp with a capacitor CA in the feedback .

1111

−− ZCA

1111

−− ZCA

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6. Signal –Flow Graph AnalysisAnd the non-switched capacitor C1 in the input:

)1( 11

−−− ZC

12

−ZC

3C−

Noninverting-delayed -switched capacitor C2:

Inverting- delay free -switched capacitor C3:



6. Signal –Flow Graph (SFG) Analysis

1111

−− ZCA

)1( 11

−−− ZC

12

−ZC

3C−

The equivalentSignal flow graph

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Implementing-Analyzing 1st Order Filters

A first- order active RC filter:

Ai

o

CSRCSR

RR

SVSV

SH2

11

1

2

11

)()(

)(++−== ??)( =ZH



Analyzing 1st Order Filters Using SFG

)1( 11

−−− ZC

2C− 3C−

)1(11

1−− ZCA

16




)1(11

1−− ZCA )1(11

1−− ZCA

)()1( 1 ZVZC outA−−

)()1()()()()1( 1123

1 ZVZCZVCZVCZVZC ininoutoutA−− −−−−=−




A

AA

in

out

CC

Z

CC

ZCC

ZVZV

ZH31

211

)1(

)1(

)()(

)(+−

+−−==

−

−

1)1(

)(

)()(

)(3

121

−+

−+

−==Z

CC

CC

ZC

CC

ZVZV

ZH

A

AA

in

outOr

Notes:

1. DC Gain [ S =0 Z = eST=1] H (Z=1) = -(C2/C3)

2. H(Z) has a pole in the Z-domain at Zpole = (CA/(CA+C3))

3. H(Z) has a Zero in the Z-domain at ZZero = (C1/(C1+C2))

17



Frequency response of the 1st order filter

21

321

21

21

221

21

1

)(

)()(

ZCC

ZZ

ZCC

ZZCC

ZH

A

AA

+−

+−−=

−

−

H(Z) can be written as :

CTjeZ ω=

)2

cos()2

sin()2(

)2

cos()2

sin()2

()(

33

221

C

A

C

A

C

A

C

AeZ T

CCT

CC

j

TCCT

CCC

jZH CTj ωω

ωω

ω

++

++

−==

and

By making the approximation of : 12 <<=C

C ff

T πω

ω

ωω

)21

(1

)2(1)(

3

2

21

3

2

++

++

−==

CC

j

C

CC

j

CC

ZHA

eZ CTj



Frequency response of the 1st order filter

CA

C

eZ

TCC

j

TC

CC

j

CC

ZH CTj

ω

ωω

)21

(1

)2(1)(

3

2

21

3

2

++

++

−==

Notes :

1. DC gain :3

20 C

CH −=

=ω

2. Pole :)

21( 3

3

A

ACp

CC

CC

Tj+

−=ω)

21(

1

2

1

2

CC

CC

Tj CZ

+−=ω3. Zero :

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Summary

ωωω

ACjRCjR

RR

jH2

11

1

2

11

)(++−=

CA

C

eZT

CC

j

TC

CC

j

CC

ZH CTj

ω

ωω

)21

(1

)2(1)(

3

2

21

3

2

++

++

−==



Switched- Capacitor Circuits

END of Chapter 7

s-c circuits microelectronic… · associate prof. dr. soliman mahmoud electronics and electrical...

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