rtl-based functional test generation for high defects
TRANSCRIPT
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RTL-based Functional Test Generation forHigh Defects Coverage in Digital SOCs
RTL-based Functional Test Generation forHigh Defects Coverage in Digital SOCs
M.B. Santos, F.M. Gonçalves, I.C. Teixeira, J.P. Teixeira
IST / INESCLisboa, Portugal
ETW 2000 May, 23-26, 2000
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PurposePurpose
• Propose a RTL-based test generationmethodology for digital SOCs to be usedfor:– design validation– identification of “dark corners” of the
functionality– generate a functional test which can be
reused in structural testing (low energy, highdefects coverage)
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OutlineOutline
• Introduction• RTL fault models• Methodology• Experimental Set-up• Results• Conclusions
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• HDL - concurrent D&T• Test Reuse
– DFT– Design validation– Production test (HQ)– Lifetime test– Product / technology evolution
uP(IP core)
DRAM
Analog
ROM
UDLReused
Logic Design
...
IntroductionIntroduction
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• Purpose: Defect detection, low cost, test reuse
• Classic approach: LSA based ATPG / test validation
• Can RTL functional test be reused in production
test, to increase Defects Coverage ?
RTL
logic
Layout
Abstraction LEVEL Fault Models
?
LSA
BRI, Line-Open
IntroductionIntroduction
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RTL Fault ModelsRTL Fault Models
[1] Teresa Riesgo, UPM, 96[2] Ch. Robach et al., ITC 96[3] Haynes, Johnson, ITC 99[4] D. Schiuto et al., ITC 98[5] Ward, Armstrong, DAC 90[6] our work
RTLFaultModel
[1] [2] [3] [4] [5] [6]
LSA type X X X X XLogic/
ArithmeticOperations
X X X
Constant/VariableSwitch
X
NullStatements
X X X X
IF/ELSE X X X X X XCASE X X X X XFOR X X X X
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MethodologyMethodology
Deeply embeddedfunctionality:
– “dark corners”– few vector
sequences in theinput space ableto exercise it
Use RTL fault models to unveil them
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• Approach:– identify “dark corners” - RTL conditions (e.g., IF,
CASE) that highly restrict observability / controllability
– dark corners must be:• targeted by N vectors RTL fault activation /
detection, or• reported as design errors
• Method:– Partial definition of test vectors - masks - which
are the key to “illuminate” each dark corner
MethodologyMethodology
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if ( {pdb2[23:16], pdb2[7:5]} == 11'b00000100_101 )00000100xxxxxx...xx101xxxxxxxxx ……..
if (pdb2[15])==0 /* if W =1 */000001000xxxxxx...x101xxxxxxxxx
……..if ( pdb2[4:2] == 3'b000 )
000001000xxxxxx...x101000xxxxxx ……..
if (pdb2[13:10] == 4'b1000 )000001000x1000x...x101000xxxxxx
• Example:
MethodologyMethodology
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000001000x1000x…x10100xxxxxxx
mask
mi fixed positional bits(mi << n, n input bit words)
RTL_N test pattern: N detection of RTL faults,complete branch coverage
Customizedmask vectors:x randomlysubstitutedby 0s and 1s
MethodologyMethodology
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MethodologyMethodology
RTL FS
Hard RTL faults (low N detection)“dark corners”
RTL descriptionRTL fault list5,000Random vectors
RTL code analysis
Mask generation & nesting
Customised masks +Random vectors
RTL_N test (N detection)
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• RTL fault simulationDesign
RTL
Fault Simulator
RTLsimulation
RTL faultlist gen.
Logic
Layout
RTLFC
N det.(N=0, 1, ...)
Experimental Set-upExperimental Set-up
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• Requirements for methodology validation:
– Realistic Fault Simulator• Multi-level: RTL + logic• compatible with commercial EDA
– Realistic Fault Models• Accurate fault extraction
Experimental Set-upExperimental Set-up
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• Multi-level realistic fault simulationDesign
RTL
Logic
Layout
Fault Simulator Cell Library
layout view
Test view
Fault freemodules
Faultymodule
Logic view
Synthesis view
cell faultsrouting faults
faulty module ...
Experimental Set-upExperimental Set-up
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• Case studies:– ITC99 benchmarks - and– CMUDSP: Add. Gen. Unit Controller (AGU)*,
Prog. Control Unit Controller (PCU);– TORCH: co-processor control (cp0control),
multiply or add PPSum module
• *Different structural synthesis:– area optimization (AREA)– critical path optimization (TIME)
Experimental Set-upExperimental Set-up
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• Realistic Fault Simulation with...
• Vector Generation:– LSA + random used as referenceused as reference
– RTL faults detection no gainsno gains
– LSA + RTL faults not detected by LSA vectors
–– N-detection: RTL faults multiple detectionN-detection: RTL faults multiple detection
Experimental Set-upExperimental Set-up
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• RTL– # lines = 4000– # faults= 600– RTL FC = 95%– undetected:
• bit sa - 2.2%• case dead - 1.7%
• Logic– # gates = 466– # LSA vectors = 129
• Layout– # faults = 2853– undetected:
• BRI AY - 0.6%• BRI AB - 0.5%
Circuit: CMUDSP Module: AGU control (AREA)
14 masks
ResultsResults
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AGU control - AREA
97
97.2
97.4
97.6
97.8
98
98.2
98.4
98.6
0 2000 4000 6000 8000 10000
#vectors
Rea
listi
c F
C [
%]
LSA+Random
LSA+RTL guided
ResultsResults
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AGU control - AREA
95
95.5
96
96.5
97
97.5
98
98.5
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000#vectors
Rea
listi
c FC
[%
]
LSA+RandomLSA+RTL guidedRTL_single+randomRTL_single+RTL guided
RTL single
ResultsResults
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AGU control - AREA
95
95.5
96
96.5
97
97.5
98
98.5
0 2000 4000 6000 8000 10000
#vectors
Rea
listi
c F
C [
%]
LSA+Random LSA+RTL guided
RTL_single+random RTL_single+RTL guided
RTL_10+Random RTL_10+RTL guided
RTL 10
RTL single
RTL masks for dark-corners
ResultsResults
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• RTL– # lines = 4000– # faults= 600– RTL FC = 95%– undetected:
• bit sa - 2.2%• case dead - 1.7%
• Logic– # gates = 580– # LSA vectors = 136
• Layout– # faults = 3315– undetected:
• BRI AB - 1.5%• LOP AY, LOP VDD-X,
BRI AY - 0.5%
Circuit: CMUDSP Module: AGU control (TIME)
14 masks
ResultsResults
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AGU control - TIME
96.5
96.6
96.7
96.8
96.9
97
97.1
97.2
97.3
97.4
97.5
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
#vectors
Rea
listi
c F
C [
%]
LSA(136)+Random
LSA(136) + RTL guided
ResultsResults
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AGU_OPT-TIME
92
93
94
95
96
97
0 2000 4000 6000 8000 10000 12000 14000#vector
Rea
listi
c F
C [
%]
LSA(136)+Random LSA(136) + RTL guided
RTL_single(157) + RTL guided RTL_single(157) + Random
RTL_10(1187) + RTL guided
RTL single
RTL 10
RTL masksfor dark-corners
ResultsResults
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• AGU-control fault simulation in DSP
Layout
Fault Simulation
DSP exceptAGU
control
AGU -- control
Logic
RTL
ResultsResults
Realistic faultcoverage
Abstraction level
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AGU (in DSP)
7576777879808182838485
0 500 1000 1500 2000 2500
#vector
FC
[%]
LSA+RTL_guidedLSA+random
ResultsResults
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• RTL– # lines = 714– # faults= 972– RTL FC = 97%– undetected:
• bit sa0 - 2.5%• if sa false - 0.5%
• Logic– # gates = 640
• Layout– # faults = 3489
Circuit: CMUDSP Module: PCU control (BIST)
6 masks:
4 x 51/350 deterministic bits +
2 x 19/350 deterministic bits
ResultsResults
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PCU_control BIST
90
91
92
93
94
95
96
0 5000 10000 15000 20000
#vectors
Faul
t Cov
erag
e
LFSR
LFSR && RTL restrictions
ResultsResults
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• RTL– # lines = 503– # faults= 110– RTL FC = 100%
• Logic– # gates = 100
• Layout– # faults = 474– undetected:
• BRI AY - 6.8%• LOP AY - 2.5%• BRI YX - 1.7%• BRI AB - 0.6%
Circuit: Torch Module: cp0 control
2 masks
ResultsResults
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Torch cp0control module
83
84
85
86
87
88
0 500 1000 1500 2000 2500
#vector
FC [
%]
rnd 90+10 80+20
50+50 30+5
… 200 000 vect.
ResultsResults
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• RTL– # lines = 96– # faults= 9 912– RTL FC = 99.5%– undetected:
• bit sa - 0.5%
• Logic– # gates = 13 200
• Layout– # faults = 39 682– undetected:
• BRI AY - 0.1%• BRI YX - 0.1%• LOP AY - 0.1%
Circuit: Torch Module: MOA PPsum
3 masks
ResultsResults
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Torch moa_PPS module
95
95.5
96
96.5
97
97.5
98
98.5
99
99.5
100
0 200 400 600 800
vector #
FC
[%
]
randomRTL restricted
ResultsResults
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• single RTL fault detection does notimprove LSA + random
• RTL fault models can be used formultiple purposes:– Design errors diagnosis– Dark corners identification– > useful in verification, test and diagnostic
ConclusionsConclusions
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• Multiple (N) RTL fault detection in darkcorners leads to:– functional test generation for high DC– test application cost minimization– test reuse (weak structural dependence)– amenable to HQ, low energy BIST
ConclusionsConclusions