risc-v community needs peripheral cores · usb, lpddr, pcie, amba but no for clocking circuitry,...
TRANSCRIPT
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@onchipUIS
RISC-V Community needs Peripheral Cores
Elkim Roa
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Good to have an Open ISA. What about Peripheral?
● IP vendors have IP based on previous customer. Hard to get a glue-and-play that works for your SoC. → $$$
● There are some std, such as PHYs: USB, LPDDR, PCIe, AMBA BUTno for clocking circuitry, biasing, GPIOFor instance a simple Power-on-Reset can hit your pocket, just because!
● Buses IP are out there but expensive. Why: Similar to compilers decades ago
Can we do better? We might
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Agenda
1. Why we need more open-std silicon-HW?
2. IC Community can build up peripheral. Our case.
3. Suggestion and take away.
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Case 1: Receiving/Sending Data Bottleneck
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Case 1.1: LowRISC Endeavour
Epiphany-V from Adapteva, 1024-core and 1024-IO running at 150MHz.
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Case 2: Linux Drivers are Still a Pain in the Butt
Most of the open-source drivers exist because reverse-engineering
Open-hardware would translate into quality drivers
There is no standard for hardware abstraction.- Sound card drivers - House Peripheral controller- Graphic drivers - House Peripheral controller (worst)
If standardization is possible, future code will be compatible with any device.● RISC-V core as controller - Nvidia● Register abstractionDriver support with Open-hardware peripherals will work on any OS.
No additional reverse-engineering will be needed if everything follows a standard.
Article title: 11 Reasons Linux Sucks
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Give standard features:- Switching
speed - Current
driving
There is no standard for GPIO.
OpenStandard
GPIO
New ideas can be standardizable!
Standard declarations using Open-hardware GPIO
Implementation driver for all users and companies
Open Standard GPIO
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Developed IP
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Peripheral tied to AMBA Buses
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Pseudo-Synthesized ADC
Std Cell-based High-Speed Strong-Arm Comparators
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RTL
SynthesysDCO
Verilog Gate Level
DACVerilog Gate
Level
NetlistDCO
Placement constraints
DACPlacement constraints
PnR
GDSII
Synthesized CDR and PLL
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USB 3.1 Gen 2
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Analogish Front-End
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ChipScope and Offset Correction
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ChipScope and Offset Correction: Measurements
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PRBS Gen and Checker: Handcrafted FF Std Cell
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LPDDR3 PCS Cracked it. UVM IP.
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Establishing a Common Key
Software: Large computational cost.
HW: Large footprint/Power
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A Light-Weight Mechanism : TPM
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Fully Synthesized: True-Random Noise Generator
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Going Beyond: NVRAM on CMOS
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● Compliance test suite - Functional model → UVM
Open-IP Bus RISC-V core used Provider Repository Functional Model Silicon proven
SPI Rocket/Open-V/Epihany-V
Adapteva github.com/adapteva ✓ ✓
I2C Open-V/Pulp Onchip/Pulp github.com/onchipUIS ✓ ✓
AXI-4.0
APB-4.0
AHB-2.0
USB 2.0 PHY
USB 3.1 PHY
RapidIO
LPDDR3
Suggestion: RISC-V Recommends
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● Don’t get your SoC-idea stuck just because you don’t have regular IP.
● We need more standard Peripherals.
● Don’t reinvent the wheel. We need to join efforts.
Take away
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