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RFIC Design and Testing for Wireless

A Full-Day Tutorial at VLSI Design & Test Symposium

July 23, 2008

Lecture 1: Introduction

s wan . grawa , vagrawa eng.au urn.e

Foster Dai, [email protected]

Auburn University, Dept. of ECE, Auburn, AL 36849, USA

1


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Abstract

This tutorial discusses design and testing of RF integrated circuits

.

have training in that area, those who work on IC design and wish tosharpen their understanding of modern RFIC design and test methods,

and engineering managers. It is an abbreviated version of a one-

semes er un vers y course. pec c op cs nc u e sem con uc or

technologies for RF circuits used in a wireless communications system;

basic characteristics of RF devices linearity, noise figure, gain; RFfront-end desi n LNA mixer fre uenc s nthesizer desi n hase

locked loop (PLL), voltage controlled oscillator (VCO); concepts of

analog, mixed signal and RF testing and built-in self-test; distortion

theory, measurements, test; noise theory, measurements, test; RFIC

.

2


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Objectives

To acquire introductory knowledge about integrated circuits

(IC) used in radio frequency (RF) communications systems.

To learn basic concept of design of RFIC.

.

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Outline

Introduction to VLSI devices used in RF communications

SOC and SIP

Functional components Technologies

Design concepts

Test concepts

Basic RF measurements

Distortion characteristics

Noise SOC testing and built-in self-test (BIST)

4


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References

1. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,

Memory & Mixed-Signal VLSI Circuits, Boston: Springer, 2000.

2. J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and

SiP Devices, Boston: Artech House, 2007.

. . , , ,

Hall PTR, 1998.

4. J. Ro ers, C. Plett and F. Dai, Integrated Circuit Design for High Speed

Frequency Synthesis, Boston: Artech House, 2006.

5. K. B. Schaub and J. Kelly, Production Testing of RF and System-on-a-chip

Devices for Wireless Communications, Boston: Artech House, 2004.

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Schedule

09:30AM 10:00AM Lecture 1 Introduction Agrawal

10:00AM 11:00AM Lecture 2 RF Desi n I Dai

11:00AM 11:30AM Break

13:00PM 14:00PM Lunch14:00PM 15:00PM Lectures 4 RF Testing I Agrawal

15:00PM 15:30PM Break

15:30PM 17:30PM Lectures 5-7 RF Testing II Agrawal

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An RF Communications System

ADC

Superheterodyne Transceiver

LNA LOVGA PhaseSplitter

or(DS

P)

90

Du

plexe

LO

alP

roces

ADC

PALOVGA Phase

SplitterigitalSign

0

D

DAC

90

7

RF IF BASEBAND


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Components of an RF System

Radio frequency Duplexer

Mixed-signal ADC: Analog to digital

LNA: Low noise amplifier

PA: Power amplifier

RF mixer

converter

DAC: Digital to analog

converter

Local oscillator

Filter

Digital Di ital si nal rocessor

Intermediate frequency VGA: Variable gain amplifier

(DSP)

o u ator Demodulator

Filter

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Duplexer

TDD: Time-Division

Du lexin

FDD: Frequency-

Division Du lexin

Same Tx and Rx frequency RF switch (PIN or GaAs FET)

Tx to Rx coupling (-50dB) More loss (3dB) than TDD

Less than 1dB loss Adjacent channel leakage

frRx

frft

TxTx

10

TDD command ft


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LNA: Low Noise Amplifier

Amplifies received RF signal

Typical characteristics:

Noise figure 2dB

IP3 10dBm

Input and output impedance 50

Reverse isolation 20dB a y ac or >

Technologies:

CMOS

, .

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PA: Power Amplifier

Feeds RF signal to antenna for transmission


Output power +20 to +30 dBm

Efficiency 30% to 60%

IMD 30dBc

Supply voltage 3.8 to 5.8 V

Gain 20 to 30 dB

Power control On-off or 1-dB steps

Stability factor > 1

Technologies:

GaAs

e

Reference: Razavi, Chapter 9. 12


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Mixer or Frequency (Up/Down) Converter

Translates frequency by adding or subtracting local oscillator

(LO) frequency


Noise figure 12dB

m

Gain 10dB

Input impedance 50 Port to port isolation 10-20dB

Tecnologies:

Bipolar MOS

, .

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Passive Mixer

V(IF)nFET

V(RF)

RL

V(LO)

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Active Mixer

VDD

V(IF)

V(LO)

V(RF)

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LO: Local Oscillator

Provides signal to mixer for down conversion or upconversion.

Im lementations:

Tuned feedback amplifierRing oscillator

Phase-locked loop (PLL)

Direct digital synthesizer (DDS)

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Phase Splitter

Splits input signal into two same frequency outputs that differ

in phase by 90 degrees.

Used for image rejection.

R

C

Vin

Vout_1

RC

ou _

17


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SOC: System-on-a-Chip

All components of a system are implemented on the same VLSI

chip.

Requires same technology (usually CMOS) used for allcomponents.

Components not implemented on present-day SOC:

Antenna

Power amplifier (PA)

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Phase Lock Loop Integer-N Frequency Synthesizer

Transfer function

that controls

loop dynamics (LPF)

Phase

Comparator reffNfo =

r

+ F(s)F(s)reference

(input) ffb

N

on ro a e gna

Source (VCO)Divider

fo synthesized signal

(output)Digital signal

to control the

value of N

Nis an integer the minimum step size = frto get a smaller step size, the reference

frequency must be made smaller N must be higher in order to generate the same fo

Frequency synthesizer design I (PLL), FDAI, 2008 21

- .


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Fractional-N Concept

If the loop divisorNis a fractional number, e.g., N=K/F, where K and F are

integer numbers the minimum step size = fr /F can achieve small step

size without lowering the reference frequency loop divisor N can be small

in order to generate the same fo better phase noise (in-band noise

magnified 20logN times by the loop).

output transits only at the input clock edge we can only generate integer

frequency divider!!

Dual-modulus divider P/P+1: by toggling between the two integer division

ratios, a fractional division ratio can be achieved by time-averaging the divider

output. As an example, if the control changes the division ratio between 8 and

1.81998

=+

=N

,

process repeats itself, then the average division ratio will be:



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Fractional-N Synthesizer with a Dual Modulus Prescaler

Transfer function

that controls

+=

++=

F

KP

R

f

F

KFPKP

R

ff rro

)()1(

fr

R + F(s)F(s)

oop ynam cs

RFfr=SizeStep

Dual Modulus

Divider

Controllable Signal

Source (VCO)

fb

Cout

+

CLK

Carry

out bitfo

synthesized

signal

(output)

+z-

log2F+

Fractional

Accumulator

yI

yI-1

F

Kff clkC =out



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Fractional Accumulator Operations

F

Kff clkC =out

clock0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Accumulator operations with F= 8, K= 1

yi 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2

yi-1 NA 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1out

Accumulator operations with F= 8, K= 3

clock cycle iyi 0 3 6 1 4 7 2 5 0 3 6 1 4 7 2 5 0 3 6

yi-1 NA 0 3 6 1 4 7 2 5 0 3 6 1 4 7 2 5 0 3


Cout 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0


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Fractional-N Frequency Synthesizer with a

Multi-Modulus Divider

n

n

n

n

n PPPPN 222...2 112

2

1

1MMD ++++=

fr

R + F(s)F(s)

Transfer function

that controls

loop dynamics (LPF)

Multi-Modulus

Divider

MMD

Controllable Signal

Source (VCO)

fb

+=

K

I

f

fr

o

+ Integer divisorI

+

+

Total divisorI+K/F

control nbito

rac ona v sor

+z-1 Klog2F

Cout

+

+

Fractional

Accumulator

CLK

1bit



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PLL Frequency Synthesizer

( )oRe Ksv = PD)( ( )oRPDCPd KKi = ( )( )1 1CPPD RsCKKv oR +=

UPid

I

VDD

R(s)Kphase

vc(s)Loop Filter

)1(21 RsCCCs s++

21

21

CC

CCCs

+=

DN

I

R

C1

C2

o(s) Kvco

PFD

rys a

Oscillatore

2

C

CRK Sphase

Gain

Magnitude

Response

Ks

Ns

VCODivider

21

21

CC

CCCS

+=where1RC SRC

1

Phase

Phase

Response

cvKVCOVCO =

ssvc )(=

sK

NvcVCOo 1 =

1

1

RCSRC

1

Frequency synthesizer design I (PLL), FDAI, 200829


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Dual Modulus Prescaler 2/3 Cell

mod in=1 and C=1 Fo/Fin=1/3; mod in=1 and C=0 Fo/Fin=1/2mod in=0 and p=x Fo/Fin=1/2

Dualmodulus



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Phase/Frequency Detector

D Q Phir

1

rst_fr

active high

lock detectreset

activelo polarity

if low, KV>0

if high, KV


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2nd Order Passive Loop Filters

IPPFD

Charge Pump

R

UP

DN

+

-ICP

oop er

VCP

N

1 2nphase

( )( )1 1RsCsF

+=

The 2nd-order filter is the

hi hest order assive RC21 s

21

21

CC

CCCs

+=

filter that can be built withoutseries resistors between the

charge pump and the VCO


tune line


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PLL Phase Noise Sources

REF

R PD+LPF

k G kVCO/s

VCO

( ) skGksG VCOLPFPD=

%R+ PD+ +VC

OLPF

output

S0+

LPin band noise HPout of band noiseNTF

REF

%N+

Close loop transfer function

N

Total output noise power spectral densityVCOLPFPD

VCOLPFPD

kGkNsNG +=

+ /1

( ) 220 /1 1/1

++

+

++++= NGSNGGk

SSSS

R

SfS VCO

PD

LPFPDNRREF

HPFLPF


+

=

+ NGNNG /1

1/1


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Simulated PLL Phase Noise Sources

3. Crystal/CP Intercept

2. CP/VCO Interce t

CPnoiseCPnoiseCrystalnoi

Crystalnoi

Dividernoise

Dividernoise

1. /VCO Intercept

PD noise

nois

e

nois

e

VCOnoise

VCOnoise



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Comparison of Measured and Simulated


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p

Phase Noise

Bc/Hz)

-

-70

-80

-90

Band

Phase

Noise

Phase

Noise

3.2- 0.44rms 0.50rms

Ph

aseNoise(d -100

-110

-120

-130

.

4.1-

4.3GHz

0.50rms 0.535rms

0.1 1.0 10 100 1000 10000

-140

-150

-160

Parameter Value

C1 3nF

C2 600pF



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Ph N i S ifi ti f O ill t


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Phase Noise Specification of Oscillators

Phase noise. We desire accurate periodicity with all signal power concentrated in one

Example of oscillator

periodic waveforms

. ,real oscillators have less than perfect spectral purity and thus they develop skirts.

Power in the skirts is evidence of phase noise, Phase noise is any noise that chargesthe frequency or phase of the oscillator waveform. Phase noise is given by:

Spectrum of a

typical oscillator

noise floor 0 0

Where Po is the power in the tone at the frequency of oscillation and No is the

noise power spectral density at some specified offset from the carrier. Phase

fo


no se s usua y spec e n c z, mean ng no se a - z an w measure

in decibels with respect to the carrier.


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Adding Negative Resistance Through


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Feedback to Resonator

L C rpa) b)

L C -rn-RnRp

The addition of negative resistance to the circuit to overcome

losses in a a arallel resonator or b a series resonator.

H1(s)+

Vin(s) Vout(s)

H2(s)


52

.


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Negative Resistance of Colpitts Amplifier


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Negative Resistance of Colpitts Amplifier

( ) )( 221 jXvgjXjXiv beminin ++=

v

Negative Impedance, if X1and X2 are the same type

2121 jXgi

Z m

in

nin ++==

11gm

2121

2 CjCjCCin

Load reactance needs

to equal j(X1+X2)add an inductor

To start the oscil lation,21

2

21

CCRg

g

Lm

Lm

>

>

2

1

213

11121

+=

CCLfosc

Oscillation frequency


56

Impedance Transform for LC Oscillator


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Impedance Transform for LC Oscillator

Drive lowimpedance

G < 1Increase theimpedance

seen by tank

Impedanceseen by

tank =

n gm


57

Passive Impedance Transformer


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Passive Impedance Transformer

Impedanceseen by tank

=(1+C1/C2)2/gm

Impedance

seen by tank =

+ 2For ne li ible m

loading on thetank, C1 > 10C2 needs a


58

large cap.


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Negative Resistance of Gm Oscillator


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g

ii

v2re2

gm2v

2

re1

vi

v1

gm1v1

2211 vgvg

v

i mmi

i==

21 ee

Both transistors are biasediZ

2=

, m

Condition for oscillation is thatp

mR

g2

>


60

where Rp is the equivalent parallel resistance of the resonator.

VCO Mathematical Model


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Output frequency of an ideal VCO: wout = wFR+ Kvco Vc

t

FR vco c-

Open loop Q : Q = (w0/2) |d/dw |

Where w0 is the center frequency is the phase of open loop transfer function


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Oscillator Phase Noise Leesons Equation


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If feedback path is unity, then H1=H, and since |H|=1 near resonance

22

2

0

2

4

)(

=

sN

sNout

Phase noise is quoted as an absolute noise referred to the carrier power22

( )

==S

in

S

out

PQPPN

222

01

. If the transistor and bias were noiseless, then the only noise present

would be due to the resonator losses. The transistors and the bias will

kTsNin =2

)(


65



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c ve ev ce no se: If is the fraction of cycle for which the

transistors are completely switched, int is thenoise current in ected into the oscillator from the

L

C

bias during this time.

During transitions (1- ), the transistors act like anamplifier, and collector shot noise icn usually

Q2Q1

I.

( ) ++= 12

)(2

22

pcn

pnt

in RiRi

kTsNRp is the

equivalent

c - m sc ator

resistance of the

tank.

Resonator loss

(source)Bias noise Transistor shot

noise

( )

kT

Ri

kT

RiF

pcnpnt

++=

1

21

22

( )

=

Ps

FkT

Q

HPN

22

2

01




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It has been assumed that flicker noise is insignificant at the frequenciesof interest. This may not be the case for CMOS designs. Ifc representsthe flicker noise corner where flicker noise and thermal noise are equal,

phase noise is given by

( )

+

=

c

Ps

FkT

Q

HPN 1

22

2

01

2

Assuming unity feedback, oscillator output spectrum density

ase no se a

Df from carrier 30 dB/decade

20 dB/decade

+

+=fQfP

fS c

Ls

VCO 12

12

log10)( 0

Thermal noise floor


c


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Testing


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Definition: Having designed and fabricated a device, testing

must determine whether or not the device is free from any

manufacturing defect.

Testing is distinctly different from verification, which checks

the correctness of the design.

Forms of testin : Production testing

Characterization testing

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Method of Production Testing


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Automatic Test Equipment (ATE) System

Test

ProgramHandler

(Feed robatics,

Binning)

DSP

RF sourcesUser

Interface

Contactors

Probe cards

Load boards

74


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Scattering Parameters (S-Parameters)


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An RF function is a two-port device with Characteristic impedance (Z0):

0 = or w re ess commun ca ons ev ces

Z0 = 75 for cable TV devices

S-Parameters of an RF device

11 S22 : output return loss or output reflection coefficient

S : ain or forward transmission coefficient

S12 : isolation or reverse transmission coefficient S-Parameters are com lex numbers and can be ex ressed in

decibels as 20 log | Sij |78


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Application of S-Parameter: Input Match


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Example: In an S-parameter measurement setup, rms value of

input voltage is 0.1V and the rms value of the reflected voltage

wave is 0.02V. Assume that the output of DUT is perfectly

matched. Then S11 determines the input match:

S11 = 0.02/0.1 = 0.2, or 20 log (0.2) = 14 dB.

Suppose the required input match is 10 dB; this device

.

Similarly, S22 determines the output match.

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Harmonic Measurements


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Multiples of the carrier frequency are called harmonics.

Harmonics are enerated due to nonlinearit in semiconductor

devices and clipping (saturation) in amplifiers.

measured to verify that a manufactured device meets the

s ecification.

86


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PAE Example

F ll i t bt i d f RF


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Following measurements are obtained for an RF power

amplifier:

RF Input power = +2dBm

RF output power = +34dBmDC supply voltage = 3V

DUT current = 2.25A

PAE is calculated as follows:

PRF(input) = 0.001 102/10 = 0.0015W

RF . .

Pdc = 3 2.25 = 6.75W

= =. . . . .

89

Automatic Gain Control Flatness(SOC DUT)

T t d d


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Tester pseudocode:

Set up input signal to appropriate frequency and power level

Set up output measurement equipment to receive output

signal when triggered rogram o rs ga n eve an r gger rece ver

Cycle SOC AGC to next gain level

Cycle to next gain level and repeat though all levels

Power at ith gain level = 20 log [VR(i)2 + Vi(i)2]1/2 + 13 dBm for50 characteristic im edance, where V and V are the

measured real and imaginary voltages90

AGC Other Characteristics

0 6 Ideal


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0.6

0.4(dBm) Ideal

0.2

0.0Power

0 200 400 600Time (s)

0.6

0.4(dBm) Actual measurement

Overshoot

0.2

0.0Power Missing

gain step

91

0 200 400 600Time (s)


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July 23, 2008

Lecture 5: Testing for Distortion

Vishwani D. Agrawal


94


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Linear and Nonlinear Functions

f(x) f(x)


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f(x) f(x)

x

s ope = a

b xb

f(x) = ax + b f(x) = ax2 + b

x

slope = a

96

f(x) = ax


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Effect of Nonlinearity on Frequency

Consider a transfer function vo = a0 + a1 vi + a2 vi2 + a3 vi3


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Consider a transfer function, vo a0 + a1 vi + a2 vi + a3 vi

Let v = A cos t

Using the identities ( = 2f):

2 = +

cos3 t = (3 cos t + cos 3t)/4

,

v = a + a A2/2 + (a A + 3a A3/4) cos t

+ (a2A

2

/2) cos 2t + (a3A

3

/4) cos 3t

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Linear and Nonlinear Circuits and Systems

Linear devices:


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Linear devices: All frequencies in the output of a device are related to input

by a proportionality, or weighting factor, independent of

power level. ,

in the input.

A true linear device is an idealization. Most electronic

devices are nonlinear.

Nonlinearity in amplifier is undesirable and causesdistortion of signal.

Nonlinearity in mixer or frequency converter is essential.100

Types of Distortion and Their Tests

Types of distortion:


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yp Harmonic distortion: single-tone test

Gain compression: single-tone test

Intermodulation distortion: two-tone or multitone test ource intermo u ation istortion

Cross Modulation

Testing procedure: Output spectrum measurement

101

Harmonic Distortion

Harmonic distortion is the presence of multiples of a


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p pfundamental frequency of interest. Ntimes the fundamental

frequency is called Nth harmonic.

Disadvantages:

Waste of power in harmonics.

Interference from harmonics.

Measurement:

Single-frequency input signal applied.

Amplitudes of the fundamental and harmonic frequencies

are analyzed to quantify distortion as:

o a armon c s or on

Signal, noise and distortion (SINAD) 102

Problem for Solution

Show that for a nonlinear device with a single frequency input


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g q y pof amplitude A, the nth harmonic component in the output

always contains a term proportional to An.

103

Total Harmonic Distortion (THD)

THD is the total power contained in all harmonics of a signal


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p gexpressed as percentage (or ratio) of the fundamental signal

power.

THD(%) = [(P2 + P3 + ) / Pfundamental ] 100%

Or THD(%) = [(V22 + V3

2 + ) / V2fundamental ] 100%

Where P2, P3, . . . , are the power in watts of second, third, . . . ,

harmonics, respectively, and Pfundamental is the fundamental signal power,

And V2, V3, . . . , are voltage amplitudes of second, third, . . . , harmonics,

respectively, and V is the fundamental signal amplitude.

Also, THD(dB) = 10 log THD(%),

104


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Signal, Noise and Distortion (SINAD)

SINAD is an alternative to THD. It is defined as


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SINAD dB = 10 lo S + N + D / N + D

where

=

N = noise power in watts

D = distortion (harmonic) power in watts

SINAD is normally measured for baseband signals.

106

Problems for Solution

Show that SINAD (dB) > 0.


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Show that for a si nal with lar e noise and hi h distortion

SINAD (dB) approaches 0.

,

increases SINAD will drop.

absence of distortion.

107

Gain Compression

The harmonics produced due to nonlinearity in an amplifierd th f d t l f t t ( d i )


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reduce the fundamental frequency power output (and gain).

This is known as gain compression.

As input power increases, so does nonlinearity causing greater

gain compression.

A standard measure of Gain com ression is 1-dB com ression

point power level P1dB, which can be

Input referredfor receiver, or

Output referredfor transmitter

108

Linear Operation: No Gain Compression


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time timeAmplitud

Amplitud

LNA

Bm)

Bm)

frequency

Power(

f1frequency

Pow

er(

f1

109

Cause of Gain Compression: Clipping


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time timeAmplitud

Amplitud

LNA

Bm)

Bm)

frequency

Pow

er(

f1frequency

Pow

er(

f1 f2 f3

110

Effect of Nonlinearity

Assume a transfer function, vo = a0 + a1 vi + a2 vi2 + a3 vi3


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Let v = A cos t

Using the identities ( = 2f):

2 = +

cos3 t = (3 cos t + cos 3t)/4

, vo = a0 + a2A

2/2 + (a1A + 3a3A3/4) cos t

+ (a A2/2) cos 2t + (a A3/4) cos 3t

111

Gain Compression Analysis

DC term is filtered out.


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For small-si nal in ut A is small

A2 and A3 terms are neglected

vo = a1A cos t, small-signal gain, G0 = a1

Gain at 1-dB compression point, G1dB = G0 1

-P1dB(output) P1dB(input) = G1dB = G0 1

112


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Testing for Gain Compression

Apply a single-tone input signal:1 Measure the gain at a power level where DUT is linear


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1. Measure the gain at a power level where DUT is linear.

2. Extrapolate the linear behavior to higher power levels.

3. Increase input power in steps, measure the gain andcompare o ex rapo a e va ues.

4. Test is complete when the gain difference between steps 2

.

Alternative test: After step 2, conduct a binary search for 1-dB

.

114


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Intermodulation Distortion

Intermodulation distortion is relevant to devices that handlemultiple frequencies


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multiple frequencies.

Consider an input signal with two frequencies 1 and 2:

= +

Nonlinearity in the device function is represented by

vo = a0 a1 vi a2 vi a3 vi neg ec ng g er or er erms

Therefore, device output is

vo = a0 + a1 (A cos 1t + B cos 2t) DC and fundamental

+ a2 (A cos 1t + B cos 2t)2 2ndorder terms

+ a3 (A cos 1t + B cos 2t)3 3rdorder terms

116


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Two-Tone Distortion Products

Order for distortion product mf1 nf2 is |m| + |n|

N b f di t ti d t F i


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Nunber of distortion roducts Fre uencies

Order Harmonic Intermod. Total Harmonic Intrmodulation

2 2 2 4 2f 1 , 2f2 f1 + f2 , f2 f11 , 2 1 2 , 2 1

4 2 6 8 4f 1 , 4f2 2f1 2f2 , 2f2 2f1 , 3f1 f2 , 3f2 f1

5 2 8 10 5f 5f 3f 2f 3f 2f 4f f 4f f

6 2 10 12 6f 1 , 6f23f1 3f2 , 3f2 3f1 , 5f1 f2 , 5f2 f1 ,4f1 2f2 , 4f2 2f1

7 2 12 14 7f 1 , 7f2

1 2 , 2 1 , 1 2 , 2 1 ,6f1 f2 , 6f2 f1

N 2 2N 2 2N Nf 1 , Nf2 . . . . .

118


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Second-Order Intermodulation Distortion


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itud

e

itud

e

DUTAmpl

Ampl

1

frequency1 2

frequency1 2 1 2

f2

120


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Test for IP3

Select two test frequencies, f1 and f2, applied in equalmagnitude to the input of DUT.


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Increase input power P0 (dBm) until the third-order products are

well above the noise floor.

Measure output power P1 in dBm at any fundamental frequency

and P in dBm at a third-order intermodulation fr uenc .

Output-referenced IP3: OIP3 = P1 + (P1 P3) / 2

- 0 1 3

= OIP3 G

Because, Gain for fundamental frequency, G = P1 P0124


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Example: IP3 of an RF LNA

Gain of LNA = 20 dB RF si nal fre uencies: 2140.10MHz and 2140.30MHz


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Second-order intermodulation distortion: 400MHz; outside

.

Third-order intermodulation distortion: 2140.50MHz; within the

.

Test:

= , 0 ,

Output power, P1 = 30 + 20 = 10 dBm

Measured third-order intermodulation distortion power, P3 = 84 dBm

OIP3 = 10 + [( 10 ( 84))] / 2 = + 27 dBm

IIP3 = 10 + [( 10 ( 84))] / 2 20 = + 7 dBm126


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What is Noise?

Noise in an RF system is unwanted random fluctuations in adesired signal.


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Noise is a natural phenomenon and is always present in the

environment.

Effects of noise:

Interferes with detection of si nal hides the si nal .

Causes errors in information transmission by changing

signal.

Sometimes noise might imitate a signal falsely.

All communications system design and operation must account

for noise.130


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Thermal Noise

Thermal (Johnson) noise: Caused by random movement of

electrons due to thermal energy that is proportional to

empera ure.


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empera ure.

Called white noise due to uniform PSD over all frequencies.

Mean square open circuit noise voltage across R resistor

[Nyquist, 1928]:

v2 = 4hfBR / [exp(hf/kT) 1]

Where

Planks constant h = 6.626 1034 J-sec

Frequency and bandwidth in hertz = f, B

o zmann s cons an = .

Absolute temperature in Kelvin = T 132


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Measuring Noise

Expressed as noise power density in the units of dBm/Hz. Noise sources:


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Resistor at constant temperature, noise power = kTB W/Hz.

Avalanche diode

Noise temperature:

Tn = (Available noise power in watts)/(kB) kelvins

Excess noise ratio (ENR) is the difference in the noise output

between hot (on) and cold (off) states, normalized to reference

thermal noise at room temperature (290K):

ENR = [k( Th Tc )B]/(kT0B) = ( Th/ T0) 1

Where noise output in cold state is takes same as reference.

10 log ENR ~ 15 to 20 dB 135

Signal-to-Noise Ratio (SNR)

SNR is the ratio of signal power to noise power.

GSi/Ni So/No


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In ut si nal: low eak ower Out ut si nal: hi h eak ower

i i o o

good SNR poor SNR

)

So/No

wer(dB

i i

Noise floorP

136Frequency (Hz)


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Cascaded System Noise Factor

Friis equation [Proc. IRE, July 1944, pp. 419 422]:


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F2 1 F3 1 Fn 1

Fsys = F1 + + + + 1 1 2 1 2 n 1

Gain = G1Noise factor



Gain = GnNoise factor

1 2 3 n

138

Measuring Noise Figure: Cold Noise Method

Example: SOC receiver with large gain so noise output ismeasurable; noise power should be above noise floor of

measuring equipment


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measuring equipment.

Gain G is known or previously measured.

Noise factor, F = No/ (kT0BG), where

N is measured out ut noise ower noise floor

B is measurement bandwidth

At 290K, kT0 = 174 dBm/Hz

Noise figure, NF = 10 log F

= N dB 174 dBm/Hz B dB G dB

This measurement is also done using S-parameters.139


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Measuring Noise Factor: Y Factor Method

Noise source provides hot and cold noise power levels and ischaracterized by ENR (excess noise ratio).

Tester measures noise power is characterized by its noise


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Tester measures noise power, is characterized by its noise

factor F2 and Y-factor Y2.

Device under test (DUT) has gain G1 and noise factor F1.

Calibration: Connect noise source to tester, measure output

power for hot and cold noise inputs, compute Y and F .

Measurement: Connect noise source to DUT and tester

cascade, measure output power for hot and cold noiseinputs, compute compute Y12, F12 and G1.

Use Friis equation to obtain F1. 141

Calibration

Noise

source

Tester

(power meter)

ENR F2, Y2


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= c ,

Nh2 = measured power for hot source

N = measured ower for cold source

F2 = ENR / (Y2 1)

142


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Effects of Phase Noise

Similar to phase modulation by a random signal.

Two t es:

Long term phase variation is called frequency drift.


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Long term phase variation is called frequency drift.

Short term phase variation is phase noise.

Definition: Phase noise is the Fourier spectrum (power spectral

density) of a sinusoidal carrier signal with respect to the carrier

power.

L f = P /P as ratio

= Pn

in dBm/Hz Pc

in dBm (as dBc)

-

Pc is RMS power of the carrier146

Phase Noise Analysis

V + t sin t + t = V + t sin t cos t + cos t sin t

( ) ( ) ( )


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[V + (t)] sin t + [V + (t)] (t) cos t

In-phase carrier frequency with amplitude noise

White noise (t) corresponds to noise floor

Quadrature-phase carrier frequency with amplitude and phase noiseShort-term phase noise corresponds to phase noise spectrum

Phase spectrum, L(f) = S(f)/2

Where S(f) is power spectrum of(t)

147

Phase Noise Measurement

Phase noise is measured by low noise receiver (amplifier) andspectrum analyzer:

Receiver must have a lower noise floor than the signal noise


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floor.

oca osc a or n e rece ver mus ave ower p ase no se

than that of the signal.

(dBm)

Signal spectrum

P

ower

Receiver noise floor

Receiver phase noise

148Frequency (Hz)


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y g y p

July 23, 2008

Lecture 7: ATE and SOC Testing

Vishwani D. Agrawal


152

Automatic Test Equipment (ATE)

ATE provides test facility for: Digital and memory devices

Analog devices (analog instrumentation)

RF d i (AWG bit f t LNA


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RF devices (AWG arbitrary waveform generators, LNA,

no se source, sources, ers, power

measurement units, Spectrum analyzer)

-, ,

Cost of ATE: $500,000 to $2M, or higher

es ng cos o c p ~ cen s secon

153


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Testing Cost

Tester time per year: T = 365 24 3600 0.6 = 18,921,600 s

Number of devices tested per year:


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NT = T/(1.5 + 1.0) = 7,568,640 Number of good devices produced per year:

N = NT Yield = 7,568,640 0.8 = 6,054,912

Testing cost per year:

C = (1,000,000 + 250,000)/5 = 250,000 dollars

Testing cost per device shipped:

Cost = C/N = 4.13 cents

156

Reducing Test Cost

Ping-pong testing: Use the same ATE with multiple handlers.

Multisite testin : Test multi le chi s to ether t icall 4 16 . . .

Built-in self-test (BIST): Applicable to SOC and SIP devices.


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- .

157

BIST for a SOC ZIF Transceiver

ADC

LNA LOPhase

Splitter(D

SP)


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o

r

90

Duplexe

lProces

ADC

TA

PALOPhase

Splitter gitalSig

n

0

Di

DAC

90

SOC

158RF BASEBAND

ZIF SOC BIST

Test implemented at baseband.

Loopback between A/D and D/A converters.

DSP implemented with digital BIST.

Test amplifier (TA) implemented on chip; is disabled during normal


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Test amplifier (TA) implemented on chip; is disabled during normal

operation.

A test procedure:

.

Apply RF BIST:

Pseudorandom bit sequence generated by DSP

pconver e y ransm er c a n an app e o rece ver roug

Down converted signal compared to input bit sequence by DSP to

analyze bit error rate (BER)

BER correlated to relevant characteristics of SOC components

Advantage: Low tester cost. Disadvantage: Poor diagnosis. 159


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Outline

Overview of direct digital synthesizers (DDS)

3rd order inter-modulation roduct IP3

BIST architecture


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Output response analyzer

Implementation in hardware

IP3 Measurements

164Analog and mixed signal testing, FDAI, 2008


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Mathematical Foundation

Input 2-tone:

x(t)=A1cos 1t+ A2 cos 2t Output of non-linear device:

y(t)=0+1x(t)+2x2(t)+3x

3(t)+


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Substituting x(t) into y(t):

y(t) = 2(A12+A2

2)2 2 2 2 1 1 3 1 1 2 1 1 2 3 2 1 2 2

+2(A12cos21t+A22cos22t)+ 2A1A2[cos(1+2)t+cos(1-2)t]

11AA

+ 3[A1

3cos31t+A22cos32t]+ 3{A1

2A2[cos(21+2)t+cos(21-2)t]+A A 2[cos(2 + )t+cos(2 - )t]}

33AA22

11 22 2222--112211--22168Analog and mixed signal testing, FDAI, 2008

3rd order Intercept Point (IP3)

IP3 is theoretical input power point where 3IP3 is theoretical input power point where 3rdrd--order distortionorder distortion

and fundamental output lines interceptand fundamental output lines intercept

erer

IIPIIP33[[dBmdBm]=]= +P+Pinin [[dBmdBm]]22


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AAputPo

putPo

(OIP3)

(OIP3)

IM3IM3 20lo 20lo AA33

with spectrum analyzerwith spectrum analyzer

33AA22PPIP3IP3 20log(20log(11A)A)O

uOu

fundamentalfundamental

freqfreq

11 22 2222--112211--22

PP

(IIP3)(IIP3)P/2P/2 169Analog and mixed signal testing, FDAI, 2008


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Actual 2-tone IP3 Measurement utputs o an ta en w t scope rom our exper mentautputs o an ta en w t scope rom our exper menta

hardware implementationhardware implementation

analyzeranalyzer

For BIST we need an efficient output response analyzerFor BIST we need an efficient output response analyzer


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DAC output x(DAC output x(tt):):

PP

DUT output y(DUT output y(tt):):

171

Analog and mixed signal testing, FDAI, 2008 171


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DC1Accumulator

y(y(tt) x) x ff22 DCDC11 AA222211

Ripple in slope due to lowRipple in slope due to low 11AAXX

y(y(tt))

DCDC11

Longer accumulationLonger accumulation

reduces effect of ripplereduces effect of ripple

33AA22ff22


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Simulation ResultsSimulation Results

Actual Hardware ResultsActual Hardware Results

ff22 22ff22--ff11

80

100

120Millions

20

40

60slope = DCslope = DC11

AA2222

11

0

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50) 173Analog and mixed signal testing, FDAI, 2008

DC2Accumulator

y(y(tt) x) x ff22 DCDC2233//88AA11

22AA222233

Ripple is bigger for DCRipple is bigger for DC22 AAXX

y(y(tt))

DCDC22

Test controller needed toTest controller needed to

obtain DCobtain DC22 at integralat integral

multi le ofmulti le of 22

33AA22PP

22ff22--ff11


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multi le ofmulti le of 22 --Simulation ResultsSimulation Results

Actual Hardware ResultsActual Hardware Results

freqfreqff22 22ff22--ff11

15

20

Millio

ns

slope = DCslope = DC22

== 33//88AA1122AA2222335

10

-5

0

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50) 174

Analog and mixed signal testing, FDAI, 2008

BIST-based P Measruement DCDC11 & DC& DC22 same proportionality to power atsame proportionality to power at ff22 & 2& 2ff22--ff11

Only need DCOnly need DC11 & DC& DC22 from accumulators to calculatefrom accumulators to calculate

= og= og 11 ogog 22

Simulation ResultsSimulation Results Actual Hardware ResultsActual Hardware Results


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50

60

20

30

40

0

10

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50)


BIST Architecture BISTBIST--based IP3 measurementbased IP3 measurement

Reduce circuit by repeating test sequence for DCReduce circuit by repeating test sequence for DC22

--

x(x(tt)=)=coscos((ff11)+)+coscos((ff22),),

DACDAC DUTDUT ADCADC

x(x(tt)=)=coscos((ff22))


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DACDAC DUTDUT ADCADC

LUT1LUT1ff11

AccumAccum y(y(tt))

XXTest Pattern GeneratorTest Pattern Generator

AnalyzerAnalyzer

LUT2LUT2 AccumAccumff22

AccumAccumDC1DC1

LUT3LUT322ff22--ff11 AccumAccum DC2DC2AccumAccum

FreqFreq

RespResp



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Hardware Results Spectrum analyzerSpectrum analyzer

PP1414

BIST measuresBIST measures PP 1414

25)

15

20

a

_P(d


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15a

5

10D

el

1.5

tage(%)1 201 401 601 801 1001 1201

Clock Cycles (x100)

0

0.5Percen

P distribution for 1000P distribution for 1000

BISTBIST measurementsmeasurements13.68 13.77 13.87 13.96 14.05 14.14 14.24

Measured Delta_P(dB)

mean= . ,mean= . , = .= .


More Hardware ResultsSpectrum analyzerSpectrum analyzer

100

BIST measuresBIST measures PP 2222

PP2222

60

a

P(

dB

l


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a

20De

1 501 1001 1501 2001 2501Clock Cycles (x50) 1.5

2

age(%)

0.5

P

ercent

P distribution for 1000P distribution for 1000

BIST measurementsBIST measurements16.30 18.94 21.58 24.23 26.87 29.51

Measured Delta_P (dB)

mean= . ,mean= . , = .= .



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rfic agr dai all power

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