REXAPP

Bilal Saqib

REXAPP

Radio EXperimentation And Prototyping Platform Based on NOC

REXAPP Compiler

Requirements for REXAPP Capacity

Computational, storage and interconnect capacity to match the expected needs of SDRs

Scalability For computational, storage and interconnect

capacity. The key component in providing this scalability would be the NOC architecture that would allow seamless addition of intra-chip and inter-chip capacity

Requirements for REXAPP Flexibility

in terms of different options to interface to RF Front ends, external debug systems and SDRAM memories

Modularity REXAPP will be modular in its architecture and

implementation methodology, so that enhancing REXAPP architecture would be a predictable and structured incremental engineering exercise

Requirements for REXAPP

Experimentation All REXAPP elements will be highly

configurable and parametrisable to control their behavior for experimentation. Experimentation, monitoring, and debugging for algorithmic development, dimensioning, performance, and power optimization

Granularity/Generality of REXAPP

Neither a fine grain architecture like FPGAs nor a fully coarse grain architecture like general purpose process

Rather comprised of hardware kernels which are a trade off between fine and coarse grain architecture

Generality is covered y having sufficiently large number of different Kernels to fulfill the functionality of SDRs

NOC Tile

NOC Tiles implement Application Domains and will be realized as a VLSI chip

NOC Tiles are composed of NOC elements Kernels are primary building blocks in NOC Tiles

NOC elements communicate with each other by 2 backbone packet switching, chip-level interconnects 1 for high bandwidth memory and data communication 1 for low bandwidth control and configuration traffic

NOC Tile

Beside Kernels, NOC elements also implement interface functionality External memory interface for DDR2

memories for bulk storage and flash memories for storage of configuration data between usage sessions

RF/Analog interface elements would enable connecting external RF/Analog front-ends to the NOC tiles for creating a complete radio

NOC Tile

There would be some NOC elements for debug and monitoring Hooks will be included to collect data at

internal nodes at speed and bring the data out without disturbing the normal execution

There will be triggers and storage for this purpose

NOC Tile

Lastly, a NOC element for controlling and orchestrating the functioning of NOC tile in the form a RISC processor and a multi-purpose scratch pad memory(ies) will also be included

NOC Tile

External Memory Interface

RFFront End Interface

Memory DataNOC Switch

Control DataNOC

Switch

Kernel

Inter-chip NOCReplicator

ScratchPadMemory

ControllerRISC Processor

External Memory Interface

RFFront End Interface

Memory DataNOC Switch

Control DataNOC

Switch

Kernel

Inter-chip NOCReplicator

ScratchPadMemory

ControllerRISC Processor

Conceptual view of a NOC tile

REXAPP

Inter-chip interface replicates the internal NOC interconnect at chip boundary for inter-chip communication

Plan to have up to four such interfaces per NOC tile This interface is the key to scalability and

allows creation of larger virtual NOC tiled systems

REXAPP

MAC APPL.

PHY PHYPHY

A NOCtile

RF Front End

External MemoryDDR2/Flash

REXAPP System Controller

MAC APPL.

PHY PHYPHY

A NOCtile

RF Front End

External MemoryDDR2/Flash

REXAPP System Controller

An example REXAPP System

REXAPP Compiler

Matlab ModelBit True

REXAPP Compiler

Kernels

NOC Template

System Level Timing

Constraints

Logic Synthesis

Physical Synthesis

TransactionLevelModel

Cycle Accurate

Model

Physical Design

PerformanceVerification

Matlab ModelBit True

Matlab ModelBit True

REXAPP CompilerREXAPP Compiler

KernelsKernels

NOC TemplateNOC Template

System Level Timing

Constraints

System Level Timing

Constraints

Logic Synthesis Logic Synthesis

Physical Synthesis Physical Synthesis

TransactionLevelModel

TransactionLevelModel

Cycle Accurate

Model

Cycle Accurate

Model

Physical DesignPhysical Design

PerformanceVerification

REXAPP Methodology Flow

REXAPP Compiler

Principal component to be developed in this project

Inputs to REXAPP Compiler

Input to the compiler will be the Matlab code To make the compilation task more

manageable, we plan to introduce some judicious restrictions on the modeling style in Matlab and some pragmas that will give hints to the REXAPP compiler to select kernels

Inputs to REXAPP Compiler

REXAPP compiler will be given the total system level timing constraints

REXAPP compiler will have access to a database of Kernels and NOC templates NOC template itself has been previously

developed at KTH and continues to evolve and is not part of this project

Outputs of REXAPP Compiler

REXAPP compiler will generate three outputs for the NOC based template RTL model meant for logic synthesis

followed by Physical synthesis. This track is meant to generate the actual

physical design in GDSII format. Transaction Level Model

used to ascertain the functional correctness of the generated model against the reference Matlab model

Outputs of REXAPP Compiler

Cycle Accurate Simulation Model To do detailed timing analysis to

check the performance and possible fine tune the architecture and possible mapping policies.

Proof of ConceptRemove cyclic prefix

FFT

De-subchannelizationPilot extraction

Channel estimation, Equalization and CFO

correction

To MAC

Symbol de-mapping

De-interleaving

FEC decoding

De-randomization

To MAC/ PHY

OFDMA Kernel-1

OFDMA Kernel-2

OFDMA Ranging

OFDMA Kernel-3

OFDMA Kernel-4

OFDMA Kernel-5

OFDMA Kernel-6

Block diagram of OFDMA Receiver Kernels

Proof of Concept

NOC tile configured as a generic OFDMA receiver

Proof of Concept

Correlator

Demultiplexer

Symbol extraction, de-mapping

De-interleaving

Viterbi decoder

CRC detector

To MAC/ PHY

CDMA Kernel-1

CDMA Kernel-2

CDMA Kernel-3

CDMA Kernel-4

CDMA Kernel-5

CDMA Receiver Kernels

Proof of Concept

NOC tile configured as a generic CDMA receiver

References

Proposal/Application for Technical Development and Research Grant for “SDR Development using NOC Based Rapid Prototyping Platform”