resume_abhijeet shinde_vit university_mtech vlsi
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ABHIJEET SHINDE
At Akhade,Post Humgaon,Taluka Jawali,District Satara,Maharashtra | (+91)80 5555 8066 | [email protected] |LinkedIn
OBJECTIVE Looking For Opportunities in Physical Design,STA, ASIC/FPGA Design ,Layout Design and Memory Design.
EDUCATION
VIT University,Vellore, TamilNadu. Percentage – 73.6% May „17 Masters of Technology in – VLSI Design. MIT,Kothrud, Pune,Maharashtra.
Bachelor of Engineering in Electronics and Telecommunication Engineering.
Percentage – 68.2% May „14
Government Polytechnic, Pune,Maharashtra.
Diploma in Electronics and Telecommunication Engineering.
Percentage – 89% May „11
New English School,Humgaon,Maharashtra.
Secondry School Certificate.(S.S.C)
Percentage – 93.38% May „08
LAB EXPERIENCE (June „15 – June „16)
• Developed PERL,TCL Script and Verilog codes with Testbench to create different RTL Design models for Testing and
Debugging Design issue with Timing and Power Calculations .
• Performed Simulation,Synthesis,Floor-planning,Partitioning,Power planning,Placement,CTS,Routing,Layouts with RC
Extraction for different RTL Design Models using Synopsys & Cadence Tools.
• Developed RTL and Symbol and Done Symbol Testing,DRC,LVS,RC Extraction for Pre & Postlayout
Simulation for different Analog and Digital circuits.
COURSEWORK
Analog IC design, Digital IC Design, Scripting Language and Verification, Advanced Computer Architecture,IC Technology, ASIC Design,Low power IC Design,FPGA based system Design,Mixed signal IC Design,System on chip,Testing and Testability, Digital Signal Processing,CAD for VLSI.
TECHNICAL SKILLS
Tools: Cadence Virtuoso (Layout,Extraction),Cadence RTL Compiler, Synopsys Design Compiler,Synopsys VCS,Synopsys
IC Compiler, Mentor’s Modelsim Altera 10.1d (Quartus II 13.1), Vivado Xilinx,AIMSPICE,PSPICE, Multisim,MATLAB,
MS-office,Linux. Languages: Basic of C,Verilog,PERL,TCL,Verilog HDL,Assembly Language(8051).
COURSE PROJECTS
Performance Modeling of Pipelined Linear Algbric Architecture on ASIC. [Modelsim,Synopsys,Verilog]
• Completed ASIC Design flow of algebric modules using verilog codes with Pipelined architecture.
• Done RTL description,Simulation (VCS compiler),Synthesis(DC compiler) with Area,Timing,Power calculations. • Performed Floor-Planning,Partitioning,Power Planning,Placement,CTS,Routing using IC compiler for backend process.
Transaction based AMBA AXI BUS Interconnect using Verilog.[Synopsys, Modelsim,Verilog]
• Developed complete set of Verilog codes for Master Interfacing of Transaction based AMBA AXI BUS interconnect.
• ASIC flow followed as RTL description,Simulation (VCS compiler),Synthesis with Clock gating & Multi VDD constraints.
• Done Comparison of Area,Timing and Power before & after adding the Constraints.
Full custom design of Low-Noise Neural Recording Amplifier. [FINFET(20nm),CMOS(180nm),Cadence(Virtuoso)]
• Custom designed RTL of Neural Recording Amplifier using FINFET and CMOS in Cadence(Virtuoso).
• Performed RTL Schmatic Simulation,Symbol Testing,DRC,LVS,RC extraction,Pre & Postlayout simulation with Cadence Virtuoso.
• Comparison between FINFET(20nm) and CMOS(180nm) is carried out for different parameters.
RTL and Physical Design of 16 bit CSA adder based on MUX-less by-passing architecture. [90nm,Virtuoso(Cadence)]
• Drew optimized 16 bit CSA adder architecture using Virtuoso(Cadence) with 90nm technology .
• Performed backend flow (RTL to GDSII),Synthesis,DRC, LVS clean in Cadence .
• Optimized design for MUX-less by-passing architecture implemented which results into energy efficient adder.
Implementation and Analysis of “MASH” modulator [AIM Spice,PSPICE]
• MASH Modulator designed in AIM-SPICE and SNR calculations are done in MATLAB.
• D-ff used to design first order FIR filter also as delay element.SNR estimated for different Over sampling ratio (OSR).
• In band noise and Over sampling ratio (OSRs) are observed.
PUBLICATION “A Reconfigurable Coprocessor units with Redundant Radix- 4 Arithmatic”
WORKSHOPS
• Attended two days workshop on “System Verilog and UVM” at VIT University.
• Attended six days workshop on “DEVICE TO GDSII FOR IC DESIGN” at VIT University.