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AASTHA GROVER
E-Mail: [email protected]
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PROFESSIONAL MISSION
To utilize my multi-disciplinary and multi-cultural aptitudes in promulgation of engineering
knowledge and management of technical personnel/resources in the global milieu.
ATTRIBUTE HIGHLIGHTS
Self-motivated, assertive, and future-oriented leaderfor committees, groups and
organizations, capable to handle all kind of academic administrations.
Teacher Assistant for tutorials of Digital Signal Processing, practical labs of Electronic
Devices and Circuits, Circuit Design and Simulation, Digital Electronics, Analog
Communication, Signals and Systems, Digital Signal Processing, Telecommunication
Networks and Digital Image Processing.
PRESENT ACTIVITIES:
Presently I am an M.Tech student (ECE) at Jaypee University of Engineering and Technologyand
being a GATE scholar I am working as a Teacher Assistantin the Department of Electronics and
Communication at Jaypee University of Engineering and Technology, Guna,(M.P.).I have
already completed my experimental part. Thesis has been submitted.
EDUCATIONAL QUALIFICATIONS:
Pursuing Full time regular PG Master of Technology (M.Tech) in Electronics Design and
Technology from Dept. of ECE, Jaypee University of Engineering and Technology,
Guna, M.P. with Honours ( CGPA= 9.7/10).
B.Tech in Electronics & Telecommunication Engineering from New Government
Engineering College with Honours (Percentage = 77.5%), Raipur (C.G.) in 2012.
Higher Secondary School in Science with 81.6% from Bharat Mata H.S.School, Raipur
(C.G.) in 2008
High School in Science with 83.5% from Bharat Mata H.S.School, Raipur (C.G.) in
2006
ACHIEVEMENTS:
Qualified GATE-2013 with 30 marks.
National Cadet Corps (NCC) A-Certificate Examination.
Excelled in NIIT Aptitude Test at National level.
Completed Vocational Training of four weeks at BRBRAITT, Jabalpur, M.P.
ACADEMIC PROJECTS:
M.TECH THESIS:
AREA OF M.TECH THESIS WORK:Very Large Scale Integrated Circuits, Simulation of
Hardware design on Xilinx 12.1.
TOPIC OF M.TECH THESIS: “HARDWARE DESIGN OF COMPLEX-VALUED PIPELINE
FFT USING VHDL”
BRIEF DESCRIPTION ABOUT MY THESIS WORK:
Fast Fourier Transform (FFT) is an essential component in many digital signal processing and
communications systems. FFT can be computed using decimation-in time (DIT) or decimation-in
frequency (DIF) approach. Both the DIT and DIF flow-graphs involve butterfly computation and
complex data-path. Besides, the flow-graph becomes increasingly disordered after subsequent
stages of butterfly computation. Therefore, mapping the FFT computation into a dedicated VLSI
system is quite challenging. Few schemes have been proposed in the literature for efficient
realization of FFT in pipelined VLSI systems. However, these pipeline designs involve huge
amount of memory and not hardware efficient. In this dissertation, we made study on the DIT
flow-graph and applied the horizontal folding to map the FFT algorithm into a pipeline structure
using L butterfly units, where L=log2N, and N is the FFT size. Multiplier outputs are truncated
for fixed-point implementation. The input-data are scaled suitably to reduce the truncation error.
The truncation error is estimated through simulation and found to be 0.0104% for N=8 and
0.0169% for N=16. We have considered a register-based storage unit design instead of RAM
based storage unit design as considered in the existing designs to buffer the intermediate outputs,
since the register-based storage unit involves nearly half the storage bits than those required by
RAM based storage unit and provides both the read and write operations. Therefore, the
proposed pipeline structure can offer a significant amount of area saving than the existing
structures.
MAJOR PROJECT:
AREA OF MAJOR PROJECT: EMBEDDED SYSTEM
TOPIC OF B.TECH MAJOR PROJECT: ‘Microprocessor Programming, Interfacing and
DTMF Based Typing to design an Automated Typing System/ Notice Board. Whatever typed on
cell phone displays live on LCD (Display)’
BRIEF DESCRIPTION:
I have done my B.Tech project work from January 2012 to June 2012 under the guidance of
Prof. A.K. Shrivastava, HOD, Electronics and Telecommunication Department, New
Government Engineering College, Raipur (C.G.). My project work was to design Microprocessor
based Automated Typing System using DTMF based typing technique Dual Tone Multi
Frequency or DTMF I a method for instructing telephone switching systems or related telephony
equipment. Using this technique, one can send/display the desired message or data on the display
screen from anywhere through his/her mobile phone. It is suitable for short as well as long
distance communications because it is a wireless communication, avoiding the use of heavy,
bulky cables. It is simple to operate, user friendly as well as DTMF tones can be recorded and
played back later.
MINOR PROJECT:
TOPIC OF B.TECH MINOR PROJECT: ‘ATM machine security system’
BRIEF DESCRIPTION: The main motive of the project is to secure the ATM machine using
the proximity sensor that sends the alert message to controlling block in case of any attempt of
theft.
SUBJECTS OF INTEREST:
PG Level (For M.Tech.): CMOS Circuit Design, Advanced Digital Signal Processing.
UG(B.Tech) Level: Digital Electronics, Electronic Devices and Circuits, Control
Systems, VLSI device and design Network Analysis and Synthesis, Signals and Systems,
VLSI, Digital Signal Processing.
SHORT TERM COURSES/ WORKSHOP ATTENDED:
National Workshop on “Advancements in Network Communication and Security” at
Jaypee University of Engineering and Technology, Guna from 29th to 31st December.
PERSONAL INFORMATION:
Father’s Name: Deependra Grover
Date of Birth: 28th October, 1990
Permanent Address: C/o Deependra Grover, H.No. 418, Street No.29, Sunder Nagar, Raipur
(C.G.)
Hobbies: Drawing, Photography, Exploring historical sites
REFERENCES:
1. Dr. B.K. Mohanty, HOD, Department of Electronics and Communication Engineering,
Jaypee University of Engineering and Technology, Guna. E-mail: [email protected]
Phone: 91-9425135311
2. Dr. Rajesh Kumar Vishwakarma, Assistant Professor(SG), Department of Electronics
and Communication Engineering, Jaypee University of Engineering and Technology,
Guna. E-mail:[email protected] Phone: 91-9302134462
DECLARATION:
I hereby declare that the above written particulars are true to the best of my knowledge and
belief.
DateAastha Grover
15/06/2016