research programmes for telecommunication …...elemental ta diffusion barriers, we were able to...

Research Programmes forTelecommunication

Electronics

TELECT

RONICS II

-

-

TE

LE

C

TRONICS

Research Programmes for

Telecommunication Electronics

Research Reports

ISBN 951-715-508-5 (print)

ISBN 951-715-509-3 (pdf)

Contents

Telectronics

Integration of Microcircuits with Multilayer Substrates.......................................................................... 5

Integrated Waveguide Bragg Gratings..................................................................................................... 9

Adiabatic Logic and its Integration with CMOS Technology ............................................................... 13

Blind Source Separation and Deconvolution in Telecommunications and Array Signal Processing ............. 19

Personal Access and User Interface for Multimodal Broadband Telecommunication .......................... 25

Integrated Circuits Solutions for Adaptive and Wideband Radio Communication Systems ................. 31

Techniques for the Third Generation of Wireless Systems ................................................................... 41

Fractal Processes in Telecommunications ............................................................................................. 45

Distributed Media Processing in Hybrid Networks ............................................................................... 47

Computational Methods for the Performance Analysis of Broadband Communication Networks ................ 51

Telectronics II

Future Internet - Traffic Handling and Performance Analysis .............................................................. 59

Blind Signal Separation in Communications Receivers and Antenna Array Systems........................... 67

Concurrent Design and Fabrication of Integrated Module Board.......................................................... 79

Advanced Radio Channel Identification and Equalization .................................................................... 87

Development of the Second Generation Delta-sigma Frequency Synthesis Techniques....................... 93

On-Chip Communication Architecture for HW/SW Co-design .......................................................... 101

TELECTRONICS Research Programme Final Report.

Integration of Microcircuits with Multilayer Substrates Using Advanced Thin-Film Processing

Jorma Kivilahti Professor

Lab. of Electronics Production Technology Helsinki University of Technology

P.O. Box 3000, FIN-02015 HUT, Finland [email protected]

ABSTRACT

The project had two major objectives. The first one was to design and fabricate an effective diffusion barrier layer between copper and silicon on the basis of the theoretical and experimental study of Cu|M|Si interactions. Having the expertise needed for manufacturing functioning Cu-metallised IC's it was possible to realise the second objective that was to interconnect bare Cu-chips with the IMB multilayer build-up technology developed earlier in the laboratory. Both objectives were attained succesfully in the project.

I. INTRODUCTION

Increasing capabilities of integrated circuits cannot be converted fully into component or system performance, because the interconnection and packaging technologies limit not only the technical performance but also contrib-ute too much to cost (Fig. 1). Thus, a great challenge is related to advances in thin film processing, underlying electronic materials and, in particular, to fabricating reliably very small interconnections. Likewise, the integration of microcircuits and passive components into

Lithography

BGA

"fine-pitch"

(FC)2

Flip Chip

1

Inte

rcon

nec

tio

nvo

lum

e[m

m3 ]

Conductor width or pad size [µm]

10-6

10-3

VLSIMSI

"ultra fine-pitch"

[10 µm]3

Paste-printing

IMB

10102103

THT

SMT

CSP

10-4

10-5

10-2

10-1

[50 µm]3

[100 µm]3

Flip Chip

FCHD Boards

Build-upcontacts

DIL

QFB

FR4

flexible or rigid

Technology transition

FC Pac

kag

ing

den

sity

Conductivepolymer pastes,films, TFB, etc.

"Green Electronics"

SLI

Cu-on-Cu contacts

Defect rate

No

volu

me

Fig. 1. Impact of miniaturisation on interconnection and packaging technology.

high density multilayer substrates should be realised cost-effectively.

These challenges can be met effectively by making use of IC's with Cu metallisation. But the utilisation of the Cu-metallised microcircuits provides essentially that the interactions between Si and Cu are understood thoroughly. Therefore, the objectives of the project were, firstly, to study theoretically and experimentally Cu/M/Si interactions and, secondly, based on the knowledge gained by the first objective to interconnect bare chips with the build-up technique. Cu and Si react strongly even at low temperatures and so a diffusion barrier layer is required between them. Tantalum and tantalum-based materials have been chosen as the diffusion barrier materials in the present study.

II. THEORETICAL CONSIDERATIONS

In the theoretical considerations the combined thermo-dynamic-kinetic analysis was employed. Phase diagrams can be used to have information about the phases that can exist in local equilibrium with each other at different temperatures. Furthermore, if the phase diagrams are coupled with the available kinetic data, it is possible to predict phase formation sequences in diffusion couples. However, this type of predictions must be executed with precautions for the thin film systems, since the use of phase diagrams for solve the phase formation sequence requires an assumption that the local equilibrium is attained at the interfaces, which is not always the case in the thin film systems. The assumption of local equilibrium demands that reactions at the interfaces are fast enough so that the atoms arriving in the reaction region are used immediately and the rate determining step is the diffusion. However, with very thin layers this requirement may not be fulfilled. The reasons for this originate mainly from the special conditions prevailing during thin film reactions: (a) relatively low reaction temperatures, (b) small dimensions, (c) high density of short-circuit diffusion paths, (d) relatively large stresses incorporated in thin

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films, (e) relatively high concentration of impurities, (f) metastable structures, (g) large gradients, etc. However, despite the difficulties mentioned, it is expected that by employing this approach better understanding of the equilibria and reactions in the system is achieved.

In this study several important ternary phase diagrams were assessed. Among them are especially Si-Ta-Cu, Si-Ta-C, Ta-C-Cu, Si-Ta-N, Ta-N-Cu and Ta-C-O systems. The activity diagrams as well as several binary diagrams were evaluated. The information extracted from these diagrams together with the experimental results were used to discover the underlying mechanism(s) for the failure.

III. EXPERIMENTS

Tantalum and tantalum-based materials have been chosen as the diffusion barrier materials in this study. Ta, TaC, Ta2N and TaN diffusion barriers with thicknesses of 10, 50 and 100 nm were used in the investigations. The films were sputter-deposited either with inert carrier gas (Ta and TaC) or with reactive sputtering (Ta2N and TaN). The copper overlayer thickness was either 100 or 400 nm. The stacked sheet films on (100) Si substrates have been annealed at different temperatures between 400 and 800 °C for 30 min under the vacuum of 10-4 Pa. The sheet resistance measurements at room temperature using the four-point probe have been used to detect interfacial reactions after each annealing step. The reaction products in the different metallisation schemes have been characterised by using the grazing incidence x-ray diffractometry (XRD), the Rutherford backscattering spectroscopy (RBS), the secondary ion mass-spectroscopy (SIMS), and the transmission electron microscopy (TEM). Surfaces of the samples were also examined with an optical microscope and scanning electron microscope (SEM). The atomic force microscopy (AFM) was used to monitor the surface of the sputtered films.

IV. RESULTS AND IMPACTS

The objectives of the project were attained very well. The project gave new insight and significant fundamental results on CuM/Si interactions. Furthermore, the project produced valuable practical results, which have been utilised successfully in developing the Integrated Module Board (IMB) technology in the ETX projects supported by the National Technology Agency and the Finnish Electronics Industry. The co-operation between the partners was very useful. By combining the thermodynamic-kinetic approach together with the detailed microstructural analyses (HUT/EPT) and by employing the novel thin film fabrication facilities (VTT), much better understanding of the diffusion barrier problem was achieved. In addition to greater expertise in

fabricating high density build-up structures several scientific papers have been published in highly esteemed research journals during the project. The theoretical approaches employed in the project proved to be very useful, and they provided excellent basis for further investigations in the field.

The first objective of the present work was to obtain a deeper understanding of the failure mechanisms, microstructures and stabilities of the Ta-based barrier layers. The combined thermodynamic-kinetic approach, which has not been previously used in the investigation of thin film diffusion barriers, was utilized for analysing and explaining the experimentally observed reaction sequences. It has been shown that this approach can provide unambiguous knowledge of the reactions taking place during the annealing in the metallization structures.

The results demonstrate that Ta-based barriers offer a very feasible solution to the diffusion barrier problem. The failure mechanisms of the different barrier layers (e.g.Ta, TaC and Ta2N) have many similarities. Especially, TaC and Ta2N behave almost identically. With the help of thermodynamic evaluation of the corresponding ternary phase diagrams, we pointed out that the reason behind this similarity was the almost identical phase relationships found in both metallization systems. In the case of elemental Ta diffusion barriers, we were able to demonstrate that the failure mechanism was thickness- dependent. Using this knowledge, it was possible to solve many contradictions with respect to the first phase formation during the annealing in the Si/Ta/Cu metallization system, as reported in the literature. Furthermore, the crucial effect of oxygen on the reactions in all the metallization schemes with the different Ta-based diffusion barriers was demonstrated and the thermodynamic basis for understanding the origins of this behaviour was given (Figs. 2 and 3).

The ternary Ta-Si-Cu, Ta-Si-N, Ta-Si-C, Ta-N-Cu and Ta-C-Cu phase diagrams have been calculated from the assessed binary thermodynamic data. The binary Ta-O and ternary Ta-C-O phase diagrams (Fig. 3) have also been calculated in order to model thermodynamically the influences of oxygen on the reactions in different metallisation schemes.

The Integrated Module Board (IMB) technique developed in the laboratory of Electronics Production Technology is used to integrate the Cu-metallised IC's being fabricated by the VTT Microelectronics. In this PWB-based technology both bare microcircuits and passive components are integrated successfully in conjunction with the fabrication of high density organic HDI substrates in large panels. This solderless, non-vacuum and fully additive technology is based on a

6


photodefinable epoxies and fully additive electroless plating process.

TaC50 nm

a-Ta[O,C]x

Cu

Fig. 2. Bright field TEM micrograph from the Si/TaC(70nm)/Cu(400nm) sample annealed at 600 °Cfor 30 min.

1/2O2

Ta C0.2 0.4 0.6 0.8 1.00

X(C)

X(O

)

TaC

TaC +Ta2O5+graphiteTaC+

Ta2O5 +Ta[O]ss

0.2

0.4

0.6

0.8Ta2O5

Ta2O5+graphite + 1/2O2

C.L.

initial composition

Fig. 3. Isothermal section from the evaluated metastable ternary Ta-C-O phase diagram at 600 °C under the external oxygen pressure of about 0.2×10-4 Pa. The tie-lines in the TaC-Ta2O5 two-phase region are shown in the diagram. The contact-line (C.L.) between the TaC film and oxygen indicating the initial unstable equilibrium as well as the approximate composition of the TaC[O]gb are also shown.

Metals such as copper or nickel are chemically deposited onto photodefined wiring tracks and I/O pads of embedded active components. The IMB technology

enables short conductor line lengths, small line pitches (< 50µm) and extremely high component density. In this manner functional high density modules with good electrical performance and better reliability than with solder-based surface mount technology (SMT) can be achieved. However, in order to fully utilise the capabilities of the IMB technology, one needs Cu- metallised IC's to get rid of the complex Under Bump Metallurgy (UBM) structures as needed currently with Al metallisation. The Cu-metallised IC's enable the fabrication of Cu/Cu contacts throughout the whole functional module (Figs. 4 and 5). This is very beneficial both from the electrical and reliability point of view, and it will simplify the fabrication process considerably. Thus, the work performed in this project has supported the development of the IMB technology, which is presently being implemented into production by the Imbera Electronics established in 2002 jointly by Aspocomp Group and Elcoteq Networks. Further development of the IMB technology continues also in the "Interfacial Compati-bility Between Dissimilar Materials in Ultra-High Density Electronics" project financially supported by Academy of Finland.

Fig. 4. Integrated Module Board (IMB) fabricated with the fully additive build-up process (www.ept.hut.fi)

50 µm

Cu

Ta

50 µm

Cu/Cu -interconnection

SiTa|Cu

(a) (b)

Fig. 5 (a) Plain view of the IC with Cu contact pads and Ta diffusion barrier and (b) cross-sectional view of the same structure showing the Cu/Cu interconnections.

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The results of the project are currently being used also in another project within the Telectronics II program, which continues and enables the development of concurrent design of very-high density integrated electronics like IMB modules and so expands the work carried out in this project. Without any doubt the research in this field will continue in the future.

V. PUBLICATIONS

A. PEER-REVIEWED PAPERS, CONFERENCE PAPERS

AND REPORTS

[1] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K., "Amorphous Layer Formation at the TaC/Cu Interface in the Si/TaC/Cu Metallization System", Applied Physics Letters, 80, pp. 938-940, (2002).

[2] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K., "TaC as a Diffusion Barrier Between Si and Cu", Journal of Applied Physics, 91,pp. 5391-5399, (2002).

[3] Laurila T., Zeng K., Molarius J., Riekkinen T., Suni I., and Kivilahti J.K., "Tantalum Carbide and Nitride Diffusion Barriers for Cu Metallisation", Microelectronics Engineering, 60, pp. 71-80, (2002)

[4] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K.,"Effect of Oxygen on the Reactions in the Si/Ta/Cu Metallization System", Journal of Materials Research, 16,pp.2939-2946, (2001).

[5] Laurila T., Zeng K., Molarius J., Riekkinen T., Suni I., and Kivilahti J.K., "Effect of Oxygen on the Reactions in Si/Ta/Cu and Si/TaC/Cu Systems", Microelectronics Engineering, (in print).

[6] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K., "Failure Mechanism of Ta Diffusion Barrier Between Cu and Si", Journal of Applied Physics, 88,pp.3377-3384, (2000).

[7] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K., "Chemical Stability of Tantalum Diffusion Barrier Between Cu and Si", Thin Solid Films, 373, pp.64-67, (2000).

[8] Molarius J., Riekkinen T., Suni I., Laurila T., Zeng K.and Kivilahti J.K., "Reactively Sputtered Ta2N and TaN Diffusion Barriers for Copper Metallization", Advanced Metallization Conference (AMC) 2000, San Diego California, October 3-5, (2000).

[9] Laurila T., Zeng K., Kivilahti J.K., Molarius J., and Suni I., "Reliability of Tantalum Based Diffusion Barriers

between Copper and Silicon", Proceedings of the MRS Spring 2000 Meeting, San Francisco, April 24-28, 2000, v 612.

[10] Molarius J.M., Suni I., Laurila T., Zeng K., and Kivilahti J.K., "R.F.-Sputtered Tantalum-Based Diffusion Barriers Between Copper and Silicon", Superficies y Vacio, 9, 206, (1999).

[11] Laurila T., Molarius J., Kodentsov A.A., van Loo F.J.J. and Kivilahti J.K., "Reactions in the Si/TaC/Cu system", (submitted 2002).

B. ACADEMIC DEGREES

[1] Laurila T., "Tantalum based diffusion barriers for copper metallization", Doctoral Dissertation (2001).

C. SCIENTIFIC REPORTS

[1] Laurila T., Zeng K., Molarius J., Suni I., and Kivilahti J.K., "Stability of TaC Diffusion Barrier Between Si and Cu", HUT Internal Report, HUT-EPT-7, ISBN 951-22-5777-7, (2001).

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Integrated waveguide Bragg gratings

Matti Leppihalme, Timo Aalto, Päivi Heimala, and Sanna Yliniemi

VTT Centre for MicroelectronicsP.O. Box 1208, FIN-02044 VTT

[email protected]

Jari Turunen, Markku Kuittinen, Janne Simonen, Jani Tervo, and Tuomas Vallius

University of Joensuu, Department of PhysicsP.O. Box 111, FIN-80101 Joensuu

[email protected]

ABSTRACT

In this project integration of Bragg grating structuresto silicon-on-insulator (SOI) waveguides was studied. Anefficient quasi-rigorous computational method wasdeveloped for analysis of waveguide gratings and appliedto SOI structures. Phase masks for Bragg gratingexposure experiments on the proximity mask aligner weredesigned and fabricated. A new method was found toeliminate the harmful zeroth diffraction order of a phase-mask grating. Investigations on photonic bandgapstructures by rigorous diffraction theory were initiatedduring the project.

State of the art fabrication methods for bothnanostructures and waveguides were developed. Themethods were demonstrated by fabricating andcharacterizing several test structures and components.The integration of SOI waveguides with gratings wasaccomplished during the project. Optical measurements,however, showed that the process still needs some finetuning.

I. INTRODUCTION

Broadband Information Technology is a majorbusiness area and optics is the enabling technology ofchoice needed for its realization. All-optical networkswhere the signal is transmitted, routed and switchedoptically from end to end have been intensively studiedworldwide leading to a tremendous development ofoptical telecommunication. At present the datatransmittance rates are on the level of 40 Gb/s for a singlelaser-fiber combination and wavelength divisionmultiplexing (WDM) systems can have hundreds ofchannels. These multi-wavelength optical networks offer

an extremely large bandwidth and are transparent to signalformat and type and offer many advantages for futuretelecommunication and computer networks.

The rapid development in WDM opticalcommunications has generated strong needs for novelplanar multiwavelength devices, which can treat opticalsignals. One of the key components is a grating, whichcan be tailored directly in the waveguide structures. Thesestructures will enable for instance such functions inoptical telecommunications, as add-drop filters needed toaccomplish a WDM circuit, notch band filters, dispersioncompensation applying chirped Bragg gratings andexternal cavities for DFB-lasers etc. The grating structurescould also be used in microsystems and in various sensingapplications. The use of a silicon substrate as an “opticalbench” is furthermore a very appealing approach toreduce the costs of the multifunctional optical systems byintegration.

In this project, our major goal was to developand demonstrate Bragg grating structures integrated withSOI waveguides and to study their properties andapplicability in optical telecommunication systems. Asthe integration of nanoscale gratings with micron-scalewaveguides proved to be very challenging weconcentrated on solving the technical problems and putless effort on the applications. Due to the process synergysome studies on photonic crystal structures were alsomade during the project.

This project was a joint research between VTTCentre for Microelectronics and University of Joensuu.University of Joensuu has been responsible for theoreticalmodeling and direct e-beam writing while VTT has beenresponsible for grating and waveguide processing andfabrication and optical characterization of accomplishedstructures.

9


II. RIGOROUS DIFFRACTION THEORY IN

GRATING MODELLING

a) Bragg grating structures in SOI waveguidesThe analysis method of waveguide gratings based on

rigorous diffraction theory, developed earlier at theUniversity of Joensuu, was applied to modeling of Bragg gratings in SOI waveguides [1]. The structure parameterswere provided by VTT Centre for Microelectronics. In particular, the effect of the weak effective indexmodulation on the grating length required was analyzed toachieve strong distributed feedback. The results werecompared to the stratified medium theory, which wasshown to predict the spectral position of the resonancepeak with inadequate precision.

As a continuation to the work reported in [1] anefficient quasi-rigorous computational method wasdeveloped for the analysis of waveguide gratings andapplied to SOI structures [2,3]. This method is based on rigorous electromagnetic diffraction theory of gratingsand on certain assumptions appropriate for waveguidestructures.

b) Phase masks for grating structuresRigorous diffraction theory was applied to design

phase masks for Bragg grating exposure experiments onthe proximity mask aligner at VTT Centre forMicroelectronics. The method was verifiedexperimentally by fabricating a test phase mask byelectron beam lithography.

A new method was found to eliminate the harmfulzeroth diffraction order of a phase-mask grating: thegrating was coated with a thin film of dielectric materialhaving a refractive index higher than that of the substratematerial. This method was demonstrated experimentally[4] using electron beam lithography, reactive ion etching,and vacuum deposition.

c) Photonic crystal structuresInvestigations on photonic bandgap structures by

rigorous diffraction theory were initiated during theproject. The intention was to fabricate such structures inSOI waveguides using the same technology as in thefabrication of waveguide gratings. During the project anovel electromagnetic approach to photonic crystals wasdeveloped. The basic idea of the method is thereformulation of the so called C method with adaptivespatial resolution enabling the use of non-identicaltrapezoidal profiles [5]. The developed method allows theefficient numerical analysis of photonic crystal structuresconsisting of polygonal rods.

III. FABRICATION PROCESS

The goal of the project was to fabricate integratedoptical components based on Bragg gratings with periodson the order of 200 nm. In a waveguide grating thecorrugation was intentionally extended beyond the ridgein order to enhance the refractive index modulation in thewaveguide region. A schematic of the Bragg gratingintegrated with a silicon waveguide and a possibleapplication is shown in Figure 1.

Figure 1 – A schematic of a targeted waveguide structurewith a grating on top (left) and its integration to afunctioning waveguide component (right). The illustratedstructure can perform as an add-drop multiplexer byreflecting a selected wavelength and passing through therest of the wavelengths.

a) Bragg grating structuresAccording to modeling the depth of the gratings over

the waveguide should be in the order of one micron toachieve sufficiently strong reflection from the grating.The fabrication procedure consisted of three critical stepsto be optimized: e-beam resist patterning, oxide masketching, and silicon etching [6]. The direct electron beamresist patterning was performed at the University ofJoensuu and the rest of the processing was done at VTTCentre for Microelectronics.

Bragg grating test structures with lattice periods of225 and 450 nm with intended air-to-dielectric filling ratioof 50% were fabricated on ordinary n-type siliconsubstrates. A thin oxide hard mask was used in siliconetching in inductively coupled plasma (ICP) to reach therequired etch depth of over 1 µm. In order to inhibit thestrong underetching in the beginning of the etching andalso the sideward etching during the process an etchingprocedure with a linear passivation was used.

In Fig. 2 scanning electron microscopy (SEM) picturesof the fabricated nanogratings are presented. Due to anartefact of the e-beam writing the filling ratio of thesmaller grating could not be precisely controlled. Thisartefact can be eliminated by optimizing the exposureparameters. The variation of the etch depth followed fromthe aspect ratio dependent etching (ARDE) effect duringthe ICP etching. The aspect ratio for the 225 nm periodgrating varied between 6 and 10 and for the 450 nm

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Figure 2 – SEM images of fabricated grating test structureswith a period of a) 225 nm period and b) 450 nm. Theetch depths are 1 µm and 1.2 µm, respectively.

period grating it was 5.3. The dip in the top of the gratingstructure followed from slight underetching in thebeginning of the silicon etching.

b) SOI waveguides and their integration with gratingsThe ridge waveguide was processed by depositing first

a plasma enhanced chemical vapor deposited (PECVD)oxide layer on the wafer. The waveguide structure waspatterned by standard UV-lithography and the pattern wastransferred into the PECVD oxide hard mask by dryetching. Finally, the waveguide structure was etched intosilicon using ICP. Etching process started with a similarcontinuously passivating etch process as was used for thegrating formation and the process was continued withpulsed etching process [7]. After etching, the waveguidestructure was covered with an oxide buffer layer. Wemeasured propagation losses less than 0.5 dB/cm at 1.55µm wavelength.

After the grating and waveguide processes were testedseparately, they were combined to form a waveguidegrating structure. First, the gratings were processed andthen the waveguide process was performed as describedabove but no oxide buffer layer was grown on top. ThePECVD oxide layer used to mask the waveguides coveredalso the small grating grooves and the nanogratings on theridge remained intact during the ICP etching of thewaveguide. The gratings outside the ridge were exposedfor one more oxide and silicon etching steps whileforming the waveguides.

a) a)

b)b)

Figure 3 – SEM images of waveguide grating teststructures with period 675 nm. The grating lines wereturned 90 degrees with respect to the real component. Theair-filling ratios were a) 60 %, and b) 70 %.

In Fig. 3 SEM micrographs of sideview profiles incorrugated waveguide grating test structures are shown.The grating was intentionally turned 90 degrees withrespect to the real optically functioning position in order to reveal processing details in SEM-analysis. The periodand the depth of the grating were 675 nm and 1.1 µm,respectively. The dimensions of the silicon ridge were 4.5µm and 7.5 µm, respectively. In the waveguide gratingtest structure shown in Fig. 3 a) the air filling ratio wasapproximately 60%. The grating on top of the ridgesucceeded well while the grating aside the ridge showedsome unintentional unidealities. High, narrow peaks ontop of the grating corners resulted from unperfect dryoxide etching when the waveguide etching mask wasformed. Plasma etching removed the oxide efficientlyfrom the grooves but in the walls of the groove part of theoxide was left and acted as a mask during the subsequentICP etching of the silicon ridge structure.

For slightly higher air-to-dielectric filling ratios orslightly smaller periods the situation was even worse. Inthese cases the oxide in the bottom of the groove wasthicker and was not totally removed in the oxide etching.The remaining oxide layer in the bottom behaved as aninverse mask in the silicon etching. The aspect ratio intrenches aside the ridge in Fig. 3 b) was on average 12.

We completed the integration of SOI waveguides andgratings during the project, but optical measurementsshowed that the process still needs fine tuning. There aretwo potential modifications to the process that could leadto functioning waveguide gratings, i.e. to replace theoxide dry etching step with wet etching (very straightforward to implement), or to limit the grating only on top

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of the waveguide ridge (processing sequence must bemodified).

c) Photonic crystal test structuresThe processes, which were developed for Bragg

gratings, are also applicable to other photonicnanostructures, such as photonic crystals. Photonic crystaltest structures were fabricated on silicon wafers with onlyslightly modifying the process described above. Theresults were very promising and optically functionalphotonic crystal structures will be realized by applying thesame processes to SOI wafers


Rigorous diffraction theory was applied to modelBragg gratings in silicon-on-insulator (SOI) waveguidesand developed for efficient analysis of waveguidegratings. In particular, the effect of the weak effectiveindex modulation on the grating length required wasanalyzed to achieve strong distributed feedback. Theresults were compared to the stratified medium theory,which was shown to predict the spectral position of theresonance peak with inadequate precision.

An efficient quasi-rigorous computational method wasdeveloped for analysis of waveguide gratings and appliedto SOI structures. The developed method allows efficientrigorous analysis of corrugated waveguide structureswithout any limitations for the corrugation depth.Furthermore, the method also facilitates the analysis ofcoupling of light from the fundamental mode into higherwaveguide modes. So far, this coupling has not beenpossible to analyze in waveguide gratings with widelyused thin-film stack methods.

Rigorous diffraction theory was applied to designphase masks for Bragg grating exposure experiments onthe proximity mask aligner. It was found that if a phasemask is coated with a thin film of dielectric materialhaving a refractive index higher than that of the substratematerial the harmful zeroth diffraction order of a phase-mask grating can be eliminated. The method was verifiedexperimentally by fabricating a test phase mask byelectron beam lithography.

Investigations on photonic bandgap structures byrigorous diffraction theory were initiated during theproject. We believe that the computational breakthroughsalready obtained will open new avenues in the analysis ofphotonics bandgap structures in waveguides and permitthe analysis of periodic structured with defects, a problemthat has appeared almost impossible to handle rigorouslyin the past.

State of the art fabrication methods for bothnanostructures and waveguides were developed. Themethods were demonstrated by fabricating andcharacterizing several test structures and components. The

depth and aspect ratio of the nanostructures were muchbetter than what is generally reported in literature. Themeasured propagation losses of the realized SOIwaveguides were one of the lowest reported in the world.

The integration of SOI waveguides with gratings wasaccomplished during the project. Optical measurements,however, showed that the process still needs fine tuning toeliminate the problems caused by the unintended oxidemasking during the waveguide etch.

In addition to the knowledge about the theory andfabrication of SOI waveguides, silicon Bragg gratings andphotonic crystals, many fabrication processes andprocedures were developed, as well as general knowledge,relating to the use of silicon as a core material inintegrated optics. We believe that these will be veryvaluable during the next few years, both scientifically andcommercially.

REFERENCES

[1] Vahimaa P. and Turunen J., 1998, "Electromagneticanalysis of waveguide Bragg reflectors", DiffractiveOptics and Micro-Optics, OSA Technical Digest,Vol. 10, pp. 69–71.

[2] Tervo J., Kuittinen M., Vahimaa P., Turunen J.,Aalto T., Heimala P., and Leppihalme M., 2001,"Efficient Bragg waveguide-grating analysis byquasi-rigorous approach based on Redheffer's starproduct", Optics Communications, vol. 198, pp.265-272.

[3] Tervo J., Kuittinen M., Vahimaa P., Turunen J.,Aalto T., Heimala P., and Leppihalme M., 2001,"Electromagnetic modeling of longitudinallyperiodic diffractive waveguide elements byRedheffer's star product approach", DiffractiveOptics, EOS Topical Meeting Digest Series, Vol. 30,pp. 138-139.

[4] Laakkonen P., Kuittinen M., and Turunen J., 2001,"Coated phase masks for proximity printing of Bragggratings", Optics Communications, vol. 192, pp.153-159.

[5] Vallius T. and Kuittinen M., "Novel electromagneticapproach to photonic crystals by using the Cmethod," 2002, submitted to Journal of OpticalSociety of America A.

[6] Yliniemi S., Simonen J., Aalto T., and Heimala P.,2002, "Fabrication of silicon nanostructures forphotonic crystal applications", submitted to Journalof Materials Science: Materials in electronics.

[7] Aalto T., Yliniemi S., Heimala P., Pekko P.,Simonen J., and Kuittinen M., 2002, "IntegratedBragg gratings in silicon-on-insulator waveguides",to be published in Proceedings of SPIE, PhotonicsWest 2002, Integrated optics devices IV, 19-25January 2002 (International Society for OpticalEngineering SPIE, San Jose, USA).

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Adiabatic logic and its integration with CMOS technology

Markku Åberg, Veikko Porra, Pekka KuivalainenJouko Marjonen, Jacek Flak, Arto Rantala

VTT Centre for MicroelectronicsP.O.Box 1208, 02044 VTT

<[email protected]>

ABSTRACT

The theme of this study is low power logic design byapplying adiabatic logic. Adiabatic logic is based onramp clocks to reduce thermal dissipation and on chargerecycling from capacitive loads. Adiabatic static and pass-transistor logic with applications (multiplicationcircuit, bus driver) have been studied. Clock generatorshave been optimized. The applicability of adiabaticprinciple in driving floating gate neural circuits has beenexamined.

I. Introduction Power consumption of digital circuits has become acritical issue in high speed and portable applications.Several means have been proposed to reduce powerconsumption. On software level for instance:-Energy efficient algorithms-Minimalisation of logic

active time of circuits/blocks is minimisedunnecessary bit processing removed

And on circuit (hardware) level: -Development of (CMOS) technology

lower capacitance and supply voltage;P = kNfCV2

V supply voltage, C gate capacitance, ffrequency, N number of gates, k activitycoefficient

-Shrinking of energy/computational operationadibatic logic/circuit

-New operation principles for circuitse.g. neural structure instead of digital structure

”Adiabatic circuit” is a fuzzy concept that covers (someof) several methods to reduce power consumption. Basictypes are [ 1]: Energy recovery circuits; that recover a substantialportion of the CV2 energy invested in logic signals.Asymptotically isentropic circuits; that in someappropriate limit (low speed/rise & fall time, low

temperature) generate asymptotically zero entropy per operation.Time-proportionally reversible circuits; entropygeneration per operation approximately inverselyproportional to the length of time over which operationsare performed.Ballistic circuits (today hypotethical); entropy coefficientso low (e.g. superconducting devices) that entropygeneration per operation is practically zero.Practical circuits usually combine a couple of types.

The basic operation principles of adiabatic logicconsidered here are: Voltage or current ramps are used to prevent resistivedissipation in parasitic resistance (asymptoticallyisentropic). The ramp rise and fall times tr, tf >> τ = RCtime constant of the circuit or block.Charge stored in the gate capacitors of the circuit iscollected back to the power supply (energy recovery).This needs an oscillating power supply that is in properphase to data load/discharge. The power supply can be realized either by LC-type resonance circuits, whereC is gate capacitance of logic blocks’ transistors andL an inductor at the power supply, or by many phasecircuits, where the carge is circulating from phase tophase.

II. Adiabatic STATIC LOGIC

We have studied both a dynamic-operation-basedadiabatic dynamic logic (ADL) [2] and a static-operation-based static logic (ASL). This report with concentrate on the former.

Adiabatic Static Logic (ASL)In ASL the adiabatic operation have been achieved byavoiding a DC current path from SPS to ground. Thecircuit is basically a full-wave rectifying circuit. Becausethe output of the SPS is above the zero voltage throughthe period it is possible to achieve a full-waverectification by means of two diodes only. One of thediodes is forward biased toward the source and it provides

13


the logical ‘1’ state. The other diode is reverse biased andprovides the logical ‘0’ state. The purpose of the CMOScircuitry connected between these two states is to allowone of the states to appear on the output. Using thisprinciple the functionality of several logic gates (NOT,NAND, NOR, AND, OR, SR flip-flop and D flip-flop)was verified in measurements. In an inverter chainmeasurement a 77% power saving was achievedcompared to CMOS implementation.

8x8-Multiplier based on the Adiabatic ChargeRecyclingIn this chapter an 8x8 binary multiplier based on theadiabatic static logic (ASL) is presented. The purpose of the fabricated chip was to research the useability of theASL gates on a larger system.Because the ASL gates are very similar to CMOS gates itwas possible to fabricated a single chip which containedboth the CMOS multiplier and the ASL multiplier. Usinga prober wiring it was possible to use the chip either inCMOS or in adiabatic mode.

MeasurementsThe functionality of the circuit was confirmed. In thepower consumption test a continuous multiplication wasperformed between items of a random vector [3]. Thevector length was 31 items. The resonator frequency waskept constant whereas the logic’s sampling frequency wasvarying between 4kHz and 40MHz. There was nosynchronization between the input data and resonatorsignal in the adiabatic power measurement.A layout error in the output buffer made exact powermeasurements impossible in the first prototype. Acorrected version is still in process at the time of writingthis report.

59 µH

268 pF

(parasitic)

Figure 2 The oscillator used in measurements

Figure 3 . A photo of the f abricated test chip.

Figure 1 . Adiabatic inverter (a), NAND (b).

III. Adiabatic Bus-Driver

This chapter describes the researches exploring theproperties of adiabatic logic on a system-level includingdesign, simulations and prototype tests. The bus-driverwas chosen as a system due to its major power-consumption of the application such as microprocessor,display controller, etc.

The driver was designed with the following goalspecifications:

- number of lines: 8- signal frequency: 10MHz- load capacitance: 10pF per line- voltage swing: 3.3V

The heart of the system is dual-rail line-driver based onthe proposal of Athas et al. in [5]. It has 2 very appealingfeatures: simplicity of the structure and ability tocooperate with standard CMOS receivers.

The circuits were redesigned for the 0.6µm technologychosen for fabrication, and during the HSpice simulationsthe sizes of the components were obtained as depicted in Figure 1.

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Figure 4. Components’ sizes in the power-clock supply(upper) and the line driver (lower). [2]

For logic 1 (high level) at the input X the driverrepeats power-clock signal φ (from supply in Fig.1) atthe corresponding output Y. Resistance of the switchestogether with inductance, tank and load capacitance forman RLC resonant circuit. It generates quasi-sinusoidalslopes utilized for charging and discharging of the loadcapacitance in adiabatic mode. Switches of the power-clock supply need two control signals VMa and VMb.

Simulation proved proper system operation andpower-saving of 66%. Also several requirements for thetiming of the clock signals appeared. To meet them thecontrol logic circuit (Fig.3) was designed. In addition tothat logic, the D flip-flops were placed at the input of system, to correct the phases of input signals andprovide the inverted signals for line-drivers. They are also clocked from the designed control logic.

Figure 5. Adiabatic Bus-Driver simulation waveforms.From top: VMa, VMb, φ, X for bit sequence [0,1,…0,1],Y, power-dissipation.

Figure 6. Scheme of the clocks generator.

X X

Y Y

X X

X X

Figure 7. Chip microphotograph.

Measurement resultsWaveforms observed during the measurements showed

that the pulse shape for the 5MHz operating frequency isthe same as simulated. At 7.5MHz it is still close to ideal,but at 10MHz a rather small part of the charge is beingrecovered. Also, the amplitude is lower than predicted.The explanation lies in imperfection of components of theresonant circuit (poor Q-factor of the available tunableinductors and large capacitor) as well as from theimplementation problems (inner lines, package and testboard parasitics). Since the parasitic parameter values arenot included in the circuit models, and they are verydifficult to predict, the imperfections were included in thecircuit afterwards. The resulting simulated waveformscome very close to the observed ones (Fig.5).

Measured Simulated

5MHz

7.5MHz

10MHz

Figure 8. Output waveforms.

Power consumption of entire system (coming frommeasured current flow of the voltage sources) was5.99mW, compared to 9.04mW calculated for standardCMOS approach. That means power saving slightly over33%, and could be further improved when applied inparticular device (replacing the tunable inductor with thehigh Q-value one after tuning in tests, lines and boardoptimization, etc.).

15


ConclusionsPresented system – bus-driver gains significant power-

saving over the standard CMOS approach, especiallywhen applied for driving large load capacitance atrelatively low frequencies. The simulations of the systemshowed that over 66% of the energy dissipated byconventional circuits may be saved. Measurements ofthe prototype chip proved the efficiency of 33%.

It seems to be reasonable to integrate some processing(adiabatic) logic together with the driver, because thatwould gain better usage of chip area and further reductionof the power consumption (one power-clock may supplythe logic and driver).

IV. NEURON MOS CIRCUITSIntroduction: A neuron MOS transistor has a floatinggate (FG) and a multiple number of the input gatescapacitively coupled to the floating gate as shown in Fig.1 (a) [6][7]. The accumulating weight of the inputcouplings controls the channel current in the neuron MOStransistor. The floating gate potential is determined as alinear sum of all the input signals weighted by thecapacitive coupling coefficients Ci/Ctotal. The voltagesignals are directly summed in the floating gate withoutany DC-power dissipation. In reality there is always aninitial charge in the floating gate due to the processing ofthe chip. This extra charge is possible to remove by UVerasing. In Figure 1 (c) a schematic cross-section of aneuron MOS transistor implemented with a doublepolysilicon CMOS process is illustrated. The upperpolysilicon layer forms the floating gate and thebottommost polysilicon layer composes capacitivelycoupled input gates. It should be noted that in addition tothe designed capacitances (the coupling capacitances ofthe input gates) some unwanted parasitic capacitancesappear. The dominant parasitic capacitance (Cfc in Figure1 (c)) is between the floating-gate and the substrate. If there are any additional structures, e.g metal layer abovethe floating-gate, also other parasitic capacitances areformed. In this study these parasitic capacitances wereused to provide calibration i.e. make more accurateneuron MOS structures.

Neuron MOS D/A: Neuron MOS transistors acts like anartificial neuron, i.e., the weighted sum of the inputvoltages controls the current of the transistor. By adding aspecific weights to the coupling capacitors more complexanalog computation functions are achieved. A simpledigital-to-analog conversion can be obtained if theweights are designed as binary weighted (i =1,2,..., n),and the neuron NMOS is connected as a source followeras shown in Figure 1 (b). An enhanced version of the D/Aconverter was designed so that the voltages driving the

lowest bits are also weighted by using a voltage division.The neuron D/A converters were processed with a 0.8 mmCMOS technology provided by VTT Electronics.Measurement results show that the presented ideasprovide an efficient way to implement DAC circuits evenat very high frequencies with low power and minimalsilicon area [8].

Neuron A/D converters and calibration : In order todemonstrate how the neuron MOSFETs reduce the totalnumber of transistors in a circuit, and especially how theproposed new calibration structures improve the circuitperformance, we have designed and fabricated simpleA/D converters utilizing the advantages offered by theproposed neuron transistor structures. A 3-bit A/Dconverte rwas implemented by using only 18 transistors(an ordinary CMOS implementation would require 174transistors). Also a special calibration topology wasintroduced, which makes it possible to implement moreaccurate A/D-converters (up to 6 bits) and an artificialneurons circuit.

Figure 9. a) A schematic diagram of a neuron (a) NMOS(b) a simple neuron MOS D/A-converter (c) a schematiccross-reference of a neuron MOS implemented withCMOS

V. Optimization of adiabatic clock generators

Clocking of the adiabatic logic is done with adiabaticclock generators that are of three main types: chargerecycling [9], tank capacitor [9] and resonant clocks. Theefficiency of the clock generators for charging anddischarging a capacitive node is compared tocomplementary or CMOS charging of similar node.Charge recycling clocks recycle the charge between phas-es and the efficiency compared to complementary charg-ing is (M-1)/M*100% (M=number of phases). If numberof phases is increased efficiency is increased but controlcy cle is longer too, which lowers the maximum usablefrequency. Tank capacitor clocks store the charge in tankcapacitors and their efficiency is N/(N+1)*100%(N=number of tank capacitors). Again higher efficiencycauses slower operation because of longer control cycle.Resonant clocking is based on natural resonance of a LC -

16


circuit. Its efficiency can be even over 97%. The seriesresistance of the circuit can dampen the resonance andwith resonant clocking as small series resistance as possi-ble should be designed. The power consumpted at the lineand coil series resistances is(1),

when both ends of the coil are oscillating and have a loadcapacitance C. Resonance efficiency is thus (1-π2fRsC/2)*100%. Also the MOSFET channel resistance could beadded to the series resistance - of course only some ap-proximation could be used because channel resistance isvarying all the time as well as the load capacitance C.Power is consumpted also at the switching MOSFETchannel-resistances, which reduces the efficiency. Shortercontrol pulse duration decreases MOSFET channelpowerconsumption, but no significant difference has beendetected with pulses that have duty cycle under ~25%.Highest adiabatic clocking frequency can be achievedwith the resonant clocking because it has the shortestcontrolling cycle. Also the control logic consumes powerwhich means that no efficiency will be get if the adiabaticcircuit is too small. This means that the controller shouldbe optimized to get a maximum efficiency and also theswitching MOSFETs should be as small as possible sothat they would have a small gate capacitance.

Conclusions

Adiabatic clock power generators, especially resonantclocking can generate high efficiency for charging anddischarging a capacitive load. Adiabatic clocking providesboth clock and power for the logic -circuit which can be agreat advantage compared to CMOS where both clock andsignal charging are usually nonadiabatic. Because of thepower consumption of the CMOS clock power generatoradiabatic circuit should be that large that this can beovercome. With a capacitive load a power saving of 92%have been achieved when also the clock generator powerconsumption was included to the total powerconsumption. With other clock generators total powersaving has been about 50% in maximum. Clock generatorshould be optimized by the load it runs, because a toolarge clock generator causes extra power consumption.Also integration of the clock generator and adiabatic chipto a minimum area increases power saving as the parasiticcapacitive loads decrease.

References

1. M.P. Frank, Reversibility for efficient computing,PhD Thesis, MIT, Cambridge, MA, 1999

2. W.S. Mak, C.F. Chan, et. al.“An 8x8 AdiabaticQuasi_static CMOS Multiplier”, ISCAS 2000, May28-31, 2000, pp. 553-556.

3. 1 Alex G. Dickinson, John S. Denker. AdiabaticDynamic Logic. IEEE Journal of Solid State Circuits,vol. 30, no. 3., March 1995, pp. 311-315.

4. 2 Yong Moon, Deog-Kyoon Jeong. An EfficientCharge Recovery Logic Circuit. IEEE Journal ofSolid State Circuits, vol. 31, no. 4., April 1996, pp. 514-522.

5. W.C. Athas, J.G. Koller, and L.”J.” Svensson: “AnEnergy-Efficient CMOS Line Driver Using AdiabaticSwitching”. USC/ISI technical report ACMOS-TR-2a, November 3, 1993.

6. T. Shibata and T. Ohmi : "A functional MOStransistor featuring gate-level weighted sum andthreshold operations", IEEE Trans. Electron Devices,1992, 39, pp. 1444 - 1455.

7. K. Kotani, T. Shibata and T. Ohmi : "Impact of high-precision processing on the functional enhancementof neuron-MOS integrated circuits", IEICE Trans.Electron., 1996, E79 C, pp.407-414.3 Luns Tee andLizhen Zheng. Charge Recycling clocking forAdiabatic Style Logic.

8. A. Rantala, P. Kuivalainen and M. Åberg. Low powerhigh-speed neuron MOS digital-to-analog converterswith minimal silicon area, Analog Integrated Circuitsand Signal Processing., vol. 26 (2001)

9. L. “J.” Svensson and J. G. Koller. Adiabatic chargingwithout inductors. Proc. Int. Workshop on Low-Power Design, Apr. 1994, pp. 159-164.

List of publications:

Diploma theses1. J. Flak: “Adiabatic Bus-Driver in CMOS

Technology”, Master’s Thesis, University of Miningand Metallurgy (AGH), Krakow, September 2001.

2. Kosonen, Jari: Power saving in Adiabatic circuits andimplementation of Adiabatic Dynamic Logic (ADL)in 0.8 µm CMOS process, HUT, Espoo, 1999

Theses on preparation1. Rantala, Arto; PhD thesis on Neuron floating gate

MOSFET circuits2. Marjonen, Jouko; licenciate thesis on Adiabatic static

logic3. Kosonen, Jari; licenciate thesis on Adiabatic dynamic

logic and clocking

Journal papers1. J. Marjonen, M. Åberg, “A Single Clocked Adiabatic

Static Logic-A Proposal for Digital Low PowerApplications”, Journal of VLSI Signal ProcessingSystems for Signal, Image and Video technologies”,vol. 27, no. 4, 2001.

2. A. Rantala, P. Kuivalainen and M. Åberg. Low powerhigh-speed neuron MOS digital-to-analog converters

17


with minimal silicon area, Analog Integrated Circuitsand Signal Processing., vol. 26 (2001)

3. A. Rantala, S. Franssila, K. Kaski, J. Lampinen,M.Åberg, and P.Kuivalainen. Improved neuronMOS-transistors for integrated neural networkcircuits, IEE Proceedings., vol. 148 (2001)

4. A. Rantala, S. Franssila, K. Kaski, J. Lampinen,M.Åberg, and P.Kuivalainen : "High-precisionneuron MOSFET structures, IEE Electronics Letters,1999, pp. 155-157

Conference papers1. J. Flak, V. Porra: “A CMOS Adiabatic Bus-Driver –

Experimental Results”. Accepted for BalticElectronic Conference, Tallinn, October 2002.

2. J. Flak, V. Porra: “A CMOS Adiabatic Bus-Driver”.Proceedings of the 15th European Conference onCircuit Theory and Design ECCTD’01, Espoo,Finland, August 28-31, 2001.

3. J. Kosonen, P. Kuivalainen and M. Åberg.Optimization of adiabatic clock generators; BEC2000, Tallinn, October 2000

4. A. Rantala, M. Åberg and P.Kuivalainen. An 8-bitand a 10-bit Low power High-Speed Neuron MOSDigital-to-Analog Converter in 0.04 mm2 Proc.ESSCIRC'99, pp. 310-313, Duisburg, Sep. 1999.

5. A. Rantala, P. Kuivalainen and M. Åberg Low powerhigh speed neuron MOS digital-to-analog converterswith minimal silicon area NORCHIP’99, Oslo 1999

6. Marjonen, Jouko & al.: A single clocked adiabaticstatic logic NORCHIP’99, Oslo 1999

7. Kosonen, Jari & al.: Implementation of ADL gateswith CMOS 0.8 µm process, NORCHIP’99, Oslo1999

8. Rantala, Arto & al. New neutron mosfet buildingblocks for analog computation, NORCHIP’98, Lund1998.

Other activities

Adiabatic logic - seminar at Munich University ofTechnology (Prof. Nossek) 14 - 14 December, 2001.

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Blind Source Separation and Deconvolution inTelecommunications and Array Signal Processing

Erkki Oja1, Jyrki Joutsensalo2, and Visa Koivunen3

1 Leader of the Consortium. Helsinki University of Technology, Laboratory of Computer and Information Science,P.O.Box 5400, 02015 HUT, Finland; email [email protected] University of Jyväskylä, Faculty of Information Technology, Telecommunications, P.O.Box 35, 40351 Jyväskylä,Finland; email [email protected] Helsinki University of Technology, Signal Processing Laboratory, P.O.Box 3000, 02015 HUT, Finland; [email protected]

ABSTRACT

In blind source separation and deconvolution, severalinstantaneous or convolved mixtures of source signals areobserved and the sources are reconstructed from themixtures without knowing the mixing system. In thisTeletronics I project with three partners, these techniqueswere developed both theoretically and for applications inantenna array processing and in CDMAtelecommunication systems.

I. INTRODUCTION

To state the problem briefly, suppose we have aset of discrete time signals (e.g., signals arriving at aportable phone by various routes from a number of otherportable phones within the same cell, or signals arriving ata sensor array). We know or assume that each of thereceived signals is some linear mixture of a number of unknown source signals (e.g. actual output signals fromportable phones, or the signals whose superpositions aremeasured by the sensor array). Also the coefficients in themixtures are unknown. Yet, the problem is to find out thesource signals and the coefficients, given only samples ofall the mixture signals. This is called blind sourceseparation (blind, because we do not know the sourcesnor the mixing system).

The problem is clearly impossible unless somerestrictions are imposed. It turns out that if the number ofmixtures is at least as large as the number of sources, andthe sources are statistically independent and non-gaussian,

then the problem can be solved by the technique ofIndependent Component Analysis (ICA).

Deconvolution refers to the problem ofdetermining the input signal or the impulse response of asystem. Typically either the system or the input is known.The need for deconvolution arises typically fromdistortions caused by interference and multipathpropagation. In blind deconvolution, the system isunknown and its input is unobservable. Consequently, itis a more difficult task. There is a clear connection toblind source separation, too: in that technique we aredealing with multiple inputs and multiple outputs(MIMO), we observe an instantaneous mixture of sourcesignals and a matrix of mixture coefficients have to be estimated, whereas in multichannel blind deconvolution amatrix of FIR filters have to be estimated. Often, boththese problems need to be solved in order to recover theoriginal source signals.

The problems of blind source separation /deconvolution have several practical applications intelecommunications and array signal processing includinguser separation in CDMA, separating signal sources by acollection of antennas without calibrating the array, anddeconvolving channel distortions. These were the topic of research in this project.

There were three project partners, initially atHelsinki University of Technology (prof. Oja), TampereUniversity of Technology (prof. Koivunen), andJyväskylä University (prof. Joutsensalo). Prof. Koivunengot a full professor's chair at HUT and moved fromTampere in 1999 together with his Statistical SignalProcessing research group.

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In the following chapters, the outcomes of theproject are outlined.

II. BLIND AND NONPARAMETRICSTATISTICAL METHODS FOR

ANTENNA ARRAYS

a) Background / Organizational information

In this subtask, led by Prof. Visa Koivunen,blind and nonparametric statistical methods for antennaarrays were studied. The program provided funding forone full-time researcher over 3 year period. Prof.Koivunen's group is included in center of excellence(SMARAD) in research nominated by the Academy ofFinland.

b) Performance of the project

The subtask by prof. Koivunen's research groupat HUT was addressing the problem of blind andnonparametric statistical methods for antenna arrays. Thenature of the work was basic research. This is attested bya good number of publications: total of 3 journal papers and 12 international conference papers were published(see the reference list at the end of this report). In addition, a book chapter to the Review of Radio Science1999-2002 was written based on the research done in thissubtask. In terms of academic degrees one doctoral degree(D.Sc. (Tech)) and two M.Sc. degrees were earned in thissubtask. This research was among the first ones toconsider Multiple-Input Multiple-Output (MIMO) modelsin communications that are now core ideas in future(beyond 3G) wireless systems.

c) Impact

We intended that our BSS methods would be adopted by some application fields, in particular, radioengineering (antenna array signal processing) and wirelesscommunications. We intended that we would have astrong impact in basic research (citations, invitations etc.)The actual impact was largely as expected: some of ourpapers have been very well cited, we have given invitedtalks in conferences. Our work on blind receivers andsmart antennas was included as a chapter in the Review ofRadio Science 1999-2002 that defines the state of the artin radio engineering. The impact on telecom industrydepends on the future in standardization. Currently,evolution of 3G is under way and the group member areactive in beyond 3G air interface research in co-operationwith Nokia.

d) Future expectations

This is a very fruitful research area, attracting growing interest world-wide. We are certainly going topursue this research, with more flexible and complexmodels and computational techniques and with morerealistic applications. In wireless communications, MIMOsystems are among the hottest topics right now and wegot a head start to that area thanks to Teletronics program.

III. SYNCHRONIZATION AND BSS INCDMA SYSTEMS

a) Background

In this subtask, synchronization and blind signalprocessing in Code Division Multiple Access (CDMA)systems was studied by Prof. Jyrki Joutsensalo and prof.Tapani Ristaniemi at University of Jyväskylä, Departmentof Mathematical Information Technology, in cooperationwit Prof. Juha Karhunen´s and Prof. Erkki Oja’s group atHelsinki University of Technology.

b) Objectives

The group concentrated on two subproblems ofthe project: the development and application of blindsource separation and timing estimation algorithms towireless communications.

CDMA (Code Division Multiple Access)technology is a strong candidate for the evolving wirelesscommunications systems. Wideband CDMA (WCDMA)has already been selected for an air interface solution e.g.in UMTS, which will provide a multitude of services,especially multimedia, and high bit rate packet data.

b.1. Application of ICA in wireless communications

In CDMA systems the users share the samefrequency band, and thus good care must be taken to limitmutual interference. Multiuser detection (MUD) is atechnique which tries to exploit the structure ofinterference to be able to suppress it. Optimal MUD,however, is computationally exhausting, and requiresseveral system parameters to be known. As aconsequence, many suboptimal multiuser receivers andadaptive multiple access interference (MAI) suppressiontechniques have been studied extensively during the pastten years.

Recently, independent component analysis (ICA)and the closely related blind source separation (BSS)problem have attracted a lot interest both in statisticalsignal processing and neural network communities. ICAcan also be applied to the interference suppression

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problem in CDMA. There exist many motivating reasonsto use the means of ICA in the reception of a CDMAsystem. First of all, ICA provides a near-far resistantreceiver, being able to resist strong interferences.Resistance is achieved by ICA quite naturally, since ICAonly requires the source signals to be statisticallyindependent, but their strengths are allowed to differ. In CDMA the sources are, roughly speaking, users' symbolstreams, and it is hence reasonable to assume that they areindependent. Near-far resistance is one of the keyrequirements of a receiver, and it becomes even moreimportant as there is a demand for higher data rates. Thisis because many solutions for higher data rates, e.g.smaller spreading factors, and higher symbolconstellations, tend to worsen the near-far situation eitherdirectly or indirectly via e.g. power control imperfections.Secondly, the propagation delay and the state of thechannel should be estimated prior to actual symbolestimation. For subspace-type receivers also theestimation for the model order should be available. Theestimation of these parameters will always include somemeasurement errors, which degrade the accuracy ofsymbol estimation. ICA, on the other hand, doesn't needthat precise knowledge of the system's parameters, sincethe estimation is based purely on the (higher order) statistical properties of the signal. Therefore, with ICA weshould expect some robustness against erroneousparameter estimation. Thirdly, an ICA block can be usedas an add-on feature, to be attached to any existingreceiver structure. This makes it possible to considerhybrid receiver structures, in which the ICA block couldbe intelligently activated only when it is expected toimprove performance.

b.2. Code timing estimation in direct sequence (DS)CDMA systems

The final objective in the reception of a DS-CDMAsystem is to estimate the symbols which carry the data,but a prerequisite task is to get the local code generatorsynchronized to that of received signal. This meansestimation of the propagation delay, which gives therequired knowledge to the receiver about the phase of thespreading code.

Matched filter is the tradiotional method to theproblem. Although simple, it inadequate if the codeorthogonality conditions are perturbed. This happens evenin synchronous system with orthogonal codes due to theexistence of multipaths with different delays. Moreover, ifthe desired signal is much weaker than the interferingsignals, which is commonly known as a near-far problem,matched filter techniques can totally collapse. Mostpromising performance with low computation can beachieved by so called differentially coherent/non-coherentalgorithms, where the effects of interference aresuppressed by correlating the matched filter output with a

delayed version of it. The goal in this project was to futherdevelopment of differentially coherent algorithms, inorder to gain more interference mitigation capabilities andhigher resolution.

c) Results

Regarding the application of ICA to wirelesscommunications, many ICA/BSS methods weresuccesfully applied in this Teletronics project to blindmulti-user detection in DS-CDMA. Especially, FastICAwas found the most suitable due to its simplicity andfastness. The performance of ICA/BSS methods wascompared to existing methods, and also some theoreticalresults on the convergence were made. In addition, newreceiver structures were proposed. Recall that in blindsource separation there is no control which source isseparated. A CDMA application in mind it is thus notmeaningful to use ICA on its own, since the desired signalis well identified by the user-specific spreading code. Therefore, hybrid receiver structures were proposed,where ICA was considered as a post-processing tool forconventional detection (RAKE). By doing this, also thestatistical independence of the users' signals can beexploited. In addition, it makes it possible to alleviate theperformance drop due to the erroneous parametersestimation in the receiver. The reseach resulted in onejournal article, one patent pending, a number of conference papers and two invited international talks.

Regarding code timing estimation, many newalgorithms were proposed and compared to existing ones.In addition, the average time used to delay estimation wasanalyzed analytically. Improved interference mitigationand higher resolution was achieved with so called DC-MUSIC algorithm, in which traditional multiple signalclassification (MUSIC) was modified into differentialmode. In this way, traditional MUSIC no more sufferfrom high system loads, since differential correlationseffectively filters interference prior to actual delayestimation. Also another method for fine estimation wasproposed, in which differential correlations enabled theestimation of the fractional part of the delay by solving asystem of two second-order polynomials for each codechip interval. The reseach resulted in one journal article,one patent pending, one book chapter, and a number ofconference papers.

REFERENCES

1) Chapter 23: ``Telecommunications'', pp. 417-440 inthe book Hyvärinen, A., Karhunen, J., and

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Oja,E.,”Independent Component Analysis''. JohnWiley, New York, 2001. 481+xxii pages.

2) R.Cristescu, J. Karhunen, J. Joutsensalo and T.Ristaniemi, “Blind Separation Methods for CDMACommunications,” Proc. The Learning Workshop,Snowbird, Utah, USA, April 2000. (invitedpresentation)

3) Cristescu, R., Joutsensalo, J., Karhunen, J., and Oja,E., ``A Complexity Minimization Approach forEstimating Fading Gaussian Channel in CDMACommunications'', in Proc. of the 2nd Int. Workshopon Independent Component Analysis and BlindSource Separation (ICA2000), Espoo, Finland, June19-22, 2000, pp. 527-532.

4) Cristescu, R., Ristaniemi, T., Joutsensalo, J, andKarhunen, J., ``Delay Estimation in CDMACommunications Using a Fast ICA Algorithm'', inProc. of the 2nd Int. Workshop on IndependentComponent Analysis and Blind Source Separation(ICA2000), Espoo, Finland, June 19-22, 2000, pp.105-110.

5) Cristescu, R., Ristaniemi, T., Joutsensalo, J., andKarhunen, J., ``Blind Separation of ConvolvedMixtures for CDMA Systems,'' in Proc. of the XEuropean Signal Processing Conference (EUSIPCO2000), Tampere, Finland, September 5-8, 2000, pp.619-622.

6) Cristescu, R., Ristaniemi, T., Joutsensalo, J., andKarhunen, J., ``CDMA Delay Estimation Using aFast ICA Algorithm'', in Proc. of the IEEE Int. Symp.on Personal, Indoor, and Mobile Communications(PIMRC'00), London, United Kingdom, September17-19, 2000, pp. 1117-1120.

7) Cristescu, R., Joutsensalo, J., and Ristaniemi, T.,``Fading Channel Estimation by Mutual InformationMinimization for Gaussian Stochastic Processes'', inProc. of IEEE Int. Conf. On Communications(ICC2000), New Orleans, LA, USA, June 18-22,2000, pp. 56-59.

8) Cristescu, R., ``Applications of IndependentComponent Analysis in Telecommunications andImage Processing''. Lic. Tech. thesis, Helsinki Univ.of Technology, Dept. of Computer Science andEngineering, November 2000.

9) Enescu, M., Koivunen, V., (2000) “Tracking TimeVarying Mixing System in Blind Separation,” InIEEE Sensor Array and Multichannel Signal

Processing (SAM-2000), pp. 291-295, Boston, USA,March 15-17, 2000.

10) Enescu, M., Koivunen, V., (2000) “RecursiveEstimator for Separation of Arbitrarily KurtoticSources.” IEEE Statistical Signal and ArrayProcessing 2000, pp. 301-305. Pocono Manor, PA,USA.

11) Enescu,M., Zhang, Y., Kassam, S.A., Koivunen, V.,(2001) “Recursive Estimator for Blind Equalizationvia BSS and Fractional Sampling.” 2001 IEEE ThirdWorkshop on Signal Processing Advances inWireless Communications, SPAWC'01, Taoyuan,Taiwan, R.O.C, March 20-23, 2001. pp. 94-97.

12) Enescu, M., Sirbu, M., Koivunen, V., (2001)“Recursive Semi Blind Equalizer For Time VaryingMIMO Channels,” The 11th IEEE Workshop on Statistical Signal Processing, Singapore, August2001. pp. 289-292.

13) J. Joutsensalo ja T. Ristaniemi, “Synkronointikorrelaatiomenetelmällä hajaspektrijärjestelmässä(Synchronization by Correlation Method in SpreadSpectrum System)”, patenttihakemus (patentpending), 1999.

14) J. Joutsensalo ja T. Ristaniemi,“Hajaspektrijärjestelmän vastaanotin (Receiver forSpread Spectrum System)”, patenttihakemus (patentpending), 2000.

15) J. Joutsensalo and T. Ristaniemi, “LearningAlgorithms for Blind Multi-User Detection in CDMADownlink,” Proc. 9th IEEE International Symposiumon Personal, Indoor, and Mobile RadioCommunications, Boston MA, USA, September 8-11,1998, pp. 1040-1044.

16) J. Joutsensalo and T. Ristaniemi, “Synchronization byPilot Signal,” Proc. IEEE International Conference onAcoustics, Speech, and Signal Processing, Phoenix,USA, March 15-19, 1999, pp. 2663-2666.

17) J. Joutsensalo and T. Ristaniemi, “Single UserSynchronization in Fading Channel,” Proc. IEEE 2ndWorkshop on Signal Processing Advances inWireless Communications, Annapolis, Maryland,USA, May 9-12, 1999, pp. 133-137.

18) J. Joutsensalo and T. Ristaniemi, “Blind Multi-UserDetection by Fast Fixed Point Algorithm withoutPrior Knowledge of Symbol-Level Timing,” Proc. IEEE Signal Processing Workshop on Higher Order

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Statistics, Ceasarea, Israel, June 14-16, 1999, pp.305-308.

19) J. Joutsensalo and T. Ristaniemi, “TimingAcquisition in Fading Channels by DifferentiallyCoherent Method,” Proc. International Workshop On Mobile Communications, Grete, Greece, June 24-26,1999, pp. 327-334.

20) J. Joutsensalo and T. Ristaniemi, “MMSE BasedSingle User Timing Acquisition in CDMA,” Proc. 6thIEEE International Conference on Electronics,Circuits and Systems, Paphos, Cyprys, September 5-8, 1999, pp. 1293-1296.

21) J. Joutsensalo and T. Ristaniemi, “Delay Estimationin CDMA System by Differentially CoherentEigenanalysis,” Proc. 6th IEEE InternationalConference on Electronics, Circuits and Systems,Paphos, Cyprys, September 5-8, 1999, pp. 1279-1282.

22) J. Joutsensalo and T. Ristaniemi, “DifferentiallyCoherent Initial Timing Acquisition in CDMASystem”, Proc. 50th IEEE Vehicular TechnologyConference, Amsterdam, The Netherlands,September 19-22, 1999, pp. 708-712.

23) J. Joutsensalo and T. Ristaniemi, “MMSE OptimalDelay Estimation in CDMA System”, Proc. 50thIEEE Vehicular Technology Conference,Amsterdam, The Netherlands, September 19-22,1999, pp. 739-742.

24) J. Joutsensalo and T. Ristaniemi, “TimingAcquisition in CDMA System,” in P. Stavroulakis(ed.) Third Generation Mobile TelecommunicationSystems, Springer-Verlag, 2001.

25) Koivunen, V., Oja, E., (1999) “Predictor-correctorstructure for real-time blind separation from noisymixtures,” In ICA'99, Aussois, France, pp. 479-484.

26) Koivunen, V., Enescu, M., Oja, E., (2001) “AdaptiveAlgorithm for Blind Separation from Noisy Time-Varying Mixtures,” Neural Computation, 2001. Vol.13, nro 10, pp.2339-2357.

27) Koivunen, V., Oja E., (2001) “Blind Methods inCommunications Signal Processing,” (In Finnish)Prosessori, No. 11, pp. 65-67. 2001

28) Möttönen, J., Oja, H., Koivunen, V., (1999) “Robustautocovariance estimation based on sign and rank correlation coefficients.” IEEE HOS'99, pp. 187-190.

29) T. Ristaniemi and J. Joutsensalo, “Novel Scheme forBlind Symbol Separation in CDMA Downlink,”Proc. 32th Asilomar Conference on Signals, Systems,and Computers, Monterey CA, USA, November 1-4,1998, pp. 1853-1857.

30) T. Ristaniemi and J. Joutsensalo, “On thePerformance of Blind Source Separation in CDMADownlink” Proc. International workshop onIndependent Component Analysis and SignalSeparation, Aussois, France, January 11-15, 1999, pp.437-442.

31) T. Ristaniemi and J. Joutsensalo, “IterativeAlgorithms for Blind Interference Suppression inCDMA”, Proc. IEEE 2nd Workshop on SignalProcessing Advances in Wireless Communications,Annapolis, Maryland, USA, May 9-12, 1999, pp.203-206.

32) T. Ristaniemi and J. Joutsensalo, “NonlinearAlgorithm for Blind Interference Cancellation”, Proc.IEEE Signal Processing Workshop on Higher Order Statistics, Ceasarea, Israel, June 14-16, 1999, pp. 43-47.

33) T. Ristaniemi and J. Joutsensalo, “AccurateDifferentially Coherent Code Acquisition in DS-CDMA with Fading Channel”, Proc. InternationalWorkshop On Mobile Communications, Grete,Greece, June 24-26, 1999, pp. 341-347.

34) T. Ristaniemi, “Code Acquisition in CDMACommunication System with Fictitious PilotSignals,” Proc. 6th IEEE International Conference onElectronics, Circuits and Systems, Paphos, Cyprys,September 5-8, 1999, pp. 1273-1277.

35) T. Ristaniemi, “Accurate Pilot Assisted PN CodeAcquisition,” Proc. 50th IEEE Vehicular TechnologyConference, Amsterdam, The Netherlands,September 19-22, 1999, pp. 723-727.

36) T. Ristaniemi and J. Joutsensalo, “IndependentComponent Analysis with Code InformationUtilization in DS-CDMA Signal Separation,” Proc.IEEE GLOBECOM'99, Rio de Janeiro, Brazil, December 5-9, 1999, vol. 1a, pp. 320-324.

37) T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based Receivers for DS-CDMA Systems,” Proc. 11thIEEE International Symposium on Personal, Indoor,and Mobile Radio Communications, London,September 18-21, 2000, pp. 276-281.

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38) T. Ristaniemi and J. Joutsensalo, “Code TimingAcquisition for DS-CDMA in Fading Channels byDifferential Correlations,” IEEE Transactions on Communications, vol. 49, no. 5, May 2001, pp. 899-910.

39) T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based Receivers for Block Fading DS-CDMAChannels,” Signal Processing, vol. 82, no. 3, 2002,pp. 417-431.

40) T. Ristaniemi and J. Joutsensalo, “Code TimingAcquisition for DS-CDMA in Fading Channels byDifferential Correlations,” IEEE Transactions on Communications, vol. 49, no. 5, May 2001, pp. 899-910.

41) T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based Receivers for Block Fading DS-CDMAChannels”, Signal Processing, vol. 82, no. 3, 2002,pp. 417-431.

42) Visuri, S., Oja, H., Koivunen V.,(1999)“Multichannel Signal Processing using RankCovariance Matrices,” IEEE-EURASIP NSIP'99,Vol. I, pp. 75-79.

43) Visuri S., Oja, H., Koivunen, V., (2000)“Nonparametric Statistics for DoA Estimation in thePresence of Multipath.” In IEEE Sensor Array andMultichannel Signal Processing (SAM-2000), pp.356-360, Boston, USA, March 15-17, 2000.

44) Visuri, S., Oja, H., Koivunen, V., (2000)“Nonparametric method for subspace basedfrequency estimation,” EUSIPCO-2000, Tampere,Finland, pp. 1261-1264.

45) Visuri, S., Oja, H., Koivunen, V. (2000) “RobustSubspace DoA Estimation for WirelessCommunications.” IEEE VTC-2000, pp. 2551-2555,Tokyo, Japan.

46) Visuri, S., Koivunen, V., Oja, H. (2000) “Rank andSign Covariance Matrices, Journal of StatisticalPlanning and Inference,” Vol. 97, No. 2, pp. 557-575.

47) Visuri, S., Oja, H., Koivunen, V., (2001) “Directionof Arrival Estimation Based on NonparametricStatistics.” IEEE Transactions on Signal Processing,2001. Vol. 49, nro 9, pp. 2060-2073.

48) Visuri, S., Oja, H., Koivunen, V., (2001) “Blindchannel identification using robust subspaceestimation.” The 11th IEEE Workshop on Statistical

Signal Processing. Singapore, August 2001. pp. 281-284.

49) Visuri, S., Koivunen, V., Terho, L., “Direction ofArrival Estimation in Nonstandard Conditions UsingNonparametric Statistics.” NATO set Symposium onPassive and LPI Radio Frequence Sensors, CD-ROMProceedings, Warsav Poland, April 21-25, 2001.

24


Personal Access and User Interface for Multi-modal BroadbandTelecommunication (PAULA)

Petri Pulli*, Ismo Rakkolainen**, Jukka Vanhala**, Tapio Takala***, Pentti Karioja****

* University of Oulu,** Tampere University of Technology,*** Helsinki University of Technology**** VTT Electronics, Oulu

ABSTRACT

Advances in broadband telecommunications, multimedia and virtual reality are expanding human-computerinteraction. In addition to normal text and multimedia,increasing levels of telepresence and immersion, including3D vision, 3D sound, touch and gestures, will be brought toour consciousness through our senses. Although there existwell-developed single modalities for communication, we donot really understand the general problem of designingintegrated multimodal telecommunication systems. Yet, managing these modalities is needed for successfulimplementation of future broadband telecommunicationproducts and services. Recent advances in mobilecommunication based on picocellular technologies allowthe transmission of high-bandwidth of data over PersonalSurrounding Networks (PSN). The technology offers morefreedom for the design of mobile multimodal 3D userinterfaces but does not solve the design problem.

In the PAULA project, we study and apply new andadvanced approaches of mobility and augmented reality to multimodal user interfaces, developed essential technology,general architecture and integration framework. Weexperiment with and demonstrate potential futureapplication by building prototypes and scenarios. Theresearch team is formed among the most advancedresearchers of telecommunication electronics, digital media, user interface and virtual reality in Finland. The research results help to scientifically prepare way for theFinnish telecommunication industry’s continued growth inthe next millennium with new products and services formobile broadband telecommunication.

I. INTRODUCTION

Recent visionary research [1] strongly suggests futureinformation society going towards virtualisation. Examplesof proposed virtual telepresence based services are: virtualmeetings, electronic shopping, games and entertainment,

guiding and tourist services, virtual village, virtual family,personal memory support systems.

Our research is based on the emerging understandingthat there is a major trend towards personal advancedtelecommunication services. “Personal” means that theseservices are mobile and conveniently available wheneverand wherever we want/need to participate incommunication activities. The PAULA project was along-term scientific study for how we are going to bringfuture increasing communication bandwidth andcomputing performance to the personal vicinity andpersonal use of individual human beings, meaningeveryone of us. We focused on the scientific study ofuser-interaction layer of the future broadband personaltelecommunication products and services. Through better understanding of user interaction issues of futuretelecommunication services we believe that, besidesscientific contributions, we have increase the potential forthe Finnish telecommunication product and serviceindustry to compete world-wide also in the future.

II. Research Approach

Scientifically we are utilising two major approaches toextend the use of computing and communicationresources: "ubiquitous computing" and "augmentedreality". "Ubiquitous computing" is a term coined byWeiser [2] to mean a situation, where smallcomputational devices are embedded into our everydayenvironment in a way that allows them to be operatedseamlessly and transparently. These devices are activeand aware of their surroundings so that they can react andemit information when needed. One implementation ofubiquitous computing are active badges, which can triggerautomatic doors and give information about the locationof a person. Weiser's team and others at Xerox haveexperimented the idea by using several types of devices,like small pager-sized "Tabs", notebook-sized "Pads" andwhiteboard-sized "Boards" [3].

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"Augmented reality" [4, 5, 6, 7] is a research approachthat attempts to integrate some form of computer mediawith the real world. When in ubiquitous computing thereare many different active devices, in many cases each ofthem having their own display and interaction devices, theaugmented reality approach usually uses much fewerdevices and aims at a seamless integration between real and digital. The integration may be between paper andelectronic documents, like in DigiDesk [4], or even morecommonly overlaying digital information (as a non-immersive virtual reality) on real world images [5]. Theoverlaying of images may take place in several ways, likeby using video projection [4, 8], by the means of small,hand-held video screens or palmtop computers [6], bymixing surrounding reality with non-immersive VR byusing head-mounted see-through displays [4, 9] orthrough haptic displays [10].

The core idea of our approach has been to use veryshort distance broadband wireless communicationnetwork to mix these two approaches. Thus we suggest,"ubiquitous computing" in the form where differentdevices in spaces and places we move around are computationally active and can recognise our presenceand identity. But instead of a multitude of differentdisplays and interaction devices that the interaction withall devices would take place in an "augmented reality",for example by using a head-mounted see-through displayand a mobile phone/remote controller.

Several networked virtual reality environments [11,12, 13, 14] exist today, but none of them supportsmobility of users. Most of the networked environmentsare based on Internet, which could be easily replaced by a mobile multimedia wireless network like SWAN [15]providing mobile connections. However, typical currentlyavailable applications and their interfaces, based on immersive virtual reality and heavy desk-top computers,would still restrict the user’s ability to move and accessservices in a natural and convenient way. In the Nara Institute of Science and Technology in Japan [16] anexperimental mobile virtual reality system is beingdeveloped. This system, like our experimental system[17] is based on augmented reality merging both real andvirtual environments to provide totally new telepresenceservices and interfaces to mobile users.

The backbone of the mobile virtual reality is awireless broadband picocellular personal surroundingnetwork (PSN). The PSN network connects user’spersonal mobile terminals like a head-mounted-display or a pen-shaped input device and provides mobile access to other mobile and fixed networks as depicted in Fig 1.

ing network

Picocellular networkcontaining personal

Personal surround-

surrounding networks

National network contain-ing macro networks

Macro network containingpicocellular networks

ing of national networksGlobal network consist-

��

��

Figure 1. The hierarchy of different mobile networks.

The benefits of using very small cells in mobile virtualreality are obvious. The smaller the cell size, the higherthe throughput, because there are fewer users in each celland higher transmission frequencies can be used. Usuallyvery high frequencies are not used in mobile networks,because of quick signal attenuation, but if thetransmission range is just a few meters, the effect ofattenuation is almost negligible. In addition, smaller cellsize enables greater frequency reuse. The diameter of a PSN cell in our system is going to be some three meters,which enables the construction of small very low-powered hand held or wearable terminals still capable oftransmitting high-bandwidth (> 1Mbit/s) multimedia datarequired by broadband services such as virtual realityapplications.

Conventional mobile networks consisting of verysmall cells have two serious drawbacks: The number of base stations and handovers will be enormous. In oursystem adjacent PSNs can change information directlywithout using a fixed base station. This does not onlyenable wireless communication between user’s personalterminals but makes it possible for two users to transmitdata to each other directly too. In fact each user’s personalsurrounding network constitutes a mobile base station,which can forward traffic packets between a fixed basestation and some user outside the cell around the basestation. In this way the number of expensive base stationsneeded can be greatly reduced. The number of handoverscannot be reduced, unless users’ ability to move is

26


restricted. But handovers can be made more transparent to the user by e.g. multicasting same data packets to adjacentcells [18]. When a handover occurs, i.e., the user changesa cell, new data packets are already in the new cell andthe user does not have to wait the time it takes to forwardthe data packets from the old cell to the new one. Anotherproblem related to handovers is the availability of services. When a user changes a cell, does the new cellprovide the same services as the previous one. In spite of implementing the same services in each network nodeincluding the mobile PSNs, it may be more reasonable toget services on demand using e.g. mobile agents [19]. Soin addition to data, knowledge about the services requiredby the user should be multicast to adjacent cells to provide transparent handovers.

In Fig. 2 a block diagram of the mobile virtual realitysystem is given. The main components of the system are a fixed base station providing access to fixed networks andtheir services, personal mobile terminals including virtualreality devices and a mobile base station providingconnections between mobile terminals and a fixednetwork. User’s virtual reality devices contain input andoutput devices and an advanced position tracking system.As an output device we use a see-through high resolutionhead-mounted-display (HMD), with which we augmentthe real world electronics and telecommunicationproducts with virtual properties and interfaces. As an input device use a 3D pen mouse, which provides verynatural way of entering data e.g. editing a text file. Inorder to provide a reasonable augmented reality weshould track both the output and input devices veryprecisely. Several methods for tracking the position exist.From these an electromagnetic method based on spread-spectrum communication providing an accuracy of a fewmillimetres [20] seems to be most promising for ourpurposes.

Position tracking device

Personal mobile terminals

Microphones

Data Gloves

Head mounted display

Gyroscope

User’s VR device

Fixed base station

Connectionand mobilitymanager

Haptic

Visual

Collision

Position manager

renderer

renderer

managerObject manager

Fixed network

Mobilenetwork

User’s mobile equipment

Personal surroundingnetwork

Userdatabase

Processing unit

Figure 2. The components of the proposed experimental researchenvironment for personal broadband telecommunication services.

>

III. RESULTS

AD-hoc networks & accurate Indoor trackingLiving Room is a project that concentrates on the user

interface design in the home environment. The livingroom itself is a laboratory room of about 40 m2 that hasbeen converted into a typical single room apartment. Theroom is instrumented with pressure sensors under thefloor, 20 individually controllable light fixtures, computercontrollable curtains, electronic locks, etc. Theinfrastructure for two-way communication between thesmart objects is based on in-house developed IR and RF communication systems. The principle is that all objectsthat are brought into the smart room are instrumented andintelligent.

Display for a Wearable ComputerThe purpose of this work was to design and construct

a small and light head-mounted monocular display, whichcould be used with wearable computers. The original plan was to make the display device as general-purpose aspossible. During the design process it was decided, thatthe display would be used with a wearable computersystem being built at TUT electronics lab. This wearablecomputer is designed to be used in industrialenvironments.

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As the starting point of the display system a miniaturedisplay component was selected. The resolution of thisdisplay, the Kopin CyberDisplay 320C, is 320 x 240 pixels. The optics designed for the display component wasbased on the principle of the simple magnifier. In order tominimize distortions the optics consists of two achromaticlenses. The head-mounting system of the display is afolding frame going around the back of the head. Thisenables the use of eye glasses simultaneously with thedisplay system. The designed display driver circuitaccepts industry standard 640 x 480 pixels at 60 Hz analog VGA-signal. Central sections of the electronics arean AD-converter, buffer memories, a DA-converter, an analog video amplifier and a programmable logic device,which controls the digital part of the system.

The constructed display driver board fulfils all setrequirements, and the picture quality of the display systemis good.

Differential GPS in Wearable ComputersWearable computers and other portable devices are

becoming more popular every day. These appliancesallow the development of location sensitive applications,which require an accurate and reliable positioningmethod. The objective of this work was to implement apositioning method for wearable computers to serve aresearch project on location aware applications andwearable computing at TUT Electronics Laboratory. Thework describes methods for improving Global PositioningSystem (GPS) performance using differential GPS(DGPS) methods. A sophisticated method was developedfor improving DGPS performance by aiding positioningwith carrier phase measurement processing during poor satellite geometry. The DGPS system was developedpurely for research purposes and as such it serves theresearch of wearable computing and positioning well.

Deviceless User InterfacesIn the first PAULA project at the University of Oulu,

research concentrated on aspects of the user-interfaces formobile users based on Augmented Reality technology andequipment, the problems associated with these devicesand appropriate telecommunication services for thesemobile users. During the course of our research on thesetopics, the results suggested that a gradual shift of focuswas needed. In terms of the User Interface (UI), lessemphasis should be placed on the devices needed to provide a UI, but more so on the UI itself. This lead to theconcept of 'deviceless' User Interfaces, whereby a non-obtrusive device can provide various UI according to thedesired situation. Work on this concept is well under wayand the first prototype of the system, called MARISIL[http://marasil.org] is complete and shown in figure 3.

Figure 3. MARISIL concept for a deviceless userinterface.

Visual CellsNew telecommunications services suitable for a

mobile user were also investigated during the PAULAproject. Experiments were carried out using aTelepresence system to enable a mobile user attend ameeting while on the move. The results of these testsdemonstrated that not only is current technologyinsufficient to support the mobile user, but that enablingthe technology to support the mobile user could open uppossibilities in the manner in which future VirtualEnterprises can work. To increase the power of the mobileuser a concept called 'Visual Cells' is under development.The Visual Cells concept is based on Augmented Realitytechnology and aims to provide a highly interactive localenvironment for a mobile user, allowing mobile users to'carry' their virtual office with them. Additionally, it alsoallows the mobile user to be 'teleported' virtually to aremote office and environment while still retaining notonly the resources of their own local environment, butalso access to the remote environments resources.

Spatial Augmented RealityAccurate registration of objects in AR is difficult so in

the PAULA project a dual registration system, usingmagnetic and visual tracking was implemented. Thissystem provides an improved registration compared tomagnetic tracking alone

3Dcity Info.TUT Digital Media Institute (DMI) has built a 3D City

Info system, which combines databases, 2D maps and 3Dvisualizations. The usability studies show that usersgreatly prefer 3D views over symbolic 2D maps, althoughboth may be needed. The system uses Java 2 and JavaJDBC API and is thus platform-independent. Also a steer-ing wheel navigation and an immersive Java3D userinterface has been developed for VRML scenes.

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In Paula-project, the system was adapted for mobileuse by integrating a GPS, a digital compass, a laptop PC,and optionally a wireless broadband connection to thesystem.

IV IMPACT

The major impact of the project has affected a numberof research fields for mobile Augmented Reality systems.An improved Tracking and registration system willimprove the accuracy and operation of mobile Augmentedreality systems, using both differential GPS and visualimage recognition tracking. The 3d City Info system formobiles has developed new 3D interfaces and outdoortracking and mobile services. A new interface handgesture language called MARISIL was designed andpatented. A Visual cell metaphor was developed that canbe used for designing better presence services.

Many of the research results for the PAULA projectwere directly impacted in the EU Wireless StrategicInitiative (WSI) Book of Visions 2000 and WWRF book of Visions 2001. Both of these books are seen as a precursor to research activity for 4th generation mobilesystems.

REFERENCES

[1] Thalmann D. From Multimedia to Telepresence. In:Konidaris, S. (coordinator): Communications forSociety, Visionary Research. European CommissionDG XIII/B. Brussels. February 1997. Pp. 173 - 195.

[2] Weiser, M. (1991) The Computer for the 21stCentury. Scientific American, 265 (3), pp. 94-104.

[3] Buxton, W. (in press) Living in Augmented Reality.Ubiquitous Media and Reactive Environments. Toappear in Finn, Sellen & Wilber (Eds.) VideoMediated Communication. Hillsdale, N.J.: Erlbaum.

[4] Wellner, P., Mackay, W., and Gould, R. (1993)Computer Augmented Environments: Back to theReal World. Introduction to the special issue.Commun. ACM, Vol 36 No. 7 (July 1993), pp. 24-26.

[5] Feiner, S., Macintyre, B., and Seligmann, D. (1993) Knowledge-based augmented reality. Commun.ACM, Vol 36 No. 7 (July 1993), pp. 52-62.

[6] Fitzmaurice, G.W. (1993) Situated InformationSpaces and Spatially Aware Palmtop Computers.Commun. ACM, Vol 36 No. 7 (July 1993), pp. 38-49.

[7] Cooperstock, J. R., Tanikoshi, K., Beirne, G.,Narine, T., and Buxton, W. (1995) Evolution of a reactive Environment. Proceedings of CHI'95, NewYork: ACM Press, pp. 170-177.

[8] Stafford-Fraser, Q. (1996) BrightBoard: A Video-Augmented Environment. Proceedings of CHI'96,New York:ACM Press, pp. 134-141.

[9] MacIntyre B., Feiner S. (1996) Future multimediauser interfaces. Multimedia Systems (1996) 4:250-268.

[10] Burdea, G.C. (1996) Force and Touch Feedback forVirtual Reality. Wiley, NY. 339 p.

[11] Carlsson, C. and Hagsand, O.: DIVE-a Multi-UserVirtual Reality System. In Proceedings of the IEEE Virtual Reality Annual Symposium, September 18-22, 1993, Seattle, Washington, USA, pp. 394-400.

[12] Shaw, C., Green, M., Liand, J., and Sun, Y.: Decoupled Simulation in Virtual Reality with TheMR Toolkit. ACM Transactions on InformationSystems 11(3), 1993, pp. 287-317.

[13] Snowdon, D. and West, A.: The AVIARY VR-system. A Prototype Implementation. InProceedings of the 6th ECRIM Workshop, June,1994, Stockholm, Sweden.

[14] Tarr, R. and Jacobs, J.: Distributed InteractiveSimulation (DIS). In Proceedings of the 1994 Summer Computer Simulation Conference, July18-20, La Jolla, California, USA.

[15] Agrawal et al: SWAN: A Mobile MultimediaWireless Network. IEEE P. Comm., 3(2), 1996,pp. 18-33.

[16] http://isw3.aist-nara.ac.jp/IS/Chihara-lab/[17] Pulli P., Antoniac P., Hickey S. 1999 Mobile

Telepresence Services for Virtual Enterprise,Proceedings of the 5th International Conferenceon Concurrent Enterprising (ICE’99), 281-292,Hague

[18] Ghai, R. and Singh, S.: An Architecture andCommunication Protocol for PicocellularNetworks. IEEE Personal Communications, 1(3), 1994, pp. 36-46.

[19] Liu, G. and Maguire, G. Jr.: A Virtual DistributedSystem Architecture for Supporting Global-Distributed Mobile Computing. Technical ReportTRITA-IT 95-01, Royal Institute of Technology,1994.

[20] Bible, S., Zyda, M., and Brutzman, D.: UsingSpread-Spectrum Ranging Techniques for PositionTracking in a Virtual Environment. In Proceedingsof the 1995 Workshop on Networked Realities,October 26-28, 1995, Boston, MA, USA.

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Integrated circuit solutions for adaptive and wideband wireless communicationsystems

Veikko Porra, Kari Halonen

Helsinki University of Technology, Inst. Of Digital Communications, Electronic Circuit Design LaboratoryPOB-3000, Otakaari 5A, FIN-02015 TKK

[email protected]

ABSTRACT

The rapid expansion of cellular mobilecommunications and the new third-generation systemspecifications towards the Universal MobileCommunication System (in Europe UMTS and world-wideIMT 2000) have stimulated the development of newtechnologies for wireless terminals with a high level ofcircuit integration. Multimode terminals with adaptability to many co-existing old and new standards and seviceswill be needed. The requirements of low production costsand low-power can only be met by high circuit integrationlevel. Three promising areas of novel integrated analogueand mixed A/D circuit design can be identified: (1) Newsystem architectures with new adaptive analogue andmixed digital-analogue, self-calibrated circuit blocks have to be developed. (2) For very high data rates monolithic60GHz transceivers may become feasible, and (3) forextremely fast, highly parallel, and low-power imageprocessing, a future processor architecture may be a cellular nonlinear network (CNN). These topics wereincluded in the Telectronics-project of HUT/ECDL. Inthe present report, the results of the project during 1998-2001 are summarized.

I. INTRODUCTION

The project is an extension of an earlier projectsupported by the Academy of Finland (SAAR, projectNr. 37713): Adaptive radio architectures andtechnologies for new radio systems, sub-project 3:Design and modeling of adaptive low-voltage integratedanalog circuits, A/D-circuits and RF-circuits for wirelesscommunication.

The objectives listed in the original research programwere the following:

1. Adaptive RF circuits for 'smart' antennas2. Integrated 60 GHz circuit blocks for wireless

multimedia systems3. Integrated implementation of Cellular Neural

Networks and chaos dynamics

Already before beginning of the project, some re-adjustment of the individual objectives turned out to benecessary. Making a wider circuit integration possible inwideband radio systems requires deep architecturalmodifications. These modifications change the borderlinebetween analogue and digital circuits, and betweenhardware and software blocks. Therefore, the firstobjective: Adaptive RF circuits for 'smart' antennas hadto be replaced by a more system-oriented consideration ofthe adaptability of a radio circuitry to differentspecifications. The key words were found to be 'softwareradio', the direct conversion receiver and use of mixedanalogue and digital circuits in the synthesis of modulated signals. The original idea to control theantenna matching was found problematic and was finallyabolished because of the intermodulation problemsconnected with the non-linearities of the impedancematching circuits. The final objectives were selected to

be:

1. Adaptive RF, analogue and mixed analogue anddigital integrated circuit design for wirelesscommunication systems

2 Integrated 40-60 GHz circuit blocks for wirelessmultimedia systems

Telectronics: IC Solutionsfor Adaptive and WidebandWireless Communication Systems

Integrated 40-60GHzcircuit blocks, 36 pmo

TEKES-LALAMO60GHzWirelessModems

Adaptive RF, anal.and mixed IC’s 70 pmoCNN/CHAOS

113 pmo 217pmo pmo

TEKES-ORAVAT-SUMU etc.INWITE-HIGH SPEED A/DAdaptive radio receiversDirect conversion receivers>300 pmo

70 pmo

Academy of F. 1999-2002CNN Integratedparallel processorsmultimedia50 pmo (+40pmo/02)

ESPRIT- INSPECT2: FM-DCSKChaos Radio 36 pmo

31


3. New nonlinear circuit applications: Cellular non-linear networks (CNN) for telecommunicationapplications and image processing; use of chaosdynamics in spread-spectrum communication systems

These sub-project names will be used in the followingproject summary.

Other projects on the same topic

During 1998-2001, the following other projects werecarried out partly or fully in the same subject area (Theamount of research work carried out within theTelectronics project objectives is given in person months,pmo):

1 TEKES- projects, more than 300 person months (pmo)in the area of Telectronics (Kari Halonen)- High speed A/D Conversion in INWITE program- ORAVAT –‘ Integrated circuits for adaptive radio receivers’ in ETX program and- SUMU – ‘Direct conversion radio receivers’ in ETX

2 LALAMO, TEKES, 70 pmo, (Veikko Porra)Wideband Wireless Modems, Integrated MillimeterWave Circuit Blocks

3 INSPECT, ESPRIT/LTR, 36 pmo (Veikko Porra), Innovative Signal Processing using Chaos Theory,circuit techniques for a 2.4GHz radio system based onfrequency-modulated chaos-shift keying (FM-DCSK)

4 CNN, Academy of Finland , 50pmo 2000-2002 (KariHalonen) Integration of parallel processing circuits forfuture multimedia and telecommunication systems andimage processing (Academy project Nr. 45796, 1999-2002, 40 pmo in 2002)

From these projects, the total research work withinTelectronics project area exceeded 650 pmo (annually 12-14 person-years), and made the project three times largerthan expected. Furthermore, the supplementary financinggiven by HUT: research by staff members, administration,rents and design/testing laboratory costs etc. sum up to50% of project salary costs or 100 pmo.

The projects of TEKES were more industriallyoriented, but they had a central role in achieving closecontacts with industry necessary for understanding thepractical problems and challenges in the field. Theresearch team could be made much larger than expected.The Telectronics research could be focused on deepeningthe understanding of the subject area and for writing thedoctoral dissertations of the senior team members at alate phase of their doctoral studies.

Co-operation in Finland and abroad

In all sub-projects, there were several co-operatingpartners in Finland and abroad. Some of them are listedhere:

Finland: Industrial enterprises: Nokia Research

Center (NRC), Nokia Mobile Phones (NMP), NokiaNetworks (NN), Electrobit Inc., MicroAnalog Systems(MAS) Inc., Ylinen Electronics Inc. (Objectives 1 and 2)

University of Turku, objective 3 International co-operation:Chalmers University of Technology, Sweden, Prof.

Herbert Zirath, Processing of 60GHz PHEMT chips, jointseminars (Objective 2)

Hungarian Academy of Science, design and testing of CNN circuits, Prof. T. Roska, (Objektive 3)

University of Frankfurt, CNN Image Processing, prof.Tezlaff, (Objektive 3)

Caltech/Jet Propulsion Laboratory, Millimeter-waveintgegrated circuits design, Prof. Sandy Weinreb, postdocexchange, Pekka Kangaslahti at JPL 1999-2001

(Planned visiting professorship of Prof. J. Choma fromthe University of Southern California had to be cancelledbecause of personal reasons of Dr. Choma)

Postgraduate student exchange: Universities ofWarsaw, Cracow and Granada

II. SUMMARY OF RESEARCH RESULTS

a) Adaptive RF, analogue and mixed analogue anddigital integrated circuit design for wirelesscommunication systems

The main research topics in this sub-project weredesign of tunable RF and analogue circuit blocks: low-noise amplifiers, oscillators, mixers etc., and fast high-resolution A/D and D/A converters, and mixed analogue-digital direct digital synthesizer (DDS) circuits forflexible and programmable wideband modulation andnon-linearity error correction. The research subjects of the individual researchers were:

R. Kaunisto: Monolithic Active Filters for 2-5 GHz.Doctoral thesis examined in Nov 2000.

K. Stadius: Active RF-filters, Enhancement of VCOtuning range. Harmonic varactorless VCOs for GHz-Range Applications diodes. Design of a double-tuner fora cable modem (2001). Doctoral thesis will be examinedsoon.

E. Tiiliharju: Integrated analogue filters. Multichip RFdesign using flip-chip techniques between active andpassive chips, as an example ‘An Image-RejectDownconverter with Sideband Selection for Double-Conversion Receivers’. Measurement techniques for IQ-mixer imperfections. Doctoral thesis to be examined in2003.

Jouko Vankka 2001, (postdoc) A book on integratedDirect Digital Synthesizer design published in 2001.Direct digital synthesis applied to an integrated analogueand digital multicarrier GMSK modulator design for basestations. Doctoral thesis examined in 2000 (not withinTelectronics-program)

Jarkko Jussila, Mikko Waltari 2001, Direct conversion

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receiver circuit design for WCDMA Fast D/A and A/Dconversion, D/A error correction. Self-calibrated pipelineADC with 200MHz IF-sampling frontend . M. Waltari’sdoctoral thesis examined in June 2002. J. Jussila’s thesisto be examined in 2002-2003.

Olli Väänänen, 2001, Reducing the crest factor of CDMA downlink signal by adding unused channelizationcodes, effect of clipping in wideband CDMA system andalgorithms for peak windowing mixed A-D design

Jonne Lindeberg, 2001 , FIR filters for compensatingD/A converter frequency response distortion

b) Integrated 40-60 GHz circuit blocks for wirelessmultimedia systems

This project was started as doctoral thesis study ofPekka Kangaslahti on 40 GHz wave frequencymultiplication The thesis was examined in Aug 1999.Frequency multiplication is beneficial in millimetre wavesignal sources to obtain low phase noise. Furthermore,high efficiency frequency doublers reduce powerconsumption and need for additional amplification andtheir small area requirement enables integration of severaldoublers and other circuit functions on one MMIC -chip.Pekka Kangaslahti then continued as a postdoc teammanager. During 1999-2001 he has been an exchangepostdoc researcher (financing from HUT-IDC/ECDL)with prof. S. Weinreb at Caltech/JPL , and studying 70GHz monolithic integrated circuit design. The researchersat HUT have been first Jan Riska 1999-2000 , (Licentiatethesis and examination in 2000), and after him MikkoKärkkäinen. The financing for both of them was arrangedvia a supporting TEKES project LALAMO, but the workhas been supervised from Telectronics (Kangaslahti,Porra).

All costly RF circuits of a 60GHz front end except oneat the end of 2001were processed and tested as a part of LALAMO using test equipment of MILLILAB atVTT/HUT. The last chip will be processed as a part ofthe Telectronics-project. The circuits were processed in aGaAs 0,2..0,1 mm PHEMT Technology in co-operationwith prof H. Zirath, Chalmers University of Technology,Gothenburg, Sweden.

c) New nonlinear circuit applications: Cellularnonlinear networks, signal processing using chaosdynamics

Since 1990, the laboratory has developed novelintegrated CMOS implementations for cellular nonlinearnetworks (CNN, also called cellular neural networks dueto the similarity with Hopfield networks). These are denseanalog processors with only local connectivity betweenthe processing units. The processing is based on analognonlinear dynamics of the cells. It has been shown, thatthis architecture will allow highly parallel teraflop speed

real time processing of moving images to be applied insuch demanding applications as in writing pads of personal communicators. All largest and fastest CNNcircuits for black and white image processing, especiallyan 128 by 128 cell universal machine chip and an 176 by144 pixel video processor chip with teraflops speed, havebeen developed at HUT-ECDL. The doctoral thesis of AriPaasio was examined in January 1999.

The research of CNN circuits has led the laboratoryin close contact with an international network of researchgroups in the field of nonlinear system dynamics. Themajor partners in this network have been prof. Leon Chua,the originator of the idea of CNN from the University ofCalifornia, Berkeley, and prof. Tamas Roska fromHungarian Academy of Sc. Using the CNN principle as apart of a computer system, Professor Roska's group hasdeveloped a Universal CNN Machine, and a programminglanguage to write CNN applications. When equipped witha CNN chip this computer will reach teraflop speed.During fall term 2002, Prof. Chua will be a guestprofessor at HUT/ECDL.

Analogue integrated circuits of this size (about 1million transistors) have never earlier been made, andmany properties of circuits of such complexity(propagating offsets and disturbances, maximizing yield,minimizing power, adaptive dynamics etc) will need largeamount of basic and applied research. This will be thetopic of one doctoral thesis (Asko Kananen)

The studies of nonlinear dynamics of CNN's andrelated structures especially by Prof. Chua at UCB havelead to other application areas of nonlinear dynamics. Thechaotic behavior of nonlinear electronic circuits has beenshown to lead to spread-spectrum signal processingcapability which can be utilized in communicationsystems. ECDL has been a partner in a European UnionESPRIT long term research project (IT/LTR) INSPECT –Innovative Signal Processing using Chaos Theory. anddeveloped a 500 kb/s 2.4 GHz radio system based on Frequency-Modulated Differential Chaos Shift Keying(FM-DCSK). This is the first experimental ‘chaos radio’reported so far. The measured performance was verifiedto follow in multipath propagation conditions closely thetheoretical predictions. A prototype chaos oscillatorbased on CNN architecture (T. Huhtanen) was developedas a part of Telectronics-project.

III. IMPACTS

Because of the parallel industrially oriented projectsall ideas have been effectively adopted by Finnishindustrial enterprises, and the results have influenced theproduct design in industry. The extensive academic co-operation has led to a wide exchange of ideas for futureresearch. As an example, Prof. Leon Chua from UCBerkeley will supervise the doctoral students in the area

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of CNN research as a guest professor during the fall termof 2002.

REFERENCES

Only publications of each author during theTelectronics research year period are included.

Book:

[1] J. Vankka, " "Direct Digital Synthesizers: Theory,Design and Applications,"," Kluwer AcademicPublishers, Boston, 2001, 216 p.

Exceptional achievements: Papers presented at theInternational Solid-State Circuits Conference ISSCC in2001 and 2002

[2] Jussila, Ryynänen, Sumanen, Kivekäs,Pärssinen,Halonen, "A 22mA 3.7dB NF Direct ConversionReceiver for 3G WCDMA," International Solid-State Circuits Conference ISSCC'2001, February 5 -7, 2001, San Francisco, USA., pp. 284-285.

[3] Digest of Technical Papers, Vankka, J., Pyykönen,J., Sommarek, J., Honkanen, M., Halonen, K., "AMulticarrier GMSK Modulator for Base Station",ISSCC'01, February 5 - 7, 2001, San Francisco,USA, pp. 354-355.

[4] M. Waltari ,L. Sumanen, T. Korhonen, K. Halonen,"Self-Calibrated Pipeline ADC with 200MHz IF-Sampling Frontend", accepted in International Solid-State Circuits Conference ISSCC'2002, SanFrancisco, Feb. 2002.

[5] J. Vankka, J. Ketola, O. Väänänen, J. Sommarek, M.Kosunen, and Kari Halonen, "AGSM/EDGE/WCDMA Modulator with On-ChipD/A Converter for Base Station," accepted toISSCC'2002.

Refereed articles in international journals:1998:

[6] Kangaslahti, P., Alinikula, P., Porra, V., "MillimetreWave Signal Generation Using Monolithic HEMT Technologies", Analog Integrated Circuits andSignal Processing, Special Issue: Selected Articlesfrom the 1996 NORCHIP Seminar, January 1998,Vol. 15 no. 1, pp. 123-134.

[7] Kaunisto, R., Stadius, K., Porra, V., "Active MMICFilters with Negative Resistance Compensation",Electronics Letters, 11th June 1998, Vol. 34 no. 12,pp. 1236-1237.

1999:

[8] Paasio, A., Dawidziuk, A., "CNN TemplateRobustness with Different Output Nonlinearities",International Journal of Circuit Theory andApplications, January-February 1999, Vol. 27, No.1, pp. 87-102.

[9] Paasio, A., Kananen, A., Halonen, K., Porra, V., "AQCIF Resolution Binary I/O CNN-UM Chip",Journal of VLSI Signal Processing, November-December 1999, Vol. 23, No. 2/3, pp. 281-290.

2000:

[10] Tanskanen, J.M., Kangaslahti, P.; Ahtola, H.;Jukkala, P.; Karttaavi, T.; Lahdes, M.; Varis, J.;Tuovinen, J. "Cryogenic indium-phosphide HEMTlow-noise amplifiers at V-band", Microwave Theoryand Techniques, IEEE Transactions on , Volume: 48 Issue: 7 Part: 2 , July 2000, pp. 1283 - 1286

[11] Kangaslahti, P., Alinikula, P., Porra, V."Miniaturized Artificial Transmission LineMonolithic Millimeter Wave Frequency Doubler",IEEE Trans. Microwave Theory Tech, vol. 48, April2000. pp. 510-518.

2001:

[12] Waltari, M., Halonen, K., "1-V, 9-Bit PipelinedSwitched-Opamp ADC", IEEE Journal of Solid-State Circuits, vol. 36, pp. 129-134, Jan. 2001.

[13] Tuovinen, J.,Kangaslahti, P., Haapanen, P., Hughes,N., Jukkala, P., Karttaavi, T., Koistinen, O., Lahdes,M., Salminen, H., Tanskanen, J. and Urpo, S., "Development of 70 GHz Receivers for the PlanckLFI", Astrophysics Letters and Communications, vol37, 2000., pp. 181-187.

[14] Paasio, A., Halonen, K., "A New Cell OutputNonlinearity for Dense Cellular Nonlinear NetworkIntegration", IEEE Transactions on Circuits andSystems-I: Fundamental Theory and Applications,March 2001, vol. 48, No. 3, pp. 272-280.

[15] J. Vankka, M. Honkanen, and K. Halonen "AMulticarrier GMSK Modulator", IEEE Journal onSelected Areas in Communications: WirelessCommunications Series, Vol. 19, No. 6, pp. 1070-1079, June 2001.

[16] J. Vankka, J. Pyykönen, J. Sommarek, M.Honkanen, and Kari Halonen, "A Multicarrier

34


GMSK Modulator for Base Station," accepted to IEEE Journal of Solid-State Circuits, 2001.

Papers submitted in 2001 to International Journals:

[17] M. Kosunen, J. Vankka, M. Waltari, and K.Halonen, "A Multicarrier QAM Modulator forWCDMA Basestation with on-chip D/A converter,"submitted to IEEE Transactions on Very Large ScaleIntegration Systems.

[18] J. Vankka, J. Ketola, O. Väänänen, J. Sommarek, M.Kosunen, and Kari Halonen, "AGSM/EDGE/WCDMA Modulator with On-ChipD/A Converter for Base Station," submitted to IEEEJournal of Solid-State Circuits.

[19] M. Waltari, K. Halonen, "Bootstrapped switchwithout bulk effect in standard CMOS technology"submitted to IEE Electronics Letters. 2001

[20] A.Kananen, A.Paasio, M.Laiho, K.Halonen, 'APractical Approach to Mixed-Mode ParallelProcessors: Hardware Partitioning and Realizations',submitted to International Journal of Circuit Theoryand Applications.

[21] M.Laiho, A.Paasio, A.Kananen, K.Halonen, 'APolynomial Type CNN with Mixed-Mode Approachfor Analyzing EEG', submitted to InternationalJournal of Circuit Theory and Applications.

International conference papers:1998:

[22] Paasio, A., Kananen, A., Porra, V., "CellularNonlinear Network Implementation for PacketSelection", Proceedings of the 5th IEEE International Workshop on Cellular NeuralNetworks and their Applications, 14-17 April 1998,London, Great Britain, pp.156-161.

[23] Kangaslahti, P.,Hughes,N. J.,Salminen,H., Jukkala,P., Porra, V., Ylinen J., "Millimetre Wave SignalGeneration Components Using MMIC and MIC Technology", Proceedings ESA workshop onMillimeter Wave Technology and Applications, 27-29 May 1998, Millilab, Espoo, Finland. pp. 490-495.

[24] Kananen, A., Paasio, A., Lindfors, S., Halonen, K., "A Cellular Nonlinear Network for Digital ErrorCorrection", Proceedings of the IEEE InternationalSymposium on Circuits and Systems, 31 May - 3June 1998, Monterey, USA, pp. III 255-259.

[25] Kaunisto R., Stadius, K., Porra, V., "A 3 GHz Silicon-BJT Active Resonator and Filter",Proceedings of the 5th IEEE InternationalConference on Electronics, Circuits and Systems, 7-10 September 1998, Lisbon, Portugal, pp.3/197-200.

[26] Stadius, K., Kaunisto, R., Porra, V., "A HighFrequency Harmonic VCO with an ArtificialVaractor", Proceedings of the 5th IEEE InternationalConference on Electronics, Circuits and Systems, 7-10 September 1998, Lisbon, Portugal, pp.3/161-164.

[27] Paasio, A., Kananen, A., Halonen, K., Porra, V., "A48 by 48 CNN Chip Operating with B/W Images",Proceedings of the 5th IEEE InternationalConference on Electronics, Circuits and Systems, 7-10 September 1998, Lisbon, Portugal, pp.191-194.(invited)

[28] Kangaslahti, P., Kalajo, S, Porra, V., Jukkala, P.,"Unlimited Bandwidth TWT Predistortion LineariserMMICs for Ku and Ka-band Operation",Proceedings of the GAAS'98 Conference, 5-6October 1998, Amsterdam, The Netherlands. pp. 85-88.

[29] Stadius, K., Holmberg, J., Kaunisto, R., Alinikula,P., Porra, V."A Monolithic TemperatureCompensated 1.6 GHz VCO", Proceedings of theGAAS'98 Conference, 5-6 October 1998,Amsterdam, The Netherlands. pp. 626-630. Also inProc. European Microwave Conference 1998 vol 1.pp 217-221.

[30] Stadius, K., Kaunisto, R., Porra, V., "MillerCapacitance Tuning for Voltage-ControlledOscillators and Active Filters at Radio Frequencies",Proceedings of the Baltic Electronic Conference1998, 7-9 October 1998, Tallinn, Estonia, pp. 215-218.

1999:

[31] Porra, V., Halonen, K., "Integrated circuits for futurewireless communication terminals," ,Proc. 10thMICROCOLL, Budapest, March 21-24,1999,pp.197-202 (invited)

[32] Paasio, A., Kananen, A., Porra, V., "A 176 x 144processor binary I/O CNN-UM chip design",European Conference on Circuit Theory and DesignECCTD'99, Design Automation Day proceedings(ECCTD'99-DAD), August 29 - September 2, 1999,Stresa, Italy, pp. 82-86. (invited)

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[33] Stadius, K., Kaunisto, R., Porra, V., "Si BJTNegative-Conductance Circuit Topologies for GHz-Range Applications", Proceedings of the EuropeanConference on Circuit Theory and DesignECCTD'99, August 29 - September 2, 1999, Stresa,Italy, pp. 301-304.

[34] Kananen, A., Paasio, A., Halonen, K., "ErrorCorrection for Flash A/D-converters Using CellularNonlinear Network", Proceedings of the EuropeanConference on Circuit Theory and DesignECCTD'99, August 29 - September 2, 1999, Stresa,Italy, pp. 936-939.

[35] Paasio, A., Kananen, A., Halonen, K., Porra, V., "Different Approaches for CNN VLSIImplementations", Proceedings of the EuropeanConference on Circuit Theory and DesignECCTD'99, August 29 - September 2, 1999, Stresa,Italy, pp. 1347-1350.

[36] Stadius, K., Kaunisto, R., Porra, V., "VaractorDiodeless Harmonic VCOs for GHz-RangeApplications", Proceedings of the 1999 IEEEInternational Conference on Electronics, Circuitsand Systems, September 5-8, 1999, Pafos, Cyprus,Vol. I, pp. 505-508.

[37] Riska, J., Kangaslahti, P., Kärkkäinen, M., Porra,V.,"60GHz PHEMT MMIC's For Broad-BandWireless Front End", Proceedings of the 10th IEEconference on microwave technique, October 12-13,1999, Prague, pp. 159-163.

[38] Paasio, A., Kananen, A., Halonen, K., Porra, V., "CNN Hardware for QCIF Video Segmentation",Proceedings of the International Symposium onNonlinear Theory and its Applications, November28 - December 2, 1999, Waikoloa, Hawaii, USA, pp. 419-421. (invited)

2000:

[39] Paasio, A., Halonen, K. "Cellular Nonlinear NetworkImplementation for Nonlinear B-Template", Proc.6th IEEE International Workshop on Cellular NeuralNetworks and their Applications, May 23 - May 25,2000, Catania, Italy.

[40] Paasio, A., Paakkulainen, J., Isoaho, J. "A CompactDigital CNN Array for Video SegmentationSystem", Proc. 6th IEEE International Workshop onCellular Neural Networks and their Applications,May 23 - May 25, 2000, Catania, Italy

[41] Laiho, M., , Paasio, A., Halonen, K. "Structure of aCNN Cell with Linear and Second Order PolynomialFeedback Terms", Proc. 6th IEEE InternationalWorkshop on Cellular Neural Networks and theirApplications, May 23 - May 25, 2000, Catania, Italy.

[42] Kananen, A., , Paasio, A., Halonen, K. "Overlappingissues in designing large CNNs", Proc. 6th IEEEInternational Workshop on Cellular NeuralNetworks and their Applications, May 23 - May 25,2000, Catania, Italy.

[43] Paasio, A., Paakkulainen, J., Isoaho, J. "AMultiplier-Free Fixed-Task Digital CNN Array forVideo Segmentation System", Proc. 2000 IEEEInternational Symposium on Circuits and Systems,May 28 - May 31, 2000, Geneva, Switzerland.

[44] Laiho, M., Paasio, A., Halonen, K. "Building Blocksfor Large Annealed Compact Neural Networks",IEEE International Symposium on Circuits andSystems, May 28 - May 31, 2000, Geneva,Switzerland.

[45] Kangaslahti, P., Riska, J., Kärkkäinen, M., Alinikula, P., Porra, V. "Low Phase Noise SignalGeneration Circuits for 60GHz Wireless BroadbandSystem", Proc. IEEE Intntnl MicrowaveSymposium, 11.-16. June, 2000, Boston, MA, USA.pp. 43-46.

[46] Porra, V., Azzinnari, L., Krol, K., Korpela, E. andTalonen, M. "Demodulation and Bit-synchronizationUnit for FM-DCSK Chaos Radio" Proc. BalticElectronic Conference BEC 2000, October 8 - 11,2000, Tallinn, Estonia pp. 187-190.

[47] Riska, J., Kärkkäinen, M., Kangaslahti, P., Porra, V."Amplifiers And Signal Generation Circuits for60GHz Wireless Broadband System", EuropeanMicrowave Conference, October 2000, Paris,France. EUMC_P3

[48] Poikonen, J., Paasio, A., Halonen, K., "BuildingBlocks for High Performance Digital to AnalogConverters", Proc. NORCHIP'00, November 2000,Turku, Finland.

2001:

[49] Stadius, Paatsila, Järviö, Halonen: An Image-RejectDownconverter with Sideband Selection for Double-Conversion Receiver, Proc. 27th European Solid-State Circuits Conference 2001, pp. 60-63

36


[50] Stadius, Järviö, Halonen: A Novel BJT Output Stagefor SAW Drivers, Proc. IEEE InternationalConference on Electronics, Circuits and Systems2001, vol-I, pp. 329-332

[51] Stadius, Järviö, Halonen: A Novel Feedback Schemefor Voltage-Followers, Proc. European Conferenceon Circuit Theory and Design 2001, vol-I, pp. 145-148

[52] Krol, K., Azzinnari, L., Korpeal, E., Mozsary, A.,Talonen, M., Porra, V.," An Experimental FM-DCSK Chaos Radio System," ," Proc. EuropeanConference on Circuit Theory and Design, Espoo28-31 Aug 2001, vol-III, pp. 17-20

[53] Azzinnari, L., Mozsary, A.,Krol, K., Porra, V, "ASimple Digital FPGA Pseudo-Chaos Generator,"Proc. European Conference on Circuit Theory andDesign, Espoo 28-31 Aug 2001, vol-III, pp. 25-28

[54] Stadius, Järviö, Paatsila, Halonen: Image-RejectReceivers with Image-Selection Functionality, Proc.IEEE International Symposium on Circuits andSystems 2001, vol-IV pp. 124-127

[55] M. Waltari, J. Pirkkalaniemi, L. Sumanen, M. Kosunen, K. Halonen, "A 14-bit, 40-MS/s DAC withCurrent Mode Deglitcher" Proc. NORCHIP'01,Stockholm, Nov. 2001.

[56] J. Vankka, J. Pyykönen, J. Sommarek, M.Honkanen, and Kari Halonen, "A MulticarrierGMSK Modulator for Base Station," ISSCC Digestof Technical Papers, February 5 - 7, 2001, SanFrancisco, USA, pp. 284-285.

[57] M. Kosunen, J. Vankka, M. Waltari, and K.Halonen, "A Multicarrier QAM Modulator forWCDMA Basestation with on-chip D/A converter,"Proceedings of CICC 2001 Conference, May 6-92001, San Diego, USA, pp. 301-304.

[58] Olli Väänänen, Jouko Vankka, Timo Viero and KariHalonen, "Reducing the Crest Factor of CDMADownlink Signal by Adding Unused ChannelizationCodes', IEEE International Conference on Communications, 2002.

[59] Olli Väänänen, Jouko Vankka and Kari Halonen,"Effect of Clipping in Wideband CDMA System andSimple Algorithm for PeakWindowing',International Conference on ThirdGeneration Wireless and Beyond, 2002.

[60] Jonne Lindeberg, Jouko Vankka and Kari Halonen,"FIR Filters for Compensating D/A ConverterFrequency Response Distortion," accepted toNorchip 2001.

[61] Jouko Vankka, Jonne Lindeberg and Kari Halonen,"FIR Filters for Compensating D/A ConverterFrequency Response Distortion," submitted toISCAS2002.

[62] M. Laiho, A. Paasio, A. Kananen, K. Halonen,'Discrete Time Analog Polynomial Type CNN withDigital State', IEEE International Symposium onCircuits and Systems, Sydney, pp. III-497-500,2001.

[63] M. Laiho, A. Paasio, A. Kananen, K. Halonen,'Effects of Partitioning in a Mixed-Mode CNN',European Conference on Circuit Theory and Design,Espoo, III-277-280, 2001.

[64] M. Laiho, A. Paasio, A. Kananen, K. Halonen,'Border Connection Schemes in Partitioned Mixed-Mode CNNs', European Conference on CircuitTheory and Design, Espoo, III-265-268, 2001.

[65] A. Paasio, A. Kananen, M. Laiho, K. Halonen, 'ACompact Computational Core for ImageProcessing', European Conference on Circuit Theoryand Design, Espoo, I-337- 339, 2001.

[66] A. Paasio, M. Laiho, A. Kananen, K. Halonen,'Different Implementation Approaches for Analogueand Mixed-Signal Array Processing', to be publishedin proceedings of U.R.S.I. Kleinheubacher Tagung,Band 45, Kleinheubach, Germany, 2001.

[67] A.Paasio, K.Halonen, 'An analogue circuit forweighted rank order filtering', European Conferenceon Circuit Theory and Design, Espoo, I-125-128,2001.

[68] A.Paasio, A.Kananen, L.Koskinen, K.Halonen,'Different possibilities for realizing the bipolar imageprocessing tasks in CNN field', EuropeanConference on Circuit Theory and Design, Espoo, I-101-104, 2001.

[69] A.Kananen, A.Paasio, K.Halonen, 'An ImprovedCurrent Mirror Based Approach for Linear SpatialFiltering', European Conference on Circuit Theoryand Design, Espoo, I-137-140, 2001.

[70] V.M.Brea, A.Paasio, D.L.Vilarino, D.Cabello, 'A DTCNN CMOS Implementation of a Pixel-Level

37


Snake Algorithm', European Conference on CircuitTheory and Design, Espoo, II-269-272, 2001.

[71] A.Paasio, A.Kananen, K.Halonen, V.Porra, 'A 48 x48 CNN chip for B/W image processing', ed.T.Roska and A.Rodriguez-Vazquez, in 'Towards theVisual Microprocessor: VLSI Design and the Use of Cellular Neural Network Universal Machines',John Wiley & Sons; ISBN: 0471956066, 2001.

[72] A.Paasio, K.Halonen, 'A New Cell OutputNonlinearity for Dense Cellular Nonlinear NetworkIntegration', IEEE Transactions on Circuits andSystems (CAS-I), vol.48, No.3, pp.272-280, 2001.

[73] M.Laiho, A.Paasio, A.Kananen, K.Halonen, 'SystemLevel Design Aspects of a Mixed-Mode ArrayProcessor', submitted to 2002 Southwest Symposiumon Mixed-Signal Design.

[74] L.Koskinen, A.Paasio, A.Kananen, K.Halonen, 'AMPEG-4 Shape Segmentation CNN Algorithm',European Conference on Circuit Theory and Design,Espoo, vol. III pp.73-76, 2001.

[75] L.Koskinen, A.Paasio, A.Kananen, K.Halonen,'MPEG-4 Encoder Architecture for a ShapeSegmentation CNN Chip', Proceedings of Workshopand Exhibition on MPEG_4, San Jose, pp. 41-44,2001.

Papers in National Conferences and Workshops

[76] Olli Väänänen, Jouko Vankka and Kari Halonen,"Effect of clipping in Wideband CDMA system',URSI XXVI Convention on Radio Science, FinnishWireless Communications Workshop, 2001.

[77] Jonne Lindeberg, Jouko Vankka and Kari Halonen,"FIR Filters for Compensating D/A ConverterFrequency Response Distortion,"URSI XXVI Convention on Radio Science, Finnish WirelessCommunications Workshop, 2001.

Patents:

[78] T. Vierro, M. Kiiski, O. Väänänen and J. Vankka,"Menetelmä Signaalin Rajoittamiseksi ja Lähetin",Patent Application 2010718FI, 2001.

Doctor's theses

[79] Paasio, A., "Integration of Cellular NonlinearNetwork Universal Machine", Doctor's Thesis,Helsinki University of Technology, January 8, 1999,p. 118.

[80] Kangaslahti, P., "Nonlinear Circuits for FrequencyMultiplication and Power Amplifier Linearisation",Doctor's Thesis, Helsinki University of Technology,August 23, 1999, p. 30.

[81] Kaunisto, R., "Monolithic Active Resonator Filtersfor High Frequencies", Doctor's Thesis, HelsinkiUniversity of Technology, November 17, 2000, p.125.

[82] M. Waltari, “ Circuit Design Techniques for LowVoltage and High Speed Analogue to DigitalConversion” Doctor's Thesis of fast A/D converters,Helsinki University of Technology , 24 June, 2002,in print

Lic. Tech theses:

[83] Riska, J.," Monolithic Integrated Circuits ForBroadband Telecommunication Millimeter-WaveRadio Front End"Licentiates Thesis, HelsinkiUniversity of Technology, September 12, 2000, p.61. (Supervised by Pekka Kangaslahti fromTelectronics-project)

[84] Kosunen, M.," A Multicarrier Quadrature AmplitudeModulator for a Wideband Code Division MultipleAccess Basestation", Licentiate's Thesis, HelsinkiUniversity of Technology, January 23, 2001, p. 90.

[85] Jussila, J.," Analog Baseband Signal Processing inWide-Band Direct Conversion Receivers",Licentiate's thesis, Helsinki University ofTechnology, March 27, 2001, p. 56.

[84] M. Laiho, 'Alternatives for Realizing an IntegratedPolynomial Type CNN', Licentiate's Thesis,Electronic Circuit Design Laboratory, Helsinki,2001.

Master's theses:

[85] Kananen, A., "Error correction for flash analog-to-digital converter using cellular nonlinear network",Master's Thesis (in Finnish), Helsinki University ofTechnology, 14th December 1998, p. 52.

[86] Laiho, M., "Integration of a Compact NeuralNetwork Optimozer for a CDMA Detector",Master's Thesis, Helsinki University of Technology,November 1, 1999, p. 57.

[87] Huhtanen, T.,"Integrated controllable chaos sourcebased on cellular neural network architecture",

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Master's Thesis, Helsinki University of Technology,February 22, 2000, p. 79.

[88] Kärkkäinen, M.,"Integrated Preamplifier for a Millimeterwave Receiver", Master's Thesis (inFinnish), Helsinki University of Technology, April26, 2000, p. 57.

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Techniques for the Third Generation of Wireless Systems

Jukka Saarinen, Jarmo Takala, and Jarkko NiittylahtiInstitute of Digital and Computer Systems, Tampere University of Technology

P.O.Box 553, 33101 [email protected], [email protected], [email protected]

Markku Renfors, Nikolay TchamovInstitute of Communication Engineering, Tampere University of Technology

P.O.Box 553, 33101 [email protected], [email protected]

Tapio SaramäkiInstitute of Signal Processing, Tampere University of Technology

P.O.Box 553, 33101 [email protected]

Visa KoivunenSignal Processing Laboratory, Helsinki University of Technology

P.O.Box 3000, 02015 [email protected]

ABSTRACT

Recently the most popular techniques used to exploit the limited bandwidth of the radio channel as efficiently as possible have been TDMA and CDMA methods. Alsothe popularity of multicarrier techniques has increased. Inthis project, several important topics in the design cycle ofa third generation’s receiver design have been addresseincluding multicarrier modulation techniques, adaptiveand blind equatlization methods, structures for digitalASIC, and RF-ASIC implementations.

I. INTRODUCTION

Throughout the history, there has been interest toexploit the limited bandwidth of the radio channel to beused as efficiently as possible. Several principaltechniques have been used to achieve this goal and latelythe popular techniques have been both TDMA andCDMA techniques, as well as multicarrier techniques(OFDM). The role of digital signal processing (DSP) is increasing and there have been great challenges indeveloping efficient implementations. Since the DSP partis becoming more and more complicated, advanced designtools and methodologies have an important role in makingthe design task manageable. Another important factor inwireless systems is the analog design of the highfrequency front-ends.

Successful design of wireless systems requires carefulselection of algorithms, architectures, implementationstyles, and technologies. In this project, several importanttopics in the design cycle of a third generation’s receiverdesign have been addressed. The contents of the projecthad two main subjects: a) algorithmic developments for

broadband wireless systems and b) hardwareimplementations for broadband wireless systems. Theobjective was to develop new algorithms and hardwareimplementations for the third generation of wirelesssystems.

II. MULTICARRIER MODULATION

TECHNIQUES

In this task, simple multicarrier CDMA scheme fordown-link was developed. The scheme is based ondifferential modulation with favourable performancecompared to direct sequence CDMA [13] [14] . In orderto design efficient filter banks for the multicarrier scheme,new design methods were developed. Further more designtools supporting the design method were developed.

During the project, also new fundamental results oncomplex modulated critically sampled filter banks wereobtained [15] [16] [17] . These results have enabled in-depth understanding of filter banks in channelequalization tasks. Based on this knowledge, efficientschemes for channel equalisation in filter bank basedsystems and for complex modulated critically sampledfilter banks were developed.

III. ADAPTIVE AND BLIND EQUALIZATION

METHODS

Conventionally, equalization is seen as an inverse-filtering task. Here however, we have consideredequalization as a classification problem. The idea is tomap the received signal into desired binary values bypartitioning the signal space into some decision regions.For this purpose, we have studied multilayer perceptron(MLP) neural network equalizers, clustering algorithms

41


and decision trees for equalization in a GSM-typeenvironment, where data is transmitted as bursts.

Conventional MLP networks obtained very good biterror rates (BER) in our simulations, but they also neededa lot of computation compared to traditional equalizationtechniques, such as Viterbi and decision-feedbackequalizer. To address this problem, we have usedmaximum covariance weight initialization technique,which speeds up the convergence and thus less training isneeded. Also the use of cascade-correlation learningmethod decreases the amount of computation needed.There, we start with a network, which has no hidden units(corresponds to a linear equalizer), and then add hiddenunits to it one by one, if needed. This way, the networkhas a suitable size for each received data burst andunnecessary computation can be avoided. By combiningthe weight initialization method and cascade-correlationlearning, and by applying RPROP-algorithm for training,we can achieve a significant improvement compared to aconventional MLP network trained with BP-algorithm.Competitive bit error rates compared to Viterbiequalization have been achieved.

The studied clustering algorithm and decision-treetechniques carry out the classification using similar idea,but they are implemented in a different way. Theclustering method finds cluster centers from the knowntraining sequence in the signal space and classifies thereceived data sequence to the binary values represented bythe nearest center. The decision-tree partitions the signalspace by placing axis-parallel decision boundaries andthereby separates the clusters formed by the set of training examples. Both methods are computationally very light,even though their BERs were not as good as obtained withViterbi or MLP networks.

In this research, also blind communication receiverstructures were derived. Blind receivers do not requiretraining sequences or pilot signals in mitigating intersymbol interference (ISI) caused by multipathpropagation. Consequently, information symbols can betransmitted instead and improved effective data rates andspectral efficiency is achieved. In this task, single-inputsingle-output (SISO) and single-input multiple-outputreceivers were developed. In particular blind equalizersbased on cyclostationary statistics of communicationsignals and prediction error filtering were derived andtheir performance analyzed analytically as well as insimulation studies [15] [19] [20] .

Least-square lattice algorithm was derived for blindequalization based on prediction error filtering. This typeof Lattice filtering algorithm lends itself to efficientimplementation because of its modular nature. Theoreticalresults on the performance of the proposed methods werederived in a form of a performance bound. We alsoshowed that most channel coding methods fulfil therequirement of uncorrelatedness of the sequence for blindequalization purposes. The validity of the concept was

shown in realistic simulations.

IV. STRUCTURES FOR DIGITAL ASIC

In this task, low-power arithmetic structures based onresidual number systems were developed [21] [22] [23][24] . These units are carry-free structures based on modulo arithmetic. The results also include new advancedalgorithms and area-efficient architectures for numericalcontrolled oscillators and especially the results includenew record in lookup table compression ratio in NCOs[25] .

In this task, also two levels of interconnections forASIC implementations were considered, local interconnections within computational resources andglobal interconnections between different computationalunits. The local interconnections were studied withemphasis on array processors, where data-dependencies ofoperations require input data to be reordered between theintermediate computational stages. In this project, low-latency interconnection structures have been developed,which can realize special class of reorderings, stridepermutations. Such a reorderings are present in severalimportant algorithms, e.g., in discrete trigonometrictransforms and Viterbi decoding. A generalfactorialization of stride permutation matrix has beendeveloped [26] [27] . The resulting decompositioncontains sparse matrices, which can be mapped ontosimple shift-exchange structures containing only registersand multiplexers. The developed method is general, i.e.,reordering networks can be designed for sequence sizes ofpowers of two and the permutation can be performed overnumber of ports, which is also any power of two.

The developed reordering networks can be used todevelop scaleable array processors, e.g., for fast Fouriertransform, discrete cosine and sine transforms, and Viterbidecoding, where the number of processing elements canbe selected during the design-time independent on theproblem size. This approach has been demonstrated in[28] especially with constant geometry discrete cosinetransform algorithm [29] .

Global interconnectios were studied with emphasis onblock transfers between coarse grain computationalresources. As the complexities of ASICs increases there isneed to develop design methods to create globalinterconnections between heterogeneous resources. Forthis purpose a parameterisable interface for bus basedsystems is developed [29] [31] [32] . The interface to theactual communication bus contains a low-level, low-overhead protocol, which allows multiple masters to sharethe communication medium. The communication unitcontains another interface to computational resourse butthis interface is parametrisable, thus several different unitscan easily be connected to a shared bus with the aid of theparametrisable interconnection unit.

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V. RF-ASIC IMPLEMENTATIONS

In this task, monolithic CMOS/BiCMOS voltagecontrolled oscillator (VCO) designs satisfying thedemanding phase-noise specifications of mobilecommunication systems were developed[33] . Theobtained results have been extended to frequency bandsutilized in Bluetooth and WLAN applications[34] .

VI. RESULTS AND IMPACTS

The main results of the project have been published ininternational conferences and scientific journals. Theimpacts of the research include citations and invitedpapers and presentations. Several professionals withexpertise in the field have been produced, i.e., the projecthas produced five D.Sc. dissertations [1-5] and sevengraduate degrees [6-12]. The project has created newinternational collaboration, e.g., with Univ. CA, Berkeley;IMEC; Delft Univ. Tech., etc.

The research performed in this project has been carried out in collaboration with other research projectsand the developed technology has been transferred toindustry through collaboration. Close co-operation hasbeen with the following projects: VDSL modem designbased on filter banks in the TEKES-TLX project ”Fast DSL technologies in broadband transmission”, filter bankbased narrowband interference cancellation approach forCDMA and VCO design developed in the TEKES-ETXproject ”Digital and Analog Techniques for FlexibleRadio”, “RF-ASIC” project with Bell Labs, developmentof array processing architectures in the TEKES-ETXproject ”System Design in Electronics”, andMultiprocessor systems for baseband processing in theTekes-ETX project ”Intelligent and configurablemultimedia systems”.

The basic studies on filter bank based modulationtechniques in wireless communications continue in theAcademy of Finland funded project “AdvancedMulticarrier Techniques for Wireless Communications”.Application oriented studies on this topic, as well as onMC-CDMA techniques are carried out in the project“Beyond 3G Multidimensional Air Interface” in the TekesNETS program.

REFERENCES

[1] J. Mannerkoski, Adaptive Blind Equalization Basedon Second-Order Statistics and MultichannelPrediction, D.Sc. Thesis, Tampere University of Technology Publications 260, Tampere University of Technology, Tampere, Finland, 1999.

[2] J. Takala, Real-Time Signal Processing Systems:Parallel Algorithms and Architectures, D.Sc. Thesis,Tampere University of Technology Publications 262, Tampere University of Technology, Tampere,Finland, 1999.

[3] P. Kolinummi, Hardware Implementation andApplications of Scalable Parallel Computer, D.Sc.Thesis, Tampere University of TechnologyPublications 294, Tampere University ofTechnology, Tampere, Finland, 2000.

[4] M. Kuulusa, DSP Processor Core-Based WirelessSystem Design, D.Sc. Thesis, Tampere University ofTechnology Publications 296, Tampere University of Technology, Tampere, Finland, 2000.

[5] K. Kuusilinna, Studies and Implementations of Bus-based Interconnections, D.Sc. Thesis, TampereUniversity of Technology Publications 320, TampereUniversity of Technology, Tampere, Finland, 2001.

[6] J. Mannerkoski, Adaptive Blind Equalization Basedon Second-Order Statistics and MultichannelPrediction, Lic.Sc. Thesis, Tampere University ofTechnology, 1998.

[7] Y. Yang, Implementation of Perfect ReconstructionCosine Modulated Filter Banks Using Digital Signal Processor, M.Sc. Thesis, Tampere University of Technology, 2001.

[8] T. H. Stitz, Filter Bank Based Interference Detectionand Suppression in Wideband Spread SpectrumSystems, M.Sc. Thesis, Tampere University ofTechnology, 2001.

[9] J. Alhava, Channel Equalization in Filter Bank-Based Multicarrier Systems, M.Sc. Thesis, TampereUniversity of Technology, 2000.

[10] T. Ihalainen, High Speed Diode-Bridge Track-and-Hold Amplifiers, M.Sc. Thesis, Tampere Universityof Technology, 2001.

[11] T. Hjelm, RF Low-Noise Amplifiers, M.Sc. Thesis,Tampere University of Technology, 2001.

[12] T. Haverinen, Channel Equalization UsingClassification Methods, M.Sc. Thesis, TampereUniversity of Technology, 2000.

[13] T. H. Stitz and M. Renfors, “Filter Bank BasedNarrowband Interference Detection and Suppressionin Spread Spectrum Systems,” in Proc. IEEE Intl. Symp. Circuits and Systems, Phoenix, AZ, U.S.A.,May 26-29, 2002.

[14] H. Xing and M. Renfors, “The Performance Analysisof a Multi-Carrier CDMA System in MobileEnvironment,” submitted to European T.Telecommunications.

[15] J. Alhava and M. Renfors, “Adaptive Sine-Modulated/Cosine-Modulated Filter Bank Equalizerfor Transmultiplexers,” in Proc. EuropeanConference on Circuit Theory and Design, Espoo,Finland, August 2001.

[16] A. Viholainen, T. H. Stitz, J. Alhava, T. Ihalainen,and M. Renfors, “Complex Modulated CriticallySampled Filter Banks Based on Cosine and SineModulation,” in Proc. IEEE Intl. Symp. Circuits andSystems, Phoenix, AZ, U.S.A., May 26-29, 2002.

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[17] J. Rinne, “Some Elementary Suboptimal DiversityReception Schemes for DVB-T in MobileConditions,” IEEE T. Consumer Electronics, vol. 46,pp. 847-850, Oct. 2000.

[18] J. Mannerkoski, V. Koivunen, and D. Taylor,“Performance Bounds for Multi-Step PredictionBased Blind Equalization,” IEEE T. Communication,pp.84-93, Jan. 2001.

[19] J. Mannerkoski and V. Koivunen “AutocorrelationProperties of Channel Encoded Sequences -Applicability to Blind Equalization,” IEEE T. SignalProcessing, pp. 3501-3507, Dec. 2000.

[20] J. Mannerkoski and D. Taylor, “Blind EqualizationUsing Least-Squares Lattice Prediction,” IEEE T.Signal Processing, vol. 47, no. 3, pp. 630-640,March 1999.

[21] F. Curticapean, K. Palomäki, and J. Niittylahti, “ADirect Digital Frequency Synthesizer with a HighMemory Compression Ratio,” accepted to ElectronicLetters, 2001.

[22] F. Curticapean and J. Niittylahti, “Complex DigitalOscillator with Absolute Periodicity,” in Proc. XEuropean Signal Processing Conference, 5-8September, 2000, Tampere, Finland.

[23] F. Curticapean and J. Niittylahti, “Low-Power DirectDigital Frequency Synthesizer,” in Proc. 43rd IEEEMidwest Symp. Circuits and Systems, Lansing, MI,USA, Aug. 9-11 2000.

[24] F. Curticapean and J. Niittylahti, “A HardwareEfficient Direct Digital Frequency Synthesizer,” inProc. ICECS 2001, 2-5 Sept. 2001, Malta.

[25] F. Curticapean, K. Palomäki, and J. Niittylahti, “AMemory Efficient Direct Digital FrequencySynthesizer,” in Proc. 3rd Int. Conf. on Information,Communications, and Signal Processing, Singapore,15-18 Oct. 2001.

[26] J. Takala, D. Akopian, J. Astola, and J. Saarinen,“Scalable Interconnection Networks for PartialColumn Array Processor Architectures,” in Proc.IEEE Int. Symp. Circuits and Systems, Geneva,Switzerland, May 28 - 31, 2000, vol. IV, pp. 513-516.

[27] J. Takala, T. Järvinen, P. Salmela, and D. Akopian,“Multi-Port Interconnection Networks for Radix-RAlgorithms,” in Proc. IEEE Intl. Conf. Acoust.,Speech, Signal Process., Salt Lake City, UT, U.S.A.,May 7-11, 2001, vol. II, pp. 1177-1180.

[28] J. Nikara, J. Takala, D. Akopian, and J. Saarinen,“Pipeline Architecture for DCT/IDCT,” in Proc.IEEE Intl. Symp. Circuits and Systems, Sydney,Australia, May 6-9, 2001, vol. IV, pp. 902-905.

[29] J. Takala, D. Akopian, J. Astola, and J. Saarinen,“Constant Geometry Algorithm for Discrete CosineTransform,” IEEE T. Signal Process., vol. 48, no. 6,pp. 1840-1843, June 2000.

[30] K. Kuusilinna, P. Liimatainen, T. Hämäläinen, and J.Saarinen, ”Reconfiguration for an IP Block BasedInterconnection”, in Proc. Euromicro Workshop on Digital System Design: Architectures, Methods and Tools, Milan, Italy, Sep 8-10, 1999, pp. 42-45.

[31] V. Lahtinen, K. Kuusilinna, T. Hämäläinen, T.Kangas, and J. Saarinen, “Reusable Interface inMultimedia Hardware Environment,” in Proc. 10thEuropean Signal Processing Conference, Tampere,Finland, Sep 5 - 8, 2000, pp. 2301-2304.

[32] K. Kuusilinna, V. Lahtinen, T. Hämäläinen, and J.Saarinen, “Finite State Machine Encoding for VHDLSynthesis,” IEE Proceedings - Computers and Digital Techniques, vol. 148, no.1, 2001, pp. 23-30.

[33] P. Väänänen, M. Metsänvirta and N. T. Tchamov,“A 3.6 GHz Double Cross-Coupled MultivibratorVCO with 1.6 GHz Tuning,” IEEE T. Circuits and Systems, Part I, vol.48, pp. 799-802, August 2001.

[34] P. Väänänen, M. Metsänvirta, and N. T. Tchamov,“A 4.3-GHz VCO with 2-GHz Tuning Range andLow Phase Noise,” IEEE Journal of Solid-StateCircuits, Vol.36, No.1, Jan 2001, pp.142-146.

44


Fractal processes in telecommunications

Ilkka Norros

VTT Information TechnologyP.O. Box 1202, 02044 VTT

[email protected]

ABSTRACT

Stochastic processes with fractal paths have been encountered in telecommunication research in severalcontexts during the 1990’s. Some mathematical problemsrelated to them were studied in this project.

I. INTRODUCTION

The project “Fractal processes in telecommunications”was set up in order to develop mathematics needed toworking with traffic processes with a fractal character. Itsobjectives were to achieve internationally recognisedresults on some of the following areas: stochastic analysisof fractal processes, multifractal analysis, fractional Levyprocesses, fractal aspects of very large networks, andstatistics of fractal processes,. The educational aims wereto create expertise and to produce two PhD theses onthese topics. The project resulted in considerabledevelopment of expertise, manifested in several journalpapers, and in the extension of international researchcontacts, including real collaboration with joint papers.The two theses are underway and expected to be finishedwithin the year 2002.

II. OVERVIEW OF THE RESULTS

a) Queueing theoryThe project produced two kinds of results in queueing

theory. Both grew out from earlier work done at VTT on a queue where the input process is a fractional Brownianmotion (fBm). The fBm is a zero-mean Gaussian processwith stationary increments such that the variance of anincrement on an interval of length t is t2H , where H is anumber between 0 and 1. The usual Brownian motion isobtained as the case H=1/2. When H>1/2, the incrementsof the process are equally dependent at all timescales – afeature that was observed to be typical for data traffic andprompted the study of new kinds of traffic models.

The paper [3] analyses a queue (storage), where theinput is Gaussian but the variance is a power onlyasymptotically as t grows to infinity. It is shown that,under mild conditions, the large deviations of the queueare similar to those of the queue fed by an fBm.

Papers [1] and [2] have a more applied character,generalising techniques learnt in the fBm context togeneral Gaussian input processes with stationaryincrements. The papers show how reasonably accurateestimates of the queue length distribution can be obtainedwith a straightforward method that also yields the mostprobable paths along which the rare events happen. Figure1 shows an example of such a path.

Figure 1 – The most probable path of the input rate process thatproduces a queue of size 1, when the input process is a superposition of a fractional Brownian motion and a periodicBrownian bridge, and the service rate is 1.

b) Stochastic analysis of Fractional Brownian motionSeveral other types of problems related to the fBm

were also studied in the project. Paper [8] obtains the fBmas a limit process of a special type of binary trees. Theclassical binary trees have the geometric Brownianmotion as the limit process. The practical motivation ofthese problems comes from mathematical finance.

Papers [5], [6] and [7] investigate general analyticalproperties of the fBm. Paper [5] develops an originalapproach to integration with respect to a fBm. In the paper

45


[7], maximal inequalities valid for Brownian motion areshown to hold for fBm, whereas in the paper [6] it isshown that the classical Ito isometry of Brownian motionis not valid for fBm even as an inequality.

c) Multifractal analysisThe analysis of data traffic traffic at small timescales

has revealed that the traffic processes are inherentlymultiscale objects with strong rescaling properties.Roughly speaking, this means that the process path hasfractal-like burstiness at each timepoint but the localfractal scaling may be different from point to point. Themathematical analysis of truely multifractal measures is ahighly sophisticated mathematical discipline. Ourcontribution, paper [4], introduces a stationarymultifractal measure that is constructed by multiplyingindependent copies of one simple “mother process” sothat the time run faster and faster for each copy. Withfinitely many factors one obtains realisations thatresemble measured data traffic quite a lot, whereas thelimit process is a true multifractal whose existenceconditions and basic properties are found in the paper.

Figure 2 – An example of a realisation of a product of sevensimilar but time-scaled two-state Markov processes.

III. RESULTS AND IMPACTS

The project gave a strong impact to the study of fractalstochastic processes in Finland, in particular as regardstopics arising from applications. The project also invitedseveral foreign visitors with whom many of the articleswere written, and organised an international symposiumin May 1999.

REFERENCES

[1] Addie, R.G., Mannersalo, P., and Norros, I., 1999,“Performance formulae for queues with Gaussianinput”, ITC 16, Edinburgh, UK.

[2] Addie, R.G., Mannersalo, P., and Norros, I., 2002,“Most probable paths and performance formulae forbuffers with Gaussian input traffic”, EuropeanTransactions on Telecommunications, Vol. 13.

[3] Kozachenko, Yu., Sottinen, T., and Vasyluk, O., “Path space large deviations of a large buffer withGaussian traffic”, submitted to Queueing Systems.

[4] Mannersalo, P., Norros, I., and Riedi, R.,“Multifractal products of stochastic processes:construction and some basic properties”, submittedto Advances in Applied Probability.

[5] Mishura, Y. and Valkeila, E., 2000, “An isometricapproach to generalized stochastic integrals”, Journalof Theoretical Probability, Vol. 13, pp. 673-693.

[6] Memin, J., Mishura, Y., and Valkeila, E., 2001,“Inequalities for the moments of Wiener integralswith respect to a fractional Brownian motion”,Statistics & Probability Letters, Vol. 51, pp. 197-206.

[7] Novikov, A. and Valkeila, E., 1999, “On somemaximal inequalities for fractional Brownianmotions”, Statistics & Probability Letters, Vol. 44,pp. 47-54.

[8] Sottinen, T., 2001, “Fractional Brownian motion,random walks, and binary market models”, Financeand Stochastics, Vol. 5, pp. 343-355.

46


Distributed Media Processing in Hybrid Networks

Matti Pietikäinen

University of OuluDepartment of Electrical Engineering

[email protected]

ABSTRACT

This research was concerned with processing and refining of multimedia information in hybrid networkenvironments. The transmission and consumption ofbandwidth intensive media objects were considered andservice presentation techniques were developed for low-to-high bandwidth scalable service units, such asintelligent wireless terminals. Experimental validation ofthe solutions was done in complete end-to-end systemsdeveloped in projects funded by the National TechnologyAgency (Tekes) and industry.

I. INTRODUCTION

Different types of media are growing in importance intelecommunication network service techniques. Thevalue-added services offered on the top of networkinfrastructure(s) are one of the main focus of theteleoperators functions in the future, e.g. video,documents, and mixed media conferencing. The networktypes or elements are connected using interfacetechniques and different handover/switching mechanisms.Using so called hybrid architecture, having many differentconnected network elements in delivering service totelecommunications access and content consumers, placehigh requirements for media provider and deliverythrough the network used.

This joint research project, carried out by groups fromthe University of Oulu, University of Maryland (USA)and National Institute of Standards and Technology -NIST (USA), contributed to the areas of mediaprocessing, transmission and distribution in varyingnetwork elements and end terminals.

In Oulu, the project was aimed to strengthen the basicresearch component of our emerging research program on distributed multimedia. An important goal was also tostrengthen the collaboration with our American researchpartners.

The responsible reader of the research in Oulu was Prof.Matti Pietikäinen and the activities within and betweenthis project and related Tekes funded projects werecoordinated by Prof. Jaakko Sauvola and Dr. Timo Ojala.

The leaders of the research in US groups were Dr. DavidDoermann (U. of Maryland) and Dr. Omid Kia (NIST).

The total funding obtained for the research from theTelectronics programme was 1 375 000 FIM. The USpartners funded their research from their own sources.The project was carried out during the period 1.6.1998-31.12.2001.

II. TOPICS OF RESEARCH

This research was concerned with processing andrefining of multimedia information in hybrid networkenvironments. The transmission and consumption ofbandwidth intensive media objects were considered andservice presentation techniques were developed for low-to-high bandwidth scalable service units, such asintelligent wireless terminals. The main challengecentered around analyzing the media and identifyingunderlying physical and semantic characteristics that canbe utilized in optimizing the service and networkperformance. The type of network, load, usabilitycharacteristics and application processing profiles incomplex human-terminal-network service environmentswere targeted. The hybrid network elements offer thebasic control for media domain preparation and affect thefinal object package delivered through distributedprocessing units. The user terminal dictates the controlparameter profiles for media preparation and transmissionthat is used to interpret and optimize the media profilecharacteristics in transmission/consumption events. Experimental validation of the solutions was done incomplete end-to-end systems developed in projectsfunded by the National Technology Agency (Tekes) andindustry. The most closely related Tekes projects led byProf. Sauvola and Dr. Ojala, and carried out in parallelwith this Telectronics project, were:• Princess - Mobile Media Adaptation• CTI - Computer Telephony Integration• Duchess - Wireless Media Telephony Services in

Office Environment

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Descriptions of the results obtained in the Academyfunded project and related Tekes projects are presented inreferences [1-15].

A part of the project funding was also used to supportour research on media analysis methods dealing withdocument images and videos, see e.g. [16]. This created basis for a deeper understanding of the mediacharacteristics related to this project.

III. RESULTS AND IMPACTS

The research produced new scientific results with highindustrial relevance.

In mobile multimedia adaptation, a new multimediacontent model was introduced. An architecture calledPrincess was developed for providing mobile services in ahybrid network environment. Some pilot services, likenews, video surveillance and sports events, wereimplemented and demonstrated to verify the usefulness of the developed approach.

In distributed computing, a mobile agent platform withbuilt-in security capabilities was developed. Among itsadvantages are dynamic distribution and load management, and service scalability. The DistributedAgent Network (DAN) architecture was developed,providing interconnectivity of a hybrid network andservice structure. Implemented pilot systems includeInternet Video Call Center and Internet Shopping Center.

In media telephony area, frameworks for buildingH.323 and SIP compliant client applications with richmultimedia content were developed. The pilotapplications included multimedia conferencing andremote application control.

The results of research were reported in over 20 refereed scientific publications. About 30 articles aimedfor general public and popularization of science appearedin newspapers and in business/professional magazines.The industrial partners participating in the related Tekesprojects were informed about the progress of research bytechnical reports, workshops and experimental pilots.

The results of research are being exploited in R&Dprojects and commercial products of industrial partners. Asuccessful spin-off company (Icecom) was established bysome students participating in this research.

The research also promoted the development of a newresearch group at the University of Oulu, MediaTeamOulu (http://www.mediateam.oulu.fi), and promotedcareers of its young directors (J. Sauvola, T. Ojala). Theresearch has also promoted new research projects in thisarea in Oulu. The key members of this project played keyroles in the founding of Mobile Forum(http://www.mobileforum.org).

REFERENCES

[1] Kia O & Sauvola J (1998) Active multimediadocuments for mobile services. Proc. 2nd IEEEWorkshop on Multimedia Signal Processing, LosAngeles, CA, 227-232.

[2] Kia O, Schaff A & Sauvola J (1998) Datarepresentation and handling for large imagebrowsing. Proc. SPIE Vol. 3527, MultimediaStorage and Archiving Systems III, Boston, MA, 37-46.

[3] Metso M, Koivisto A & Sauvola J (1998)Multimedia adaptation for dynamic environments.Proc. 2nd IEEE Workshop on Multimedia SignalProcessing, Los Angeles, CA, 203-208.

[4] Kia O, Sauvola J & Doermann D (1999) Network-diffused media scaling for multimedia contentservices. Proc. 6th International Workshop on Interactive Distributed Multimedia Systems andTelecommunication Services, Tolouse, France, 149-162.

[5] Metso M, Koivisto A & Sauvola J (1999) Contentmodel for mobile adaptation of multimediainformation. Proc. 3rd IEEE Workshop on Multimedia Signal Processing, Copenhagen,Denmark, 39-44.

[6] Sauvola J & Kia O (1999) Distributed processing of multimedia extended documents. Proc. 3rd IEEEInternational Conference on Multimedia SignalProcessing, Copenhagen, Denmark, 623-628.

[7] Koivisto A, Pietikäinen P, Sauvola J & Doermann D(2000) Live multimedia adaptation through wirelesshybrid networks. Proc. IEEE InternationalConference on Multimedia and Expo 2000, NewYork City, NY, 3:1697-1700.

[8] Metso M & Sauvola J (2001) The media wrapper inthe adaptation of multimedia content for mobileenvironments. Proc. SPIE Vol. 4209, MultimediaSystems and Applications III, Boston, MA, 132-139.

[9] Metso M, Koivisto A & Sauvola J (2001) Contentmodel for mobile adaptation of multimediainformation. Journal of VLSI Signal Processing29:115-128.

[10] Metso M, Löytynoja M, Korva J, Määttä P &Sauvola J (2001) Mobile multimedia services - content adaptation. 3rd International Conference onInformation, Communications and SignalProcessing, Singapore. (CD-ROM)

[11] Kaukonen S (1999) Distributed computing incomputer telephone integration. M.Sc. thesis,Department of Electrical Engineering, University of Oulu, Finland (in Finnish).

[12] Kaukonen S, Sauvola J & Ojala T (1999) Agent-based conferencing using mobile IP-telephony. Proc.3rd IEEE International Workshop on MultimediaSignal Processing, Copenhagen, Denmark, 593-598.

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[13] Tienari H, Kaukonen S & Sauvola J (2001) Usingmobile code to improve distribution performance inslow wireless environments. Proc. 9th InternationalConference on Advanced Computing andCommunications, Bhubaneswar, India, 191-198.

[14] Keskinarkaus A, Ohtonen T & Sauvola J (1999)Beethoven architecture for media telephony. Proc.SPIE Vol. 3842, Internet II: Quality of Service andFuture Directions, Boston, MA, 276-284.

[15] Keskinarkaus A, Korhonen J, Ohtonen T,Kilpelänaho V, Koskinen E & Sauvola J (2001)Comparing architectural solutions of IPT applicationSDKs utilizing H.323 and SIP. Proc. SPIE Vol.4522, Voice over IP (VoIP) Technology, Denver,CO, 13-24.

[16] Okun O, Doermann D & Pietikäinen M (2001) Pagesegmentation and zone classification: a brief analysisof algorithms. Proc. International NAISO Congresson Information Science Innovations (ISI'2001) - Workshop on Document Image Analysis andUnderstanding, March 17-21, Dubai, U.A.E., 98-104.

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Computational Methods for the Performance Analysis of Broadband

Communication Networks -- Com2

Jorma Virtamo

Helsinki University of Technology, Networking Laboratory P.O. Box 3000, 02015 HUT, Finland

[email protected]

ABSTRACT

In the Com2 project traffic related problems emerging

in broadband multiservice networks and the Internet were

studied. Several new results were obtained and algorithms

developed. Notably the results include an algorithm for

calculating blocking probabilities in multicast networks,

an analysis of the performance of the RED buffer

management mechanism, and a novel application of

importance sampling technique for very efficient variance

reduction in Monte Carlo simulations. Further, optimal

link control of multibitrate networks was studied and an

efficient approximation method developed for the

problem. Optimal marking mechanism for congestion

pricing in the Internet was developed. In traffic modelling,

a new way of estimating the Hurst parameter of self-

similar traffic was presented and implemented. A program

library of developed algorithms is being maintained.

I. INTRODUCTION

The goal of the project was to develop mathematical and computational methods for the performance analysis of broadband multiservice networks, and, in particular, the Internet. Such methods are needed to provide the basic tools for developing appropriate dimensioning methods and traffic and congestion management mechanisms for the networks.

The topics were broadly divided into three areas: 1) queueing models, 2) simulation methods, and 3) traffic models. All three areas were addressed in the project.

In the area of queueing models, four different problems were studied. First, a queue management mechanism, called RED, was modelled and analysed. The model, consisting of a set of coupled ordinary differential equations, captures the most important features of the system and allows us to analyse the stability conditions of the system. This kind of analysis gives guidelines for setting the parameter values of the RED controller. Second, multicast networks were studied and new algorithms were developed for calculating the blocking probabilities of end users of such a system. Third, optimal

link control of multibitrate systems were analysed within the framework of Markov decision processes. This problem appears as a sub-problem in optimal routing of connections in the network. A new approach for the problem was proposed and successfully solved. Fourth, optimal marking of packets in the congestion pricing scheme was studied. Use of expected shadow prices for marking was suggested, and these expected shadow prices were explicitly worked out for some model systems.

In the area of simulation methods, the work focused on developing efficient speed-up methods for the Monte Carlo simulation of blocking probabilities of multibitrate systems. A series of progressively better methods were proposed. The ultimate result was a new importance sampling based method, which in an advantageous way combines analytical results and the actual simulation. Sample generation in this method is done applying so-called inverse convolution. The performance of this method is far better than that of the previously known methods.

The traffic in the Internet is long-range dependent. A popular model for this kind of traffic is fractional Brownian motion, proposed by I. Norros. The estimation of the three parameters of the model on the basis of measured traffic, however, is not trivial. In particular, the estimation of the Hurst parameter, describing the scaling behaviour of the traffic, may require a very large number of sample points if done in a straight forward way. In this work the use of geometric sampling grid, along with Maximum likelihood method, was suggested and the method was fully developed. The advantages of the method were demonstrated; it yields as good or better results than the wavelet based estimation method. As spin-off of this work a new method for generating 2-dimensional fractional Brownian motion was developed.

In parallel with the Com2 project, some other projects have been carried out in the teletraffic group of the Networking Laboratory. In particular, COST257 project, funded by Tekes and the industry, dealt with partly the same problems, and in some cases it is difficult to tell exactly which result is due to which project. An attempt, however, is made to give correct indication of this.

51


II. ANALYSIS OF AN ACTIVE QUEUE

MANAGEMENT MECHANISM RED

Random early detection or RED [1] is a widely

accepted mechanism for the buffer management in

Internet routers. It works by randomly dropping packets

even before the buffer is full, thus spreading out the

phases of sources that use the TCP protocol and breaking

up their tendency to synchronize themselves. Dropping is

done with a probability that depends on the current value

of the so-called exponentially weighted average queue

length.

TCP sources are controlled by their internal flow

control mechanism. Packet loss acts as an implicit signal

of existing congestion, causing the sources to back off, i.e.

to reduce their sending rate.

The TCP source population and a RED controlled

queue constitute a closed loop control system whose

dynamics is analysed in a series of papers, [2]-[6]. Our

central modelling assumption is that the system can be

described in terms of the expected values of the random

variables. This amounts to saying that variances of the

variables are unimportant in comparison to the dynamic

behaviour of the expected values. This assumption can be

justified when the time constant of the averaging is long,

as is the case in practice.

In its full-blown form [5], our model comprises three

coupled, retarded ordinary differential equations for the

expectations for the instantaneous queue length, the

averaged queue length and the aggregate packet rate of

the source population. Retardation here means that the

propagation delays of the packets in the network are taken

into account. The dynamics of the system as described by

these equations is found to agree reasonably well with

results obtained by simulations.

A slightly simplified model is used in [6] to analyse

the stability of the system. Three intrinsic parameters

(denoted a0, a1, and a2) determine the stability region of

the system, as depicted in Figure 1.

-15 -10 -5 0 5 10 15 20a0

0

2

4

6

8

10

a1

STABLE

Figure 1 – A cross section of the stability region (constant a2).

The intrinsic parameters depend in a complex way on

the physical parameters. By inverting this mapping, the

stability region of the physical parameters can be

unfolded. An example is given in Figure 2. This kind of

analysis sheds light on the notoriously difficult problem of

setting the parameter values for the RED mechanism.

20 40 60 80 100 120 140Tmax

0.5

1

1.5

2

2.5

3

Tmin

pmax=1

pmax=0.7

pmax=0.4

pmax=0.2

STABLE

Figure 2 – Stability region in the physical parameter space.

III. MULTICAST SYSTEMS

Multicasting means a mode of transmission where

certain flow on information is sent simultaneously to a

group of recipients (also called users). Instead of sending

the same stream separately to each recipient, in

multicasting a multicast tree is formed, having the origin

of the information as the root and the recipients as leaves.

The root sends only one stream, which is then copied to

each direction at a branching point of the tree. Since in

each branch only a single copy of the stream is being

carried, multicast transmission has a bandwidth saving

nature.

In a more general case, the root sends several

multicast transmissions, called channels (c.f. TV program)

and for each channel there exists a separate multicast tree.

In a dynamic setting the users may join and leave any of

the trees as they wish. Sometimes a request of a user to

join a tree may be blocked because some of the links

along the branch that has to be created may not have

sufficient resources for the new stream. The problem

addressed in our work is how to calculate the probability

of blocking for a user request in such a setting. Prior to

our work this problem was largely unexplored.

The problem was solved piece by piece in a series of

papers. In [7] and [8], the single link problem is studied

and reduced to so-called generalized Engset system (the

single link problem means that there is only one

bottleneck link, all the other links having, in effect,

infinite capacities). The blocking problem in a network

was first solved in [9], which resulted from the COST257

project. The algorithm developed, is an extension of the

known convolution-truncation algorithm for tree-like

access networks. The novel feature is that in the multicast

52


application the ordinary convolution operation has to be

replaced by a new construct, so-called OR-convolution.

The convolution-truncation algorithm remarkably reduces

the complexity of computing the blocking probabilities,

rendering the problem essentially independent of the

network size (as opposed to an exponential growth of the

complexity in a more direct approach).

The computational load remains heavy when the

number of channels grows (to more than, say, 10

channels). Assuming that the channels can be divided into

groups of statistically identical channels, the algorithm

can be further simplified by defining a combinatorial

convolution operation [10], [11], which can be used to

efficiently solve even systems with large number of

channels.

The work is further extended to cases where each

multicast stream uses layered coding (i.e., higher bit rates

for better quality, and lower rates for lower quality) in

[12] and [13]. The importance sampling simulation

methods developed in the project (see Chapter V) are

applied to the multicast problem in [14] and [15]. A

related problem of the signalling load for multicast group

management is studied in [16].

In summary, the work carried out in the Com2 project

has considerably advanced the state of the art of

calculating the basic performance characteristics of

multicast networks.

IV. RESOURCE ALLOCATION

a) Optimal link control in multiservice network Optimal routing based on the theory of Markov

Decision Processes (MDP) is a well-studied area in

traditional telephone networks. Assuming the links to be

independent, routing decisions can be made based on

optimal control of the resources of a separate links [17].

In multiservice network carrying connections with

different bandwidth requirements, however, even the

single link control problem becomes difficult. An exact

analysis is not feasible due to the huge size of the state

space.

An approximate approach was presented in [18]. The

idea was to describe the system in terms of an aggregate

process (describing the total usage of link capacity) and

approximate this by a Markov process. In our work [19],

[20], the idea is not to approximate the actual process

(multidimensional Markov process) but approximate the

so-called relative cost of states as a function in the state

space. Experiments with different sets of base functions

were done, e.g. piecewise polynomial (linear, quadratic,

cubic) functions with or without cross-terms. The

approach in [18] can be viewed in this framework as an

approximation of the cost function by piecewise constant

base functions.

The parameters of the approximate functions, i.e.

coefficients of the base functions, were determined by a

least squares procedure, i.e. by maximizing the degree the

exact equations are satisfied, leading to so-called normal

equations. Efficient recursive algorithms were developed

to calculate the matrix elements between different base

functions. The results obtained with our method compare

very favourably with the published results of other

researchers. In particular, piecewise linear approximation

worked well. Despite of the efficiency of the developed

algorithms, the problem, however, remains hard for large

systems.

b) Congestion pricing The congestion pricing scheme proposed by Gibbens

and Kelly [21] has appealing simplicity. It is based on the

idea that rational Internet users maximize the difference of

their own utility and the cost of network usage, and their

behaviour can be affected by economical incentives. More

precisely, rational users accept that their terminal devices

run algorithms that do this maximization on their behalf.

Basically, the users are allowed to send traffic to the

network as they wish, but provided that the network gives

appropriate feedback to them, the system as a whole will

tend towards a state where the total welfare is maximized.

A crucial question here is what is the correct feedback

information. It turns out that the so-called shadow price of

the resource usage is what should be signalled to the users

(e.g. in the form of marked packets). For an unbuffered

system the shadow price can easily be worked out. In case

of a buffered system, the problem is that the shadow price

is not known at the moment a packet leaves the buffer.

Some suggestions to overcome this difficulty have been

made, such as the use of a virtual queue or time reversal.

The idea in our work [22] is to mark each packet with

the expected shadow price, which turns out to be the same

as the probability that after the departure of the packet the

buffer overflows before becoming empty. This quantity is

closely related to the so-called relative costs of states

studied in the theory of Markov Decision Processes

(MDP) and can be calculated for an M/M/1/K queue with

the tools provided by the theory. An alternative derivation

for the expected shadow price is also given.

Our analysis gives the best marking strategy given the

available information. Unfortunately, the results depend

on the modelling assumptions of the queue. As a more

robust approach, also approximation of the queue by a

diffusion process is studied. This approach calls for on-

line estimation of the diffusion parameters. As only two

parameters are involved, the task should not be too

difficult.

V. SIMULATION METHODS

Exact calculation of end-to-end blocking probabilities

in a network is in general a difficult problem. The

difficulty is even more pronounced when the traffic is

composed of different traffic classes, distinguished by

53


attributes such as the bandwidth. In principle, it is easy to

write down the expression for the blocking probability: it

is the ratio of two sums. The problem is the overwhelming

size of the sums. There are a few approximation methods,

e.g. the reduced load method, that allow computation to

some accuracy. The accuracy, however, is out of the users

control.

Monte Carlo (MC) method, based on sampling the

terms, suits well to the estimation of the kind of sums

appearing here and was adopted in our work. But even

MC method is inefficient when very small blocking

probabilities are to be estimated. The problem addressed

in our work is how the efficiency of the MC method can

be improved by variance reduction methods, and, in

particular, by the importance sampling (IS). In importance

sampling, the more interesting samples are made more

probable, and this is compensated for in the statistics

collection by giving them a smaller weight.

A series of progressively more efficient methods was

developed in [23]-[28] and [14]. The method of

conditional means, combined with sample generation by

Gibbs sampling, was successfully applied (in COST257

project) in [23] and [24]. Importance sampling was first

applied in [25], where the existing sample biasing

methods was significantly improved by using composite

distributions.

The main achievements are represented by the method

described in [26]-[28]. The new method by far

outperforms all the previously known methods in variance

reduction. Two key components in our method are

decomposition and inverse convolution. The method

combines in a serendipitous way the power of analytical

approach with actual simulations; the simulation starts

where the theory leaves us.

Roughly speaking, decomposition means that we

break down the end-to-end blocking problem into a set of

independent single link blocking problems as depicted in

Figure 3. In cases where several links block

simultaneously, there is some ambiguity in determining

which link the blocking should be attributed to. With a

consistent convention, however, we make this assignment

unambiguous.

x1

x2 �

2

�2

�1

�3

�3

�1

Figure 3 – Decomposition of blocking problem.

Inverse convolution is the crucial element in our

method. It is based on the observation that the steps in

calculating the distribution of the sum of independent

random variables can be reversed in such a way that each

component, one by one, can be drawn a value on the

condition that their sum has a given value. This method

allows one to directly generate sample points of the

blocking states for a system where just a single link has

finite capacity and all others are have an infinite capacity

(with some precomputed tables the generation of the

samples is very fast). With this device at hand, the MC

simulation of the interesting probability (the probability of

the set of actual blocking states of the single link problem)

becomes very efficient; for each generated sample one

just records whether it is an actual blocking state or not.

Speed-up factors in the range 103-105 were obtained.

A comparison of the efficiency of the method with other

methods is shown in Figure 4 (the Gaussian method is

another variant of out method, which the space does not

allow to describe in detail here). The inverse convolution

method is best suited for high-accuracy calculations,

where a large number of samples need to be generated;

otherwise the overhead of preparations needed to generate

the tables may not be justified.

A fast C code implementation [29] of the method is

freely available from the web:

http://keskus.hut.fi/tutkimus/com2/netwsim/index.shtml.

00.10.20.30.40.50.60.70.80.91

Case 1

Convolution

Gaussian

Composite

Single tw ist

Ross

MC

00.10.20.30.40.50.60.70.80.91

Case 2

Figure 4 – Comparison of variance reduction techniques (the lower the bar the better).

54


VI. TRAFFIC MODELING

a) Estimation of the parameters of FBM model Traffic in the Internet has been found to exhibit long-

range dependent behaviour. Roughly speaking this means

that the traffic fluctuates on all time scales, a fact that has

some implications with regard to how efficiently different

congestion management methods may work. In order to

study these, it is necessary to develop traffic models that

capture long-range dependence. The fractional Brownian

motion (fBm), suggested by Norros [30] as such a model,

has increasingly gained popularity in recent years. The

advantages of the model are its parsimony - the model is

completely determined by three parameters - and its

basically simple mathematical properties - fBm traffic is

self-similar (which, however, leads to many challenging

problems).

One of the three parameters is the Hurst parameter, H,

which describes the scaling behaviour of the traffic, i.e.

how fast the covariance function decreases. It turns out

that the estimation of the three parameters on the basis of

traffic measurements is not trivial. In particular, the

estimation of H is difficult. With a naive approach even

modest estimation accuracy requires a very large number

of sampling points.

In [31]-[33] we present a new approach to the

estimation problem. The idea in the method is to use a

geometric sampling grid (sampling intervals increase in

geometrical progression) instead of an evenly spaced grid.

Intuitively, the aim is to sample the traffic at different

time scales with few sample points and to avoid collecting

redundant information. Also the self-similar nature of the

grid seems to fit nicely with that of the traffic model.

Indeed, the covariance matrix of the traffic over the

geometric grid has a simple structure.

In this setting, we apply the well-established method

of maximum likelihood estimation (MLE). This method

calls for the inversion of the covariance matrix, which is a

major difficulty in the method. For small number of points

this can be done by direct numerical inversion. For larger

number of points, to obtain a higher accuracy, we develop

various approximation methods.

The results show that the goal of reducing the number

of sampling points was indeed achieved. It turned out that

the method also outperforms the wavelet approach, which

is today very popular. Our method may, however, be more

sensitive to measurement accuracy at short time scales.

In the hindsight, it can be realized that in essence we

transformed the original process to another one by using

logarithmic time, and that this transformed process is

short-range dependent (to which we apply the standard

MLE method). This explains why the method works well.

b) Generation of 2-dimesional fractional Brownian

motion For many purposes, e.g. for simulations, it is desirable

to be able to generate sample paths from a given traffic

process. Norros et al. [34] presented a top-down approach

for generating sample paths from 1-dimensional fBm, a

variant of the so-called random midpoint displacement

method. The idea of this method is extended to a 2-

dimensional fBm process in [35] (most of the work was

done in COST257 project). A square is divided in 4-ary

fashion into ever-smaller sub-squares. The 2-dimensional

fBm process is generated by conditioning the value of the

process in each sub-square on the values of the process

already generated on the larger scale, i.e. on the

environment of the sub-square (the process starts at some

scale, where the number of sub-squares is small enough to

allow transforming the process into white noise process

by the square root of the covariance matrix). With a

sufficiently large environment, the generated process very

closely resembles a true 2-dimensional fBm.

c) Traffic measurements Though traffic measurements were not specifically on

the agenda of the project, some work in this field was also

carried out. In particular, traffic statistics of the modem

pool at the ingress of the HUT network were collected.

Samples of the results can be found at http://keskus.hut.fi/

tutkimus/com2/modempools/ modempools.shtml.

VII. RESULTS AND IMPACTS

In the project, a number of new teletraffic results were

obtained and related computational algorithms developed.

The goals set for the project were well achieved. As

mentioned in the Introduction, the methods provide basic

tools needed in dimensioning of the networks and

designing appropriate traffic and congestion control

methods.

Besides the direct scientific results, the project had a

crucial role in allowing the teletraffic group of the

Networking Laboratory to reach a critical size and to get

its operation on a stable basis. At the time of writing the

group consists of some 15 researchers, among them three

post docs.

From the educational perspective, the results were also

positive. One doctoral degree was obtained during the

project, and another doctoral thesis, largely based on the

work done in the project, is now in the pre-examination

phase. Further, a crucial part of the doctoral thesis of a

visiting researcher was done in the project. In addition,

two Master’s theses were completed.

A side result of the project was that a program library,

Qlib, of algorithms needed in queueing theory was

developed and maintained [36]. Initial work to create the

55


library had been done in an earlier project at VTT, but in

the course of the Com2 project several new algorithms

were developed, tested and added to the library. The

algorithms have been coded in Mathematica, but for many

algorithms also fast implementations in C were coded.

These can be called from the Mathematica by the

MathLink mechanism. The library is completely open:

http://keskus.hut.fi/tutkimus/com2/Qlib/index.shtml.

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57

TELECTRONICS II Research Programme Final Report.

FIT – Future Internet: Traffic Handling andPerformance Analysis

Jorma VirtamoNetworking Laboratory, HUT

P.O.Box 3000, 02015 HUT, [email protected]

Ilkka NorrosVTT Information Technology

P.O. Box 1202, 02044 VTT, [email protected]

ABSTRACT

The FIT project has addressed a number of problemsarising in controlling the traffic and providing quality ofservice in the Internet and in analyzing the performance ofthe system. An efficient recursive algorithm has been devel-oped for calculating the flow level performance of elastictraffic under a bandwidth sharing scheme called balancedfairness (BF). The notion of BF has been extended and ap-plied to the flow throughput estimation in ad hoc networks;also other applications of BF are being explored. Schedul-ing mechanisms, in general, and adaptive scheduling mech-anism with delay bounds, in particular, were studied. A sim-ple adaptive and distributed load balancing mechanism hasbeen suggested and analyzed. In this system, traffic is grad-ually redistributed based on measured link loads, leading toa nearly optimal performance. Analytical results have beenobtained on the performance of MAC protocols in ring net-works employing optical burst switching. For traffic matrixestimation, the Gravey-Vaton method has been analyzed indetail in the case of Gaussian traffic variations. The sta-bility problem of an overloaded network with measurement-based admission control has been analytically solved.

I. I NTRODUCTION

FIT is a joint project between the teletraffic theory groupof the Networking Laboratory of Helsinki University ofTechnology (HUT) and the VTT/UH (University of Hel-sinki) group. The site http://www.netlab.hut.fi/tutkimus/fit/provides general information about the project. The projectstarted in 2001 and continues to the end of 2004. For vari-ous reasons, the center of the gravity of the project at HUThas shifted towards the end of the project and at the time ofthis writing (March 2004) the project is still going on withfive researchers working full time. Therefore, this report isnot complete but more results will be produced.

At a general level, the objective of the project has beento study methods for traffic handling in the Internet in orderto avoid or manage congestion and methods for providingQuality of Service (QoS) and QoS differentiation and, fi-

nally, to develop methods for analyzing the performance ofsuch systems. The specific topics studied are detailed be-low.

Balanced Fairness (BF) discussed in Section II can, onone hand, be viewed as an ideal bandwidth sharing scheme.On the other hand, BF can be seen as a computational ap-proximation tool for analyzing more easily implementableschemes like max-min fairness. Scheduling, which is thetopic of Section III, is the key mechanism for QoS differen-tiation in the routers; packets belonging to different trafficclasses are handled differently. Load balancing is one of thebasic tasks of Traffic Engineering (TE) in a network. Sec-tion IV introduces a simple adaptive mechanism by whichan almost ideal load distribution is obtained without know-ing the traffic matrix. At the transport level, modern broad-band networks utilize optical technology, which poses dif-ferent type of traffic handling problems. In Section V, theperformance of MAC protocols in an optical ring networkusing optical burst switching is analyzed. Many traffic han-dling operations at the network level require knowledge ofcurrent traffic demands between different origin-destinationpairs. Estimating the traffic matrix on the basis of link loadmeasurements, however, is a strongly under determinedproblem and poses a big challenge. Results of a study re-lated to a recently introduced method are discussed in Sec-tion VI. Some traffic measurements have also been done inthe project as briefly documented in the next section. Sec-tion VII deals with another traffic handling method, mea-surement based admission control for networks subject tooverload. The analysis of a simple network model demon-strates how the lack of complete state information makes thestability of the system very sensitive to its parameters

II. B ALANCED FAIRNESS

In the Internet, the bandwidth resources of the networkare shared between all concurrent traffic flows. Typically,the sharing is determined by a flow control protocol suchas the TCP (Transmission Control Protocol), which is usedby the majority of applications. An objective of bandwidthsharing is some kind of fairness, but what fairness means

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when there are many resources (link capacities) shared byseveral flows with different routes is not obvious. Many def-initions have been developed, including the classical max-min fairness and proportional fairness. These are specialcases of a more general class of so-called utility based fair-ness criteria [1].

A new notion of fairness, called balanced fairness (BF),has recently been introduced by Bonald and Proutière [2]-[4]. The most important property of BF is that it leadsto completely insensitive network performance: the perfor-mance under BF depends solely on the traffic loads on dif-ferent routes but not of any other traffic characteristics (e.g.,flow size distribution). This is a very desirable propertyfrom the point of view of networks design and management.Another remarkable property of BF is that the performancein a real dynamic setting, where new flows arrive stochas-tically and depart upon completion, can be evaluated in ananalytic form for many important network topologies.

The analysis of a network performance under BalancedFairness is based on the theory of Whittle queueing net-works [5], i.e. networks of Processor Sharing (PS) nodesthe capacities of which,φi(x), depend on the global net-work statex in a “balanced way”. This condition meansthat there exists a balance functionΦ(x) such that

φi(x) =Φ(x − ei)

Φ(x)∀i, x, (1)

wherex−ei denotes the network state with one class-i cus-tomer less than in statex. Balanced Fairness refers to a ca-pacity allocation that satisfies the balance condition (1) andat the same time utilizes the network resources maximally.

An important contribution of the FIT project was the de-velopment of a recursive method for an exact calculation ofthe normalization constant of a BF system [6, 7] (from thenormalization constant all the performance metrics can beeasily derived). Notably, the algorithm completely avoidssolving the balance function explicitly. The recursion is alsovery efficient: in a system withn flow classes only2n num-bers have to be recursively calculated, in contrast to someNn numbers in a direct calculation, whereN typically, de-pending on the desired accuracy, is of the order of 100.

C1=16

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Figure 1: An example of a 4-level tree.

0.5 1 1.5 2 2.5 3load of class−10 flows

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Figure 2: Comparison of class-10 throughput lower and up-per bounds with the exact result. From bottom up: store-and-forward, parking lot, exact, deterministic.

The method has been applied to practically importanttopologies for access networks, like parking lot and generaltree with and without access rate limits. An implementa-tion of the recursion for a general tree network has beenadded to the Qlib library [8]. As an important side result itwas proven in [7] that BF is Pareto efficient in all tree net-works, i.e. no network resources are wasted by the balancecondition. Explicit results have been worked out for severalexample networks. In Figure 1 a four level tree network isillustrated and Figure 2 shows the flow throughput in thisnetwork for class-10 flows going through the links 10, 7, 3and 1.

As noted before, the distinguishing feature of BF is itsinsensitivity. In contrast, all utility based fairness schemesare sensitive except for some special network topologies,where they coincide with BF. Indeed, Bonald and Proutièrehave shown that in order for any queueing network of PSnodes to be insensitive the resource allocation has to be bal-anced. This result was extended to any network of symmet-ric queues in [9].

An extensive study of the sensitivity properties of vari-ous schemes was undertaken in [10]. The study confirmsthat the non-BF schemes are sensitive (their performancewas evaluated by simulations). The sensitivity on the flowsize distribution, however, is not very strong; more pro-nounced is the sensitivity with respect to so-called timescale changes. It was also found that, largely speaking,BF provides a reasonably good approximation for the per-formance of max-min fairness. Furthermore, it was con-firmed that in a network topology called hypercycle, BF isnot Pareto efficient but some capacity is wasted. This isillustrated in Figure 3. Fortunately it turns out that in a dy-namic setting the impact of the capacity waste is minor. Ananalytical representation for the balance function of a sym-metric 3-link hypercycle was obtained in [11].

The concept of BF was extended in [12] to the case wherethe constraints are more complicated than fixed link capac-ity constraints. In particular, [12] outlines an approach forthe case where the flows can be split over several routes

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Figure 3: The capacity waste in a 3-link hypercycle.

and the constraints are then of the type encountered in mul-ticommodity flow problems. The important insight is thatin a given statex, given the balance function for all statesy < x, the balance condition (1) fixes the capacity allo-cations up to a multiplicative factor1/Φ(x). Then,Φ(x)can be recursively determined by making it at each pointas small as allowed by whatever constraints the system issubject to.

This idea was further developed in [13], where the jointproblem of scheduling and resource sharing was studied inan ad hoc network, where the simultaneous use of somelinks is limited by the interference. In an idealized model,the effect of scheduling can be viewed as allowing, undercertain limits, a shift of capacity from one link to anotherone. Again, the system constraints are not just fixed linkconstraints. By applying the extended BF principle, it waspossible to determine both the schedule and resource shar-ing in such a way that the resources are maximally utilizedwhile preserving the balance property guaranteeing the in-sensitivity and robustness of the system. In addition, ana-lytical tractability is retained, at least for smaller systems.

In the FIT project, several studies related BF are still go-

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Figure 4: Bandwidth allocations as a function of timein a simulation run with an adaptive scheduler.

ing on. In [14] the possibility of insensitive adaptive routingis being studied. In insensitive routing, not only the capacityallocations are balanced but also, separately or jointly, thearrival rates determined by the probabilistic routing. In an-other study [15], queueing network models, such as BF, arebeing applied to the analysis of flow throughputs of the datatraffic in a cell of a cellular network with finite user popu-lation. Application of BF to closed queueing networks wasexplored in [16]. A general tutorial on Balanced Fairness isalso available on the web site of the project [17].

III. S CHEDULING AND QUALITYDIFFERENTIATION IN DIFFSERV

During the last decade the Internet has developed into apublic multiservice network that should be able to supportheterogeneous applications and customers with diverse re-quirements. For this reason, quality of service (QoS) provi-sioning in the Internet has gained increasing attention. Gen-eral service architectures, e.g. Differentiated Services (Diff-Serv) [18], have been proposed in the literature for pro-viding QoS. In DiffServ, common resources are allocatedamong service classes. Packet scheduling is the mechanismprimarily responsible for the allocation.

In [19] and [20], we studied issues related to qualitydifferentiation, traffic mapping and scheduling in DiffServ.The focus was on the differentiation of two important qual-ity parameters, capacity and delay. Two models were con-cerned in detail, absolute capacity differentiation and pro-portional delay differentiation with delay bound, and vari-ous packet schedulers were investigated by simulations. Ac-cording to the results, provisioning and differentiation withstatic resource allocation methods is problematic but withsome adaptive schedulers tunable so that consistent differ-entiation can be achieved. Based on these observations, wesuggested that in DiffServ networks an adaptive schedulerwith delay bound should be used for resource allocation.We also argued that from applications point of view it isbeneficial to map different traffic types into separate serviceclasses.

Figures 4 and 5 illustrate the behaviour of an adaptivescheduler (HPD with delay bound) in a simulation run withmixed traffic in four service classes. It can be seen that thebandwidth allocation follows quite well the development ofqueue lengths: if the queue of a class starts to build up, moreresources are allocated to the class.

IV. A DAPTIVE L OAD BALANCING USINGMPLS

Multiprotocol Label Switching (MPLS) [21] brings upnew possibilities to improve the performance of IP net-works. Notably the explicit routing of MPLS facilitates bal-ancing the load by moving traffic from a congested part ofthe network to some other part in a well controlled way.

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Figure 5: Queue lengths as a function of time in a simulationrun with an adaptive scheduler.

In [22], we studied adaptive load balancing based onmeasured link loads without knowledge of the full trafficmatrix. As an objective for load balancing we used min-imizing the maximum link utilization and minimizing themean delay in the network. A simple adaptive and dis-tributed algorithm was presented to obtain these objectives.In addition, a numerical method was developed to evaluatethe performance of the algorithm. The method was appliedto three test networks. The results showed that the maxi-mum link utilization and the mean delay obtained in a rea-sonable number of iterations are very close to the optimalvalues, even with random traffic fluctuations in the time-scale of the measurements.

Figure 6 illustrates how our adaptive algorithm ap-proaches the lowest possible level of the maximum link uti-lization (0.54) in less than 100 iterations when applied toa test network with 10 nodes, while the standard min-hoprouting results in a much higher level of congestion corre-sponding to the maximum link utilization of 0.88. Three

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Figure 6: The maximum link utilization as a function ofthe number of iterations in a numerical evaluation run of anadaptive load balancing algorithm.

different adaptation granularities are applied. With a finergranularity (g = 50, 100), the adaptive algorithm convergesslightly slower but much more smoothly than with a coarsegranularity (g = 10).

V. OPTICAL BURST SWITCHING

Wavelength division multiplexing (WDM) is a tech-nique, where several optical channels are used concurrentlyto transfer massive amounts of information, even terabitsper second, in a single optical fibre. Optical networks em-ploying WDM play already an important role in the cur-rent backbone networks and the trend is that WDM will beadopted also in MAN and finally in LAN networks.

In optical burst switching network optical bursts are usedto transfer the data [25]. Each burst consists of several con-catenated (IP) packets all having the same destination nodeand thus routed along the same path. Hence, the opticalburst switching (OBS) can be seen as an intermediate stepfrom the wavelength routed networks (i.e. circuit switching)towards the optical packet switching.

In an OBS network the necessary resources are typicallyreserved only for the duration of the burst. In particular,the source node first sends a control packet or frame to in-form the receiver (and possibly intermediate nodes) aboutthe coming burst. The receiver and intermediate nodes eachcheck, one at a time, if the switches along the path canbe configured to deliver the burst successfully towards itsdestination. Meanwhile, after a certain offset time, the ac-tual data burst is sent along the same path without waitingfor any acknowledgment from the receiver (or intermediatenodes).

Optical ring network is a suitable solution for metropoli-tan area networks (MAN). One cost effective solution us-ing the OBS paradigm is described in [26, 23], where eachstation of the ring has a dedicated fixed “home wavelengthchannel” for transmitting its bursts. In addition to thesedata channels also a shared control channel with a certainnumber of circulating control frames is used to inform theother nodes about the arriving bursts resulting a time slot-ted system. Thus, the number of wavelength channelsW isequal toN +1, whereN is the number of stations. Further-more, each station has only one adjustable receiver. Thus,no transmissions collide in the fibre. But, as each station canlisten to at most one channel at a time, burst losses may oc-cur at the receiver in the case two or more concurrent burstshave the same destination node. The traffic pattern for acase withN = 4 nodes is illustrated in Figure 7.

In [24] we have studied, both analytically and numeri-cally, the performance of the MAC protocols proposed in[26] under static traffic conditions. In particular, we haveconsidered both random order and round-robin transmissionpolicies. When a station operates in random order policy thetransmission queue to be served next is chosen randomly

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idle time forreceiver 1

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Figure 7: Arrival process in OBS-ring network.

among the non-empty queues. In round-robin transmissionpolicy the non-empty transmission queues are served in afixed order so that during a one full period one burst is trans-mitted from each queue. In the analysis we have consid-ered an arbitrary receiver and derived formulae for the burstblocking probability and the so called (receiver) efficiency,i.e. the proportion of the time the receiver is active. In Fig-ure 8 the efficiency is depicted for both random order andround-robin transmission policies in a certain traffic case. Itcan be seen that the round-robin order, while generally be-ing a more fair, leads to a worse efficiency, and hence, to ahigher blocking probability.

In [24], special attention has been given to the perfor-mance under an extremely heavy load, where each sourcehas always bursts to be sent to allN − 1 other destinations,i.e. the offered load isρ = 1. Although this symmetricheavy traffic scenario does not hopefully exist, it gives alower bound on blocking probability for each MAC protocoland allows comparing their worst case performances. Notethat in an ideal situation the blocking probability would bezero and each receiver busy all the time, leading to an av-erage pairwise throughput ofC/(N − 1), whereC is thecapacity of one channel andN the number of nodes. How-ever, in [24] we have shown that without any coordinationbetween the nodes the actual throughput will be consider-ably less, i.e. about a half of that. This heavy traffic scenario

3 4 5 6 7 8 9 100.5

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Figure 8: Receiver efficiency under a heavy traffic load forrandom order (upper curve) and round-robin (lower curve)transmission policies as a function of the number of activenodes.

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Figure 9: Efficiency forN = 10 (upper curve) andN = ∞(lower curve) as a function of mean burst size. The constantline represents the efficiency for very long bursts.

is depicted in Figure 9. From the figure it can be seen thatthe mean burst size should be about5 slot times or more inorder to achieve a reasonably high efficiency, where the slottime is equal to the interarrival time of control frames.

VI. T RAFFIC M ATRIX ESTIMATION

The traffic matrixx, which gives the volume of trafficbetween each origin/destination (OD) pair in the network,is a required input in many network management tasks. Un-fortunately, the traffic matrix cannot be directly measured.Only the link loadsy and the routing matrixA are available.These satisfy the relation

y = Ax. (2)

Since in any realistic network there are many more OD pairsthan links, the problem of solvingx from A andy is highlyunderdetermined and the problem is ill-posed.

To overcome the ill-posedness, some type of additionalinformation has to be brought in to solve the problem.Typically, prior information is incorporated into the traf-fic matrix estimation using different traffic models. Mostpromising proposed methods include Bayesian inferencetechniques and network tomography [28, 29, 30]

The Vaton-Gravey iterative Bayesian method [31] con-sists of iteration and exchange of information between two“boxes”; the first calculating an estimate for the traffic ma-trix, given the observed link counts and parameter valuesof the prior, and the second updating the parameter values.Both boxes involve extensive numerical simulations or nu-merical algorithms.

In the FIT project, a study [27] of the above idea has beenconducted with simplifying assumptions. The aim has beento gain insight into the method and, in particular, the outputof the first box by examining a model simple enough to becomputed analytically. Independence and normality are as-sumed for the OD pair distributions. This reduces the com-plexity of the Vaton-Gravey method. Our prior information

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consists of the mean and the covariance matrix of the Gaus-sian distribution. The attractive feature of this approach isthat the distribution conditioned on the link counts is againGaussian and analytical results can be obtained. When it-eration is performed, it turns out that the expected value ofthe mean does not change in the iteration after the first con-ditioning on link counts has been made.

We have shown that when the mean,m, and the covari-ance,C, of the Gaussian distribution is iterated, the expec-tation of the result(m, C) of an iteration round can be writ-ten as {

m(i+1) = GAµ + Hm(i),

C(i+1) = C + GAΣ(GA)T,

whereG, H andC depend on the covariance of the priordistribution, whileA andΣ are constant matrices. The in-dex i refers to the iteration round. We have proven that themeanm does not change after the first iteration.

Figure 10 illustrates the situation when two OD pairs areto be estimated from a single link count. On the left is theprior distribution. The real distribution that we are tryingto find out is shown on the right. From equation (2) weknow the sum of the two variablesx1, x2, telling that themean of the distribution is somewhere along the line shownin the picture. The resulting distribution is shown in red,and is the estimate of the real distribution based on the priordistribution and link loads. The green dots are produced bysampling from the conditional distribution, and are seen tocoincide with the explicitly calculated result, as expected.

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Figure 10: Result of the first iteration.

Directions for future work may include for examplestudying the possibility of utilizing the covariance matricin the estimation. This requires assuming a certain relationbetween the mean and the variance of the OD pairs.

VII. M ODEM POOL TRAFFIC SURVEY

We continued collection and analysis of the HUT mo-dem pool statistics started in the previous project (Com2)funded by the Academy of Finland. In addition to the ear-lier samples from years 1997 and 1998 surveyed in [35], wegot new samples in 2001 and 2002. A comparative studywas carried out and the results were presented in [36]. Anillustration of the results for 2002 is given in Figure 11. Acomparison with the results of 2001 shows that the daily us-age profile has remained very much the same but the overalltraffic level has decreased almost to a half, presumably dueto a shift from modem to ADSL connections.

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Figure 11: The number of student users as a function of timeduring the weekdays in October of 2002.

VIII. S TABILITY ANALYSIS OF ANADMISSION CONTROL M ECHANISM

In DiffServ Networks, the suggested resource allocationmechanisms for bandwidth brokers are based on incompleteinformation about the network state. In this project, we haveinvestigated the impact of this lack of information to thestability properties of the mechanisms. To facilitate analyti-cal treatment, we have restricted ourselves to a simple two-server network with feedback admission control, depictedin Figure 12.

Rather surprisingly, it was found that this simple networkhas a non-trivial stability region. A paper on this discoveryhas been submitted for publication [32]. The solution of theproblem is depicted in Figure 13, with unit input rate. Theparameter space of the server rates is partitioned into fourregions. HereA1 is the domain where the system is neverstable, no matter how strict admission control is employed.RegionsA2 andA3 represent the situation where the over-loaded network can be stabilized;A2 requires strict enoughadmission control to be stable, whileA3 is stable with any

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1(X2<=K)

X1 X2

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Figure 12: The admission controller (AC) tracks the state ofthe server 2. If the size of the queue for the server 2 exceedsa given threshold K, the AC will block all incoming traffic.

control threshold. InA4 there is no overload present, andthus the network is always stable. The phase diagram illus-trates how accelerating server 1 drives the system towardsmore stable regions, while rather paradoxically, speeding upserver 2 may unstabilize the network. In [32] these resultsare proven and extended to more complex controllers, giv-ing easily verifiable stability conditions for the network interms of the system parameters.

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Figure 13: Phase diagram of the network with feedback ad-mission control.

Another related problem studied in this project was con-nected with traffic modelling. An interesting new limit pro-cess had been recently found (later published as [33]) thatresulted in simultaneous increase of the number of sourcesand the timescale. A proof of an analogous result for uni-variate distributions with a somewhat different traffic modelwas found independently, but the authors of [33] extendedtheir paper to cover this model as well. The attention wasmoved to another aspect of long-range dependent traffic:its behaviour under measurement-based admission control.This means a scheme where traffic flows are accepted tothe network according to the measured load. The goal was,in rigorous mathematical terms, to understand the empiri-cal observation of [34] that such a control almost removeslong-range dependence, and to study how reliable this kindof feedback mechanisms would be. This type of questionis closely connected with the question studied in [32], andthere are plans to extend the type of results obtained in [32]for stability of Markovian networks to limiting distributionswith heavy-tailed input processes.

IX. R ESULTS AND I MPACTS

Within the FIT project so far two Master’s theses havebeen completed (J. Antila and V. Timonen) and one morewill be completed in 2004 (S. Liu). One PhD work will becompleted in 2004 (E. Hyytiä), two others are at an inter-mediate phase (L. Leskelä and R. Susitaival), and two moreat an early phase (I. Juva and J. Leino).

The FIT project has been an important element in helpingthe HUT and VTT groups to strengthen their internationalcontacts and collaboration. During the project the groupshave been actively participating in the action COST279,where also work done in this project has been reported.

Both the VTT and HUT groups were invited to becomemembers in Euro-NGI, a Network of Excellence of the EU6th Framework Programme. Altogether 58 partners are in-volved in this three-year activity, which was started in De-cember 2003.

The appropriation for Senior Scientist received by Prof.Virtamo in association to this project enabled very fruitfulvisits to France Telecom R&D and to Cambridge Univer-sity. The work on balanced fairness was initiated duringthese visits, and the collaboration with the researcher’s atFrance Telecom R&D continues. Several studies related tothis topic are going in the Networking Laboratory.

Prof. Virtamo has served as a member of Scientific Com-mittee of the forthcoming program on Queueing Theoryand Teletraffic Theory at the Institute Mittag-Leffler of theRoyal Swedish Academy of Sciences. Several researcherof the project are going to participate in the Program by alonger stay at the Institute during autumn 2004.

Networking Laboratory of HUT hosted the 16th NordicTeletraffic Seminar, NTS-16, which was held in Otaniemi inAugust 2002 [37]. The seminar was supported by a separategrant from the Academy of Finland.

The results of the FIT project have been annually pre-sented in a half-day seminar jointly organized with the do-mestic COST279 project funded by Tekes. Researchersfrom the academia and industry have been invited to attendthe seminar. Links to the programs of the last two seminarsare given in [38].

The program library of teletraffic theory functions [8]has been maintained and developed. New functions andalgorithms have been added into the library, notably thoserelated to calculating the performance under balanced fair-ness, as well as algorithms needed for network calculationsand synthetic network generation for simulation purposes.

References

[1] J. Mo and J. Walrand, 2000, “Fair end-to-end window-based congestion control”, IEEE/ACM Transactionson Networking, Vol. 8, pp. 556-567.

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[2] T. Bonald, A. Proutière, 2003, “Insensitive bandwidthsharing in data networks”, Queueing Systems, Vol. 44,pp. 69-100.

[3] T. Bonald, A. Proutière, 2002, “Insensitivity inprocessor-sharing networks”, Performance Evalua-tion, Vol. 49, pp. 193-209.

[4] T. Bonald, A. Proutière, 2004, “On performancebounds for balanced fairness, Performance Evalua-tion”, Vol. 55, pp. 25-50.

[5] R. Serfozo, 1999, “Introduction to Stochastic Net-works”, Springer-Verlag, Berlin.

[6] T. Bonald, A. Proutière, J. Roberts and J. Virta-mo, 2003, “Computational aspects of balanced fair-ness”, Proceedings of the 18th International TeletrafficCongress (ITC-18), pp. 801 - 810.

[7] T. Bonald and J. Virtamo, 2004, “Calculating the flowlevel performance of balanced fairness in tree net-works”, to appear in Performance Evaluation.

[8] Qlib, Program Library for Traffic Theory Functions,http://www.netlab.hut.fi/qlib/.

[9] J. Virtamo, 2004, “Insensitivity of a network of sym-metric queues with balanced service rates”, submitted.

[10] V. Timonen, 2003, “Simulation Studies on Per-formance of Balanced Fairness”, Master’s Thesis,Helsinki University of Technology, Networking Labo-ratory, Report 6/2003.

[11] J. Virtamo, 2003, “On the balance function of a homo-geneous hypercycle”, Technical Report.

[12] L. Massoulié and J. Virtamo, 2003, “Extending the no-tion of balanced fairness”, Technical Report.

[13] A. Penttinen and J. Virtamo, 2004, “Performance ofwireless ad hoc networks under balanced fairness”, tobe presented in Networking’04, Athens.

[14] J. Leino, 2004, “Insensitive Routing”, Tech. Report.[15] S. Liu, 2004, “Quasi stationary limit of the data traffic

performance of a wireless cell with finite user popula-tion”, work in progress (Master’s thesis).

[16] J. Virtamo, 2003, “Calculating the normalization con-stant for closed networks”, Technical Report.

[17] J. Virtamo, 2003, “Balanced fairness – insensitivebandwidth allocation”, tutorial presentation, 80 pages.

[18] S. Blake, D. Black,M. Carlson, E. Davies, Z. Wangand W. Weiss, 1998, “An Architecture for Differenti-ated Services”, IETF RFC 2475.

[19] J. Antila, 2003, “Scheduling and quality differen-tiation in Differentiated Services”, Master’s Thesis,Helsinki University of Technology, Networking Labo-ratory, Report 5/2003.

[20] J. Antila and M. Luoma, 2003, “Scheduling and qual-ity differentiation in Differentiated Services”, Pro-ceedings of MIPS, November 2003, pp. 119-130.

[21] E. Rosen, A. Viswanathan and R. Callon, 2001, “Mul-tiprotocol Label Switching Architecture”, IETF RFC3031.

[22] R. Susitaival, S. Aalto and J. Virtamo, 2004, “Adap-tive load balancing using MPLS”, submitted for pub-lication.

[23] T. Battestilli, 2002, “Optical burst switching: A sur-vey”, Technical Report TR-2002-10, North CarolinaState University.

[24] E. Hyytiä and L. Nieminen, 2004, “Analytical lossmodels for MAC protocols in optical ring network op-erating under a static traffic load”, submitted for pub-lication.

[25] C. Qiao and M. Yoo, 1999, “Optical burst switching(OBS) - a new paradigm for an optical internet”, Jour-nal of High Speed Networks, Vol. 8, pp. 69-84.

[26] L. Xu, H.G. Perros, and G.N. Rouskas, 2002, “A sim-ulation study of protocols for optical burst-switchedrings”, Proceedings of Networking 2002, pp. 863-874.

[27] I. Juva, P. Kuusela, J. Virtamo, 2004, “A Case Studyon Traffic Matrix Estimation under Gaussian Distribu-tion”, Technical Report.

[28] A. Medina, N. Taft, K. Salamatian, S. Bhattacharyya,and C. Diot, 2002, “Traffic matrix estimation: Exist-ing techniques and new directions”, ACM SIGCOMM2002, Pittsburg, USA.

[29] C. Tebaldi and M. West, 1998, “Bayesian inferenceon network traffic using link count data”, Journal ofthe American Statistical Association, Vol. 93, pp. 557-576.

[30] Y. Vardi, 1996, “Network Tomography: Estimat-ing Source-Destination Traffic Intensities from LinkData”, Journal of the American Statistical Associa-tion, Vol. 91, pp. 365-377.

[31] S. Vaton, A. Gravey, 2004, “Network tomography: aniterative Bayesian analysis”, Proceedings of the 18thInternational Teletraffic Congress, ITC-18.

[32] L. Leskelä, 2004, “Stabilization of an OverloadedQueueing Network Using Measurement-Based Ad-mission Control”, submitted for publication.

[33] R. Gaigalas and I. Kaj, 2003, “Convergence ofscaled renewal processes and a packet arrival model”,Bernoulli, Vol. 9, No. 4, pp. 671-703.

[34] G. Bianchi, V. Mancuso and G. Neglia, 2002,“Is Admission-Controlled Traffic Self-Similar?”, Pro-ceedings of Networking 2002, Pisa, Italy.

[35] J. Lakkakorpi, 1999, “Traffic in modem pools ofHelsinki University of Technology”, Helsinki Univer-sity of Technolgy, Laboratory of TelecommunicationsTechnology, Technical Report.

[36] A. Matinlauri, 2003, “Modem pool traffic survey con-tinued”, Helsinki University of Technolgy, Network-ing Laboratory, Technical Report.

[37] http://www.netlab.hut.fi/nts16/.[38] http://www.vtt.fi/tte/tte21/cost279/seminar.htm,

http://www.netlab.hut.fi/tutkimus/cost279/FITsemi-nar_2004.htm

66

TELETRONICS Research Programme Final Report

BLIND SIGNAL SEPARATION IN COMMUNICATIONS RECEIVERS AND ANTENNAARRAY SYSTEMS

Erkki Oja1 (Project Coordinator), Visa Koivunen2, and Jyrki Joutsensalo3

1. Helsinki University of TechnologyNeural Networks Research Centre

P.O. Box 5400, FIN-02015 HUT, [email protected]

2. Helsinki University of TechnologySignal Processing Laboratory

P.O.Box 3000, FIN-02015 HUT, [email protected]

3. University of JyväskyläLab

Post [email protected]

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ABSTRACT

In this Teletronics II project of the Academy of Finland,blind source separation (BSS) is proposed as an advancedadd-on tool in DS-SS communication systems and antennaarrays. The main new results were as follows:

First, BSS was considered as a pre-processing tool forblind suppression of interfering jammer signals in DS-SScommunication systems utilizing antenna arrays. The mo-tivation for this the ability of BSS/ICA to provide an un-jammed signal to the conventional detection, and thus im-prove the detection performance under different jammingscenarios. Two possible switching schemes were consid-ered, called pre-switching and post-switching, which ac-tivate the ICA-based jammer canceler only when it is ex-pected to improve conventional RAKE-based detection.

Second, BSS/ICA was considered to enhance the perfor-mance of conventional interference cancellation schemes.The new scheme combines the benefits of existing BSS basedschemes and conventional successive interference cancella-tion (SIC). The motivation for this is to enhance the sys-tem capacity, since conventional interference cancellationschemes fail in highly loaded systems. However, the use ofover-complete ICA somewhat circumvents this problem andhence increases the system capacity.

Third, adaptive decision feeedback equalizers (DFE) andsubspace methods for equalizing FIR-MIMO channels weredeveloped. The main contribution is a novel MIMO DFEwhich belongs to the family of non-connected MIMO DFE’s.This implies that individual DFE’s are applied on the re-ceived signals. This type of DFE is used in combinationwith a Kalman filter in order to achieve equalization of time-varying channels.

1. INTRODUCTION

This Teletronics II project proposed three subtasks: 1. ba-sic research into adaptive separation algorithms, 2. blindMIMO equalization and antenna array processing, and 3.blind source separation for spread spectrum receivers. Onthe topic of the first subtask, the participating laboratories(especially at Helsinki University of Technology) have ex-tensive projects going on mostly outside this Teletronicsprogramme, as parts of their Academy Center of Excellenceprogrammes. The CIS lab also worked on separation algo-rithms in an EU project. It is somewhat difficult to separatethe work done in the Teletronics project from those moreextensive research efforts. Therefore, this report concen-trates on the more concrete telecommunication approachesin subtasks 2 and 3 and refers to the theoretical work in thiscontext.

This report first covers the basic separation algorithms,followed by subtask 2 and subtask 3. After that, some con-clusions and administrative issues are reviewed.

2. BLIND SIGNAL SEPARATION BYINDEPENDENT COMPONENT ANALYSIS

Independent Component Analysis (ICA) (see the textbookrecently co-authored by one of the partners in this project[1]) is an increasingly popular statistical signal processingtechnique. The goal of ICA is to express a set ofm ob-served signalsx1(t), . . . , xm(t) at time t as linear combi-nations ofn unknown but statistically independent compo-nentss1(t), . . . , sn(t) called usually sources or source sig-nals. The ICA problem is blind, because not only the sourcesignals but also the mixing coefficients are unknown.

Introducing the data vectorx(t) = [x1(t), . . . , xm(t)]T

and the source vectors(t) = [s1(t), . . . , sn(t)]T , the instan-taneous noisy linear ICA mixture model is given by

x(t) = As(t) + n(t) (1)

Here them×n unknown but constant mixing matrixA con-tains the mixing coefficients, andn(t) denotes the additivenoise vector at timet. We make the standard assumptionsthatA has full column rank, and thatn ≤ m, meaning thatthere are at most as many source signalssj(t) as mixturesxi(t) [1].

The source signalss(t) are estimated using only the ob-servationsx(t) by finding ann × m unmixing matrixW

such that then-vectorWx(t) recovers the original sourcesas well as possible. Because of the blindness of the prob-lem, only the waveforms of the sources can be estimated.For estimating the unmixing (separating) matrixW, manydifferent methods have been proposed; see [1] for an exten-sive discussion.

In most ICA methods, the data are first pre-whitenedspatially, because this makes the subsequent separation taskeasier [1]. In whitening, the observed mixturesr(t) aretransformed linearly so that their components become un-correlated and have unit variance:

y(t) = Tr(t), E{y(t)y(t)H} = I (2)

Herey(t) is the whitened data vector,T a whitening trans-formation matrix,I the unit matrix, andH denotes complexconjugation and transposition. Whitening is often carriedout via principal component analysis (PCA), which yieldsfor complex-valued data the transformation matrix

T = Λ− 1

2s UH

s (3)

There the matricesΛs andUs respectively contain the eigen-values and eigenvectors of the autocorrelation matrix E{r(t)r(t)H}of the received data vectorsr(t). When PCA is used forwhitening, it is easy to reduce the dimensionality of the datavectors simultaneously if desired by using only the principaleigenvectors inΛs andUs; see [1] for details.

68


In our experiments, we mostly applied the complex-valuedversion [2, 1, 16] of the so-called FastICA algorithm to thewhitened mixturesy(t) for separating the sources. The coreof this algorithm is updating of theith columnwi of the or-thogonal separating matrixW according to [2, 1]

w+i = E{y(t)[wH

i y(t)]∗|wHi y(t)|2} − γwi (4)

wherew+i is the updated value ofwi, and∗ denotes com-

plex conjugation. The constantγ is 2 for complex-valuedsignals, and 3 for real ones. In practice, the expectation Ein (4) is replaced by computing the respective average overthe available set of whitened data vectorsy(t). In additionto (4), the columns ofw+

i must be orthonormalized aftereach step. This can be carried out for example via Gram-Schmidt orthogonalization. FastICA and its different vari-ants are discussed thoroughly in [1]. Instead of FastICA,other ICA algorithms introduced for complex-valued mix-tures could be used.

3. BLIND MIMO EQUALIZATION AND ANTENNAARRAY PROCESSING

In order to improve effective data rates and consequentlyeffective spectral efficiency, blind receiver structures havebeen developed. The term blindness means that the receiverhas no knowledge of either the transmitted sequence or thechannel impulse response. Channel identification, equal-ization or demodulation is then performed using only somestatistical or structural properties of the transmitted and re-ceived signal. Training data can then be either completelyexcluded or significantly reduced, and information symbolstransmitted instead. In the face of deep fades, blind meth-ods may allow for tracking fast variations in the channeland re-acquiring operational conditions using informationsymbols only. The processing in blind receivers is typicallynonlinear. Common design goals for blind receiver algo-rithms are the following:capability to identify any type ofchannel; fast convergence to the desired solution, capabilityof tracking channel time-variations, and low computationalcomplexity.

Systems employing multiple transmitters and receiversmay be modeled as Multiple-Input Multiple-Output (MIMO)systems. Such systems provide major improvement in spec-tral efficiency (bits/s/Hz) and link quality by exploitingthe diversity (multiple independent channels between thetransmitter and receiver) and array (SNR) gains. Radio spec-trum is a scarce and expensive resource. The potentiallyhigh capacity of MIMO systems may be achieved only ifthe channels are reliably estimated. Furthermore, effectivespectral efficiency in these systems is reduced by large amountof training data. Hence, there is a strong motivation to de-velop blind and semi-blind receivers for MIMO systems,too.

In this project, adaptive decision feedback equalizers(DFE) and subspace methods for equalizing FIR-MIMO chan-nels were developed. These methods are briefly described inthe following. Publications [29]–[37] give detailed deriva-tions as well as performance analysis of the proposed meth-ods.

3.1. Subspace method for blind identification of MIMOsystems

In blind MIMO system identification, the input-output rela-tionship may be rewritten in the form of a low rank model ifsufficient number of received data samples is available. Thefact that the column space of the received data matrix andcolumn space of the channel matrix span the same subspacemay then be exploited in determining the parameters of FIR-MIMO model. A well-known noise subspace method canbe used to determine the channel matrix up to an ambiguitymatrix. It is a constant full rankK ×K matrix, whereK isthe number of transmitted sources.

The remaining ambiguity matrix models an I-MIMO sys-tem with non-gaussian communication signals. The systemmay be solved using blind source separation (BSS) if thesources can be assumed to be statistically independent. Thisis reasonable assumption if signals originate from differentusers.

3.1.1. Signal model

We assume the standard FIR-MIMO baseband signal modelwith K transmitters andP receivers, in which the receivedsignal x(n) having P components arranged as a columnvector is of the form

x(n) =

L∑k=0

Hks(n − k) + v(n). (5)

Heres(n) = (s1(n), s2(n), . . . , sK(n))T is aK-dimensionalsignal vector (P > K), L is the channel order,{Hk}k=0,...L

are the the unknownP ×K matrix-valued impulse responsecoefficients accociated with the transfer functionH(z) =∑L

k=0 Hkz−k, andv(n) is noise. In this work we use thenotationH = [HT

0 ,HT1 , . . . ,HT

L]T .We assume that

rank(H(z)) = K for each z (6)

H(L) is of full column rank. (7)

These assumptions are needed to ensure the channel identi-fiability by using only second order statistics of the receivedsignal vectorx(n). By stackingN + 1 observations of (5)into an (N + 1)P × 1 vector X(n) = [xT (n),xT (n −1), . . . ,xT (n − N)]T we may write

X(n) = HN (H)S(n) + V(n). (8)

69


Here,S(n) = [s(n)T , s(n − 1)T , . . . , s(n − N − L)T ]T ,V(n) = [v(n)T ,v(n−1)T , . . . ,v(n−N)T ]T andHN (H)is the(N +1)P ×K(L+N +1) channel matrix (Sylvestermatrix) given by

HN (H) =

H0 H1 · · · HL 0 · · · 0

0 H0 H1 · · · HL

. .. 0...

. . .. ..

.. ... .

. .. 0

0 · · · 0 H0 H1 · · · HL

Assumptions (6) and (7) imply that the channel matrix is offull column rank when the st acking parameterN is chosensufficiently large.

3.1.2. Channel identification

The channel may be identified using a subspace methodlater extended to MIMO systems. Assume thatX(n) givenin (8) is a wide-sense stationary process and the signalS(n)and noiseV(n) are mutually independent and o f zero mean.The covariance matrix ofX(n) is

E{X(n)X(n)H} = Σ = HN (H)ΣsHN (H)H + Σv,

whereΣs = E{S(n)S(n)H} is the signal covariance ma-trix of full rank, andΣv = E{V(n)V(n)H} is the noisecovariance matrix of the formΣv = σ2I, whereσ2 is thenoise power. The maximum channel orderL is assumed tobe known.

Denote the noise subspace eigenvectors bygi, i = 1, . . . , r.The orthogonality of the signal and noise subspaces

HHN (H)gi = 0, i = 1, . . . , r.

allows for identification of the channel matrixH up to aright multiplication of an invertibleK × K ambiquity ma-trix.

We may partition the noise subspace eigenvectors as

gi = [g(i)T

0 ,g(i)T

1 , . . . ,g(i)T

N ]T , (9)

whereg(i)k , k = 0, 1, . . . , N are of sizeP × 1. Define

Gi =

g

(i)0 g

(i)1 · · · g

(i)N 0 · · · 0

0 g(i)0 g

(i)1 · · · g

(i)N

. .....

.... . .

.. .. . .

.. .. .. 0

0 · · · 0 g(i)0 g

(i)1 · · · g

(i)N

(10)

It can be shown that for each column of the matrixH,hi, i = 1, . . . , K,

hHi

(r∑

i=1

GiGHi

)hi = 0.

Moreover, the dimension of the null space of the matrix

C =r∑

i=1

GiGHi

is K. This implies that

H = BR−1

whereB is aP (L + 1) × K matrix of the eigenvectors ofC corresponding to the noise subspace eigenvalues, andR

is an invertibleK × K matrix. We may now determine thechannel matrix up to a right multiplication of an invertibleK × K ambiguity matrix, i.e.,

B = HR. (11)

3.1.3. Equalization using subspace method and BSS

Assume that we know the channel matrix up to the ambigu-ity matrix R, i.e. we knowB = HR. Then

HN (B) = HN (H)R,

whereR is aK(L+N +1)×K(L+N +1) block diagonalmatrix

R =

R 0 · · · 0

0 R · · · 0...

.. . 0

0 0 · · · R

.

Consider the noise-free case of the signal model (8)

X(n) = Hn(H)S(n).

Let HN (B)† be the pseudo-inverse of the matrixHN (B),i.e.

HN (B)† = (HN (B)HHN (B)−1HN (B)H .

Now it is easy to see that

HN (B)†X(n) = Y(n) = R−1S(n)

orS(n) = RHN (B)†X(n).

Note that

R−1 =

R−1 0 · · · 0

0 R−1 · · · 0...

. . . 0

0 0 · · · R−1

and consider, for example,K first components ofY(n).Denote these components byy(n). Then

y(n) = R−1s(n).

70


This is in a form of I-MIMO model. If theK source signalsare statistically independent and non-Gaussian, we may es-timate the signalss(n) up to a permutation and complexscaling, i.e.

s(n) = DPs(n),

whereD is a complex-valued diagonal matrix andP is areal-valued permutation matrix. The separation task may beperformed any BSS algorithm, for example EASI. The re-mainin rotation and scaling of the constellation pattern maybe resolved by using differential coding and the finite alpha-bet property of the communication signals.

3.2. DFE equalizer for MIMO systems

In this subproject we derive an adaptive equalizer for MIMOsystem with independent data streams (spatial multiplex-ing). Decision Feedback Equalizer (DFE) algorithm is ca-pable of identifying, tracking and equalizing time-varyingchannels (TVCs). The algorithm is derived using state-variablemodel. The advantages of the estimation and tracking stagescan be summarized as follows: the estimator is akin to theconventional Kalman filter (KF), it is thus an exact solutionto the estimation problem. The channel estimation stagedoes not require additional knowledge of state-space modelparameters in order to estimate the state. Consequently, thenoise estimation problem need to be addressed. The methodpresented here for estimating the noise statistics relies oncovariance matching between the theoretical and estimatedcovariances of measurement and observation noises. A re-cursive formula is derived and the quality of the noise statis-tics estimates are assessed by performing a non-parametricwhiteness test on the innovation sequence of the KF. White-ness of innovations is necessary for optimal performance ofKF-based channel estimators.

The main contribution of the project is a novel MIMODFE which belongs to the family of non-connected (NC)MIMO DFE’s. This implies that individual DFE’s are ap-plied on the received signals. This type of DFE is usedin combination with the Kalman filter in order to achieveequalization of time-varying channels. The DFE structureis derived using the MMSE criterion. The MIMO DFEcost function takes into account the cross channels, hencethe equalizer is able to cancel both the Inter User Interfer-ence (IUI )and the Intersymbol Interference (ISI). The mainassumption is that the input signals and the noise are un-correlated. Combining the Kalman filtering and the MIMODFE we get a true real-time algorithm in the sense that itis recursive in time and the storage space needed to evalu-ate the estimates remains constant, as time progresses andthe amount of received data increases. Consequently, themethod can cope with a large number of parameters.

In our derivation, assuming that the input and noise pro-cesses are uncorrelated we compute pairs of feedforward-feedback filters for the received signal at each antenna based

on the MMSE criterion. Let us start by defining the channelconvolution matricesHij of dimensionNch × Nf , whereNch = L + Nf − 1 andNf is the FF filter length.

Hij(k) =

hij(0;k) 0 . . . 0

hij(1;k) hij(0;k)

...

.

.

.

hij(2;k) hij(1;k) 0

.

.

. hij(2;k) hij(0;k)

hij(Lh−1;k)

.

.

. hij(1;k)

0 hij(Lh−1;k) hij(2;k)

.

.

. 0

.

.

.

.

.

.

.

.

.

...

.

.

.0 0 hij(Lh−1;k)

.(12)

The DFE equalizer hasNf FF coefficients andNb FB co-efficients. This will be written as DFE(Nf ,Nb). Applyingthe FF filter to the pastNf received observations and the FBfilter to the pastNd estimated symbols for each output weget the soft estimate:

zj(k) =

Nf∑q=1

fjqyj(k − q) −Nd∑q=1

djqxj(k − q).(13)

Equalization is achieved via feedforwardfj = (fj1, . . . , fjNf)T ,

and feedbackdj = (dj1, . . . , djNd)T filters. These fil-

ters are obtained by minimizing the following cost functionswith respect tofj anddj :

Jj = E{|xj(k − δ) − zj(k)|2}, (14)

whereδ is the equalization delay. In equation (14) we as-sume that past decisions are correct. Moreover, the inputsequences are assumed to be uncorrelated with each otheror with the noise.

For am × n MIMO system we obtain:

fj = [∑m

i=1i�=j

HHijHij + H

Hij |i=jP

jDF E

Hij |i=j − λI]−1H

Hij |i=jeδ

dj = MjHij |i=j fj ,

(15)

whereMj = (0Nd×δ INd×Nd0Nd×Nch−Nd−δ), and

PjDFE = (I − MT

j Mj). Furthermoreλ =σ2

x

σ2v

andeδ =

(0, . . . , 0, 1, 0, . . . , 0)T is the standard basis vector, with oneat the positionδ, 0 ≤ δ ≤ Nf . The derivation of the abovetwo equations is presented in the Appendix. We note thateven that the DFE’s are non-connected, each of the feedfor-ward filters is taking into account the cross channels of theMIMO model, hence, when performing equalization is alsoable to cancel the inter-user interference. The noise statis-tics needed by the FF filters is estimated using the noiseestimation stage.

Finally, the symbol estimatexi at timek is obtained by:

xi(k) = arg minα∈X

|α − zi(k)|, (16)

whereX is a finite alphabet.

71


4. BLIND SOURCE SEPARATION FOR SPREADSPECTRUM RECEIVERS

4.1. Interference and jammer mitigation

In this subtask, we concentrated on interference and jammermitigation techniques [4, 10, 12]. They have been studiedactively in spread spectrum (SS) communications, becausethey improve the overall system performance and capacitywithout the need for a wider spectrum. In commercial cellu-lar SS and DS-CDMA systems, many types of interferencescan appear, starting from multiuser interference inside eachsector in a cell to inter-operator interference. Unintentionaljamming can also be present due to co-existing systems atthe same band, whereas intentional jamming arises mainlyin military applications.

Interference rejection/cancellation has been consideredone of the most attractive class of suboptimal solutions, andhas been studied extensively in the past [12]–[23]. Paral-lel and successive interference cancellation (PIC and SIC,respectively) are the main categories within this class, de-scribing the procedure by which the interference is sub-tracted from the original data, after regenerating the inter-ference from the tentatively estimated data. This procedurecan, naturally, be repeated many times resulting in multi-stage interference cancellation schemes. Needless to say,any interference subtractive receiver performs the better themore accurately tentative decisions are being made. This isbecause the interference level is then reduced the most.

Considering antenna arrays, jamming can be mitigatedby utilizing spatial diversity. However, when using conven-tional array receivers, directions of arrivals of signals mustbe first estimated. This in turn requires exact prior knowl-edge of the positions of the receiving antenna sensors. Blindtechniques [5, 8, 9, 1] relax this stringent requirement, mak-ing it possible to achieve performance gains when appliedto uncalibrated arrays in which the positions of the sensorsare known only roughly or not at all. Most blind techniquesare based on the assumption that the original source signalsare statistically independent of each other. This assumptionis quite realistic here, because the jammer signal originatesfrom a different physical source than the information bear-ing signal.

In this project, we extended the framework proposed in[5] in three respects. Firstly, we apply BSS techniques basedon independent component analysis (ICA) [1] instead oftemporal correlations. ICA takes into account also higher-order statistics by forcing statistical independence of theseparated signals. This enables jammer suppression for dif-ferent types of jammer signals under realistic conditions.Secondly, we propose a hybrid receiver structure in whichthe ICA-based pre-processing is activated only when it isexpected to improve the performance of the whole receiverchain. Finally, we propose different switching criteria be-

tween ICA and RAKE branches in the receiver chain andevaluate their effects to the performance of the receiver.

Regarding single antenna reception, another applicationof BSS is proposed as well in the project. This is the utiliza-tion of blind source separation (BSS) techniques in interfer-ence subtractive receivers. It is shown how the parametricform of the mixing matrix can efficiently be used to refinethe ICA solution, and hence avoid interference enhance-ment while subtracting that source from the original data.The BSS-SIC -type receiver is also developed for highlyloaded systems. Recall that a major drawback for standardBSS is the case where the number of source signals (to beblindly extracted from the received data) is greater than thenumber of observations made. This is a commonplace sit-uation in communications applications in which cases stan-dard BSS model doesn’t hold anymore. The key finding inthis problem was the ability of a BSS-SIC -type receiverstructure to somewhat circumvent the “more sources thanobservations”-problem in the sense that adequate performance(in terms of bit-error probability) is still achievable even inextremely highly loaded system, whereas conventional par-allel and successive interference cancellation only remain ata moderate level.

4.2. Signal models

A standard spread spectrum system [19] with direct sequencespreading is assumed. Without loss of generality, we con-sider here a downlink channel (for example base-to-mobile).Thus the data describing the received block ofM symbolsis of the form [11, 20]

r(t) =

M∑m=1

K∑k=1

am bkmsk(t − mT − d) + n(t) (17)

where the symbolsbkm are sent toK users via a channelcharacterized by a complex path gainam and a path delayd. The delayd is discrete,d ∈ {0, . . . , (C − 1)/2}, and re-mains constant for every block ofM data symbols. Further-more,sk(·) is kth user’s binary chip sequence, supported by[0, T ), whereT is the symbol duration, andn(t) is Gaussiannoise [20, 19].

The received signalr(t) in (17) is jammed by a signalj(t), which has the form

j(t) = δp(t)√

Jei(2πfjt+φ) (18)

wherei =√−1. The quantityδp(t) = 1 with a probability

p during a symbol. Jamming corresponds to a continuouswave whenp = 1 and pulsed wave at the symbol level oth-erwise. These two cases are used as examples of narrow-band and wide-band jamming1. The power, frequency, and

1Also chip-pulsed jamming could have been considered as an exampleof wide-band jamming.

72


phase of the jammer signalj(t) are denoted respectively byJ , fj , andφ. The phase is assumed to be uniformly dis-tributed over the interval[0, 2π).

Denoting the received antenna datar1(t), . . . , rN (t) wecan represent the array data more concisely in vector formas

r(t) = Θz(t) + n(t) (19)

where the vector

r(t) = [r1(t) r2(t) · · · rN (t)]T (20)

contains the signals received at theN array elements at timet,

z(t) = [r(t) j(t)e−i2πfct]T (21)

is a two-component vector having as its elements the infor-mation signalr(t) and down-converted jammer signalj(t)at timet, and the array steering matrix

Θ =

1 1eiθr eiθj

......

ei(N−1)θr ei(N−1)θj

(22)

The N -vector n(t) is similar in form to (20), containingadditive white Gaussian noise (AWGN) termsni(t) at eachantenna elementi = 1, 2, . . . , N . A comparison of the arraysignal model (19) with the ICA mixing model (1) showsimmediately that (19) is actually a noisy mixing model witha mixing matrixΘ and source vectorz(t). Hence ICA orother BSS techniques can be applied to separation of theinformation signal and jammer signal. Estimates of thesesignals are obtained as the components of the vectorWr(t),but their order and scaling is arbitrary. In case of a singleantenna reception the data model can be represented as [27]

rmdef=

K∑k=1

ak(bk,m−1gk+ bkmgk + bk,m+1gk) + nm

(23)

where a processing window size of two symbols is assumed.Herenm denotes noise vector and the2C-length code vec-tors are delayed (according to the path delay) copies of thesignature sequences.

With a simple manipulation, we can get a compact rep-resentation for the data,

rm = Gbm + nm. (24)

The2C×3K dimensional code matrixG contains the codevectors and path strengths, while the3K-vectorbm con-tains the symbols:

Gdef=

[· · · akgk

akgk akgk · · ·]

(25)

bmdef= [· · · bk,m−1bkmbk,m+1 · · · ]T .

The DS-CDMA signal model (24) is readily a linear noisyICA model (cf. eq. (1)) withm = 2C observations ofn = 3K source components.

4.3. Receiver structures

4.3.1. Suppression of jamming signals using ICA and RAKE

In our jamming problem, RAKE uses prior knowledge onthe desired user’s code, and it can be applied also when ajammer signal is present. However, RAKE does not ex-ploit independence of the information bearing signal fromthe jamming signal in any way. On the other hand, ICA re-lies on the strong but realistic independence assumption, butit is a blind technique which does not take into account thedesired user’s code and the structure of the array steeringmatrix (22). In this work, we combine ICA and RAKE se-quentially when it is reasonable for utilizing better the avail-able prior information on the considered jamming problem.

The basic ICA-RAKE receiver proposed for jammer sig-nal suppression consists of the three blocks (Preprocessing,ICA & Selection, and RAKE Detection); see reference [18].The received vectorsr(t) are first prewhitened, and then theFastICA algorithm (4) is applied to the prewhitened vec-tors y(t) as explained in the previous section. Due to theinherent indeterminacies of ICA [1], two additional tasksmust be performed in the basic ICA-RAKE receiver. Theseare selection of the estimater(t) of the desired informationbearing sourcer(t) among the separated two sources, andestimation of the channel. Notice that in our problem ICAis usually used for separating two sources only, which thenprovide estimates of the components of the vectorz(t) in(21). Recall that the components of the vectorz(t) are theinformation bearing signalr(t) and down-converted jam-mer signalj(t).

ICA can estimate the source signals only up to a permu-tation, and a complex scaling factor can be exchanged be-tween a source and the respective column of the mixing ma-trix [1]. For getting rid of this ambiguity, a short preamblesequence is used, consisting ofNp training symbolssp

d(t)(t = 1, 2, . . . , Np) of the desired userd. The preamble isused for both conventional matched filter based channel es-timation [19], and for identifying the desired informationbearing source among the sources estimated by ICA. Morespecifically, this takes place by matching the preamble se-quencesp

d(t) (t = 1, 2, . . . , Np) of the desired user with thecorresponding portionssp

i (t) (t = 1, 2, . . . , Np) of the sym-bols estimated using RAKE for all the separated sources:

Id = arg maxi

Np∑t=1

distH [spd(t), s

pi (t)]

, i = 1, . . . , NS

(26)Here Id is the selected source index,NS is the numberof separated sources after whitening and ICA filtering, and

73

TELETRONICS Research Programme Final Report∑Np

t=1 distH [spd(t), s

pi (t)] computes the Hamming distance

between the preamble symbol sequencespd(t) (t = 1, 2, . . . , Np)

and the corresponding estimated symbolsspi (t) for the ith

source.Finally, conventional detection is performed for the data

of the selected sourceId. This leads to the basic ICA-RAKEreceiver structure, where the well-known and robust RAKEmethod [13, 19] is used for conventional detection. Wecould have tried instead of RAKE other methods developedfor multi-user detection [20], but in this work the prime in-terest was to study the capability of ICA to mitigate jammersignals prior to the actual detection.

However, the basic ICA-RAKE receiver described aboveas well as the BSS method proposed in [5] are still some-what impractical as such. This is because they employ anICA or BSS block even though it may not always be desir-able. In fact, if the jammer signal is weak or even absent,the additional ICA or BSS jammer suppression block mighteven cause additional interference to the information bear-ing signal. Therefore, we improve the basic ICA-RAKEreceiver by introducing two different switching strategies,pre- and post-switching schemes, which select either ICA-assisted or conventional RAKE detection in the array re-ceiver chain.

The training symbols in the preamble can be used alsoto determine whether the additional jammer suppression byICA is desirable or not. In general, this decision can bemade either before or after ICA has been applied. In thepre-switching scheme, the switch decides whether there isa need to separate the jammer signal by ICA prior to con-ventional detection, or should conventional detection alonebe performed. This decision is based on the performanceof the RAKE detector on the preamble sequencesp

d(t) (t =1, 2, . . . , Np). RAKE alone is applied if sufficiently manysymbols in the preamble are detected correctly:

Np − maxi=1,...,Ns

Np∑t=1

distH [spd(t), s

pi (t)]

< δsNp (27)

whereδs is the chosen threshold value for switching. Inthe post-switching scheme, both ICA-RAKE and RAKEbranches are first active. ICA-RAKE branch provides ten-tative estimatesI

d(t) for thetth symbolsd(t) of the desireduser, and RAKE branch respectively tentative symbol esti-matesR

d (t). The final outputsd(t) of the receiver is selectedfrom the branch which provides higher correlation with thetraining symbols:

maxI,R

(E{sI,p

d (t)spd(t)}, E{sR,p

d (t)spd(t)}

)(28)

That is, both branches first provide their own estimatessI,pd (t)

and sR,pd (t) corresponding to the symbolssp

d(t) belongingto the preamble, and the branch providing better symbol es-timates is then selected and used for the final hard decision.

4.3.2. BSS/ICA Based Successive Interference Cancellation

By an interference subtractive receiver we loosely speakingmean an iterative multi-user receiver, where the estimatedinterference is subtracted from the received signal prior tothe estimation of a particular user. The principle of this kindof receiver utilizing BSS/ICA is quite straightforward andis here only shortly revisited. Namely, the received signal isfirst separated by ICA. After separation, users are identifiedby their spreading codes. Hence, the receiver is semi-blind.Strictly speaking, for the user identification a correlation

ρ(k, k′) =|ck(τk)wH

k′ |‖ck(τk)‖‖wk′‖ (29)

is computed for eachk, k′, wherewk′ corresponds to theICA basis vector ofk′:th source. Next, a threshold,ρ1, is setto indicate proper detection. This is needed because subtrac-tion of erroneously detected signal would actually enhanceinterference. Thus, only the signal corresponding to the userk with ρ(k, k′) > ρ1 for somek′ is subtracted from the re-ceiver signal. After subtraction of all such users’ signals,the next ICA separation is performed for the interference-subtracted signal. The order of ICA model decreases insubtraction, which help ICA to recover the remaining users.The procedure is repeated successively until all users aredetected. Furthermore, one can easily show, that phase ofcomplex numberρ(k, k′) in 29 equals to phase shift pro-duced by ICA. This makes it possible to correct ICA’s phaseambiguity.

It is of primary importance to see that what is actuallysubtracted from the original data is a tentative decision ofthe formakck(τk)bk rather thanwk bk. Hence the ICA so-lution is first refined (according to the knowledge of theparametric form of the mixing matrix) before subtractionis performed.

4.3.3. Joint delay tracking and interference cancellation us-ing BSS/ICA

The receiver structure described above is now developed tocope with inaccuracies in delay estimation. Recall that ICAperforms purely in blind manner. The first occasion wheresome a prior knowledge of the users is needed is the useridentification phase (29). Naturally, the timing informationcan also be used to generate a good initial value for ICA it-erations, and hence speed up the separation [27]. Anyway,what lousy timing estimate ultimately does is that it worsenthe user identification. More importantly, given that a useris nevertheless identified having an erroneous timing esti-mate, the subtraction of that user enhance interference themore the bigger was the timing inaccuracy. To avoid thatsituation the delay of each identified user could first be re-

74


fined according to

δk ← arg maxδ

gk(δ, τk)wHk′

‖gk(δ, τk)‖‖wk′‖ (30)

where the maximization of the correlation is performed ina close neighborhood ofτk, e.g. δ ∈ (−1/2, 1/2). Thesignal corresponding to the userk is re-built after delay re-finement, only after which it is beneficial to go to the sub-traction phase:

rm ← rm − ak(bk,m−1gk(δk, τk) + bkmgk(δk, τk)

+ bk,m+1gk(δk, τk)) (31)

4.4. Experiments

4.4.1. Array reception

An example of the performance evaluation is given in thefollowing. A simulated system withK = 8 users was con-sidered, spread with short Gold Codes of lengthC = 31[13, 19]. The length of the data block wasM = 200 QPSKsymbols. The monitored user was chosen randomly, and thesignal-to-noise ratio (SNR) and the signal-to-jammer ratio(SJR) were defined with respect to this desired user. Theprobability that a bit is jammed was chosen to bep = 0.5.The number of elementsNa is 2. Pre-switching involved ac-tivation of the ICA-RAKE branch only if more than10% ofthe training symbols were erroneously estimated by RAKE.Post-switching involved switching at the decision device,where either the soft decision outputs of the ICA-RAKEbranch or the RAKE branch were decoded, based on theerrors with respect to the training sequence.

In the continuous wave setting, the SJR varied against aconstant SNR of10 dB. Using a pulsed jammer which hada frequency offset resulted in the bit and block error ratesshown in Figs. 1 and 2. Pre-switching is equivalent to MRCin this case, while post-switching results in a gain of1 dB inthe−15 to5 dB region, as seen from the BER curves. In factthe BLER curves show that post-switching outperforms pre-switching by at least2 dB when the target rate is10−1, and itprovides better performance in the region of high jamming.Increasing the number of antenna elements yielded resultswhich are comparable to the two-antenna case.

Computationally, the proposed pre-switching and post-switching schemes are more demanding than the simple RAKEreceiver. Pre-switching requires three times more computa-tion than standard RAKE, and post-switching is computa-tionally clearly more demanding. In general, pre-switchingis suitable for real-time applications, while post-switchingis ideal if real-time operation is not required.

4.4.2. Single antenna reception

As an example the performance evaluation for the single an-tenna interference canceller, considerK users transmitting

−30 −25 −20 −15 −10 −5 0 5 10 1510

−7

10−6

10−5

10−4

10−3

10−2

10−1

100

SJR

BE

R

Post−SwitchingPre−SwitchingMRC N

a = 2

RAKE Na = 1

Fig. 1. Bit-error-rate as a function of SJR at an average SNR= 10 dB. This system hadK = 8 users of equal strengthin an AWGN channel with a bit-pulsed jammer, that had afrequency offset. The antenna was a2 element array.

data blocks ofM = 5000 QPSK symbols. Symbols arespread using Gold codes of lengthC = 31. Two serviceclasses are assumed, which is modelled as a power differ-ence of 10 dB between the two user groups. Inside bothgroups all the users are assigned the same power. The lengthof the all the receivers is2C and hence both the LMMSE-PIC and LMMSE detectors are truncated to that length. Re-call that the optimal length for asynchronous data would beMC (the whole block of symbols) which is not a sensiblechoice for the receiver length in practise [20].

The results demonstrate that ICA-assisted methods main-tain their competence also with great numbers of users. Es-pecially the successive ICA-receiver outperforms referencemethods, SIC and PIC, clearly. This can bee seen in Fig.3 The figure depicts BERs of the ICA-assisted methods aswell as the reference methods as a function ofK (numberof users).

Finally, we also notice from the experiments that theFastICA with successive interference cancellation performsclearly better than astICA alone, given that the delays aretracked, too, see Fig. 4

5. RESULTS AND IMPACTS

We believe that scientifically, the goals of the project havebeen attained. A total number of 28 articles have appeared,of which 3 are journal papers. The ideas have been posi-tively received in many conferences which the partners haveattended. Also industry representatives have shown interest

75


−30 −25 −20 −15 −10 −5 0 5 1010

−4

10−3

10−2

10−1

100

SJR

BL

ER

Post−SwitchingPre−SwitchingMRC: N

a = 2

Rake: Na = 1

Fig. 2. Block-error-rate as a function of SJR at an aver-age SNR = 10 dB. This system hadK = 8 users of equalstrength in an AWGN channel with a bit-pulsed jammer,that had a frequency offset. The antenna was a2 elementarray.

to ideas like inference cancellation. These discussions arecontinuing.

In this consortium, each of the three partners used thefinances essentially for the salary of one graduate studentwhose Ph.D. projects were done in the subtasks. One of thestudents, Mihai Enescu, already got his doctoral degree atthe HUT / SPL in 2002 with the Thesis "Adaptive Methodsfor Blind Equalization and Signal Separation in MIMO Sys-tems". Another one, Karthikesh Raju at HUT / CIS startedhis graduate studies in this project in 2001 and is presentlyfinishing his doctoral thesis. His thesis defense will be inwinter 2005.

On the administrative side, the leaders of the three projectshave met regularly both at HUT and in appropriate confer-ences. The students have attended some winter / summerschools of the graduate schools like GETA.

6. REFERENCES

[1] A. Hyvärinen, J. Karhunen, and E. Oja,IndependentComponent Analysis. Wiley, 2001.

[2] E. Bingham and A. Hyvärinen, “A fast fixed-point algo-rithm for independent component analysis of complex-valued signals”,Int. J. of Neural Systems, vol. 10, 2000,pp. 1-8.

[3] T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based

22 24 26 28 3010

−5

10−4

10−3

10−2

10−1

100

# users (K)

BE

R

Successive ICA−receiverBasic ICA−receiverPIC, 5 stagesSIC

Fig. 3. Bit-error-rates as a function of number of users.Number of FastICA iterations was 110 in ICA based re-ceivers. SNR was fixed to 20 dB wrt. the weakest users.

0 0.01 0.02 0.03 0.04 0.0510

−7

10−6

10−5

10−4

10−3

10−2

10−1

100

Variance of delay estimation error

BE

R

Successive ICA with delay trackingSuccessive ICA without delay trackingBasic ICALMMSELMMSE−PIC (two or more stages)

Fig. 4. Bit-error-rates as a function of variance of delayestimation error in a system ofK = 22 users.

76


receivers for block fading DS-CDMA channels”,SignalProcessing, vol. 82, 2002, pp. 417-431.

[4] M. Amin and Y. Zhang, “Interference suppression inspread spectrum communication system”, in J. Proakis(Ed.), the Wiley Encyclopedia of Telecommunications.Wiley, 2002.

[5] A. Belouchrani and M. Amin, “Jammer mitigation inspread spectrum communications using blind sourceseparation,”Signal Processing, vol. 80, 2000, pp. 723-729.

[6] A. Belouchrani and M. Amin, “A two-sensor array blindbeamformer for direct sequence spread spectrum com-munications”,IEEE Trans. on Signal Processing, vol.47, August 1999, pp. 2191-2199.

[7] J.-F. Cardoso and A. Souloumiac, “Blind beamform-ing for non Gaussian signals”,IEE Proceedings-F, vol.140, no. 6, 1993, pp. 362-370.

[8] G. Giannakis, Y. Hua, P. Stoica, and L. Tong (Eds.),Sig-nal Processing Advances in Wireless and Mobile Com-munications, Vol. 2: Trends in Single- and Multi-UserSystems. Prentice-Hall, 2001.

[9] S. Haykin (Ed.),Unsupervised Adaptive Filtering, Vol.1: Blind Source Separation. Wiley, 2000.

[10] J. Laster and J. Reed, “Interference rejection in digi-tal wireless communications”,IEEE Signal ProcessingMagazine, vol. 14, no. 3, May 1997, pp. 37-62.

[11] U. Madhow, “Blind adaptive interference suppressionfor direct-sequence CDMA”,Proc. of the IEEE, vol. 86,October 1998, pp. 2049-2069.

[12] L. Milstein, “Interference rejection techniques inspread spectrum communications”,Proc. of the IEEE,vol. 66, June 1988, pp. 657-671.

[13] J.G. Proakis, Digital Communications, 3rd ed.McGraw-Hill, 1995.

[14] K. Raju, T. Ristaniemi, and J. Karhunen, “Suppres-sion of bit-pulsed jammer signals in DS-CDMA ar-ray systems using independent component analysis”, inProc. IEEE Int. Symposium on Circuits and Systems(ISCAS2002), Phoenix, Arizona, USA, May 2002, pp.I-189/I-192.

[15] K. Raju and T. Ristaniemi, “ICA-RAKE switching forjammer cancellation in DS-CDMA array systems”, inProc. IEEE Int. Symp. on Spread Spectrum Techniquesand Applications (ISSSTA’02), Prague, Czech Republic,September 2002, 638-642.

[16] T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based receivers for DS-CDMA systems”, InProc. of theIEEE Int. Conf. on Personal, Mobile, and Radio Com-munications (PIMRC), London, UK, September 2000,pp. 276-281.

[17] T. Ristaniemi, K. Raju, and J. Karhunen, “Jammer mit-igation in DS-CDMA array system using independentcomponent analysis”, inProc. IEEE Int. Conf. on Com-munications (ICC2002), New York, USA, April 2002.

[18] T. Ristaniemi, K. Raju, J. Karhunen, and E. Oja, “Jam-mer cancellation in DS-CDMA arrays: pre and postswitching of ICA and RAKE”, inProc. of the 2002IEEE Workshop on Neural Networks for Signal Pro-cessing, Martigny, Switzerland, September 2002, pp.495-504.

[19] A. Viterbi, CDMA: Principles of Spread SpectrumCommunications. Addison-Wesley, 1995.

[20] S. Verdú,Multiuser detection, Cambridge UniversityPress, 1998.

[21] J. M. Holtzman, “DS/CDMA successive interferencecancellation”,Proc. IEEE ISSSTA’94, vol. 1, 1994, pp.69–78.

[22] M. K. Varanasi, B. Aazhang, “Multistage detectionin asynchronous code-division multiple-access commu-nication”, IEEE Transactions on communication, vol.38(4), 1990, pp. 509–519.

[23] M. Latva-aho, J. Lilleberg, “Parallel interferencecancellation in multiuser detection”,Proc. IEEE 4thISSSTA’96, vol. 3, 1996, pp. 1151–1155.

[24] T. Huovinen, T. Ristaniemi, “Blind source separa-tion based successive interference cancellation in theDS-CDMA uplink”, Proc. IEEE ISCCSP2004, March2004, to appear.

[25] T. Huovinen, T. Ristaniemi, “DS-CDMA CapacityEnhancement Using Blind Source Separation BasedGroup-Wise Successive Interference Cancellation”,Proc. IEEE 5th SPAWC2004, July 2004, subm.

[26] M. Latva-aho, M. Juntti, K. Kasanen, “Residual inter-ference suppression in parallel interference cancellationreceivers”,Proc. IEEE ICC’99, vol. 2, 1999, pp. 927–931.

[27] T. Ristaniemi and J. Joutsensalo, “Advanced ICA-based receivers for block fading DS-CDMA channels”,Signal Processing, vol. 82, 2002, pp. 417-431.

77


[28] S. Bensley, B. Aazhang, “Subspace-based channel es-timations for code division multiple access communi-cation systems”,IEEE Trans. Commun., vol. 42, pp.1009-1020, Aug. 1996.

[29] Visuri, Samuli, Koivunen, Visa “Resolving Ambigui-ties in Subspace-Based Blind Receiver for Mimo Chan-nels.” Thirty-Sixth Asilomar Conference on Signals,Systems & Computers, Pacific Grove California USA,November 3-6, 2002. pp. 589-593.

[30] Enescu, Mihai, Koivunen, Visa “On the estimationof correlated noise statistics in a class of state-spacemodels.” Thirty-seventh Asilomar Conference on Sig-nals, Systems and Computers, CA USA, November 9-12 2003.

[31] Koivunen, Visa, Enescu, Mihai, Sirbu, Marius “Blindand Semiblind Channel Estimation.” In: Nonlinear Sig-nal and Image Processing Theory, Methods, and Appli-cations. CRC PRESS 2004, Boca Raton Florida , pp.257-294.

[32] Enescu, Mihai, Koivunen, Visa “On the estimation ofstate transition matrix and noise statistics in state-spacemodels.” IEEE VTC2002-Vancouver, BC, Canada 24-28 September 2002.

[33] Enescu, Mihai, Koivunen, Visa “Kalman smoothingbased channel estimation for space-time block cod-ing.” European Conference on Signal Processing EU-SIPCO2002, Toulouse France, 3-6 September 2002.

[34] Enescu, Mihai, Sirbu, Marius, Koivunen, Visa “Adap-tive Equalization of Time-Varying MIMO Channels.”Signal Processing, revised version still under review.

[35] Enescu, Mihai, Zhang,Yinglu, Kassam, S.A.,Koivunen, Visa “Recursive estimator for Blind MIMOequalization via BSS and fractional sampling.” 2001IEEE Third Workshop on Signal Processing Advancesin Wireless Communications, SPAWC’01, Taoyuan,Taiwan, R.O.C, March 20-23, 2001. pp. 94-97.

[36] Enescu, Mihai “Adaptive Methods for Blind Equaliza-tion and Signal Separation in MIMO Systems.” HUTdoctoral thesis, Espoo: 2002. pp. 96 (Signal ProcessingLaboratory Report 36).

[37] Roman, Timo, Enescu, Mihai, Koivunen, Visa, “Time-Domain Method for Tracking Dispersive Channels inOFDM Systems.” IEEE Vehicular Technology Confer-ence, VTC 03 Spring, Jeju, Korea, 2003..

[38] A. Hyvärinen, R. Cristescu, E. Oja, “A fast algorithmfor estimating overcomplete ICA basis for image win-dows”,Proc. International Joint Conference on NeuralNetworks, pp. 894–899, 1999.

78


Concurrent Design and Fabrication of

Integrated Module Boards

Jorma Kivilahti

Professor

Lab. of Electronics Production Technology

Helsinki University of Technology

P.O. Box 3000, FIN-02015 HUT, Finland

[email protected]

Ilkka Suni

Research Manager

Microelectronics

VTT Technical Research Centre of Finland

P.O.Box 1208 FIN-02044 VTT Finland

[email protected]

ABSTRACT

The project had two major objectives. The first objective

of the research project was to interconnect reliably bare

Cu-metallised chips and integrated passive components

into multilayer flexible and rigid substrates with the IMB

technology. This required comprehensive design and

modelling of electrical, thermal and mechanical performance as well as the interfacial compatibility - all

at the chip and the module board levels. Consequently,

the second objective was to develop a new concurrent

design and manufacturing approach for producing

reliable solderless electronic products by combining

electrical, thermal and mechanical design and simulation

tools and aspects into a one coherent approach. Both

objectives were achieved in the project.

I. INTRODUCTION

Increasing employment of portable electronics will

require the most advanced materials and manufacturing

technologies; higher performance and reliability at lower

cost are becoming ever more crucial. However, while

striving for higher performance we will encounter also

more fundamental manufacturing and reliability

challenges, which require concurrent designing and

simulation of electrical, thermal, and mechanical

behaviour of multilayer structures used in future portable

electronics. This concerns, in particular, very high-density

interconnection and packaging technologies like the IMB

technology being originally developed at Helsinki

University of Technology [1]. It enables solderless

integration of embedded IC's and passives. Even though

our approach focuses on IMB technology, but it is by no

means limited to it.

Increasing (I/O) densities with finer feature sizes on

chip level are unavoidably related to thinner

metallisations, so there is a growing risk that the

metallisations of the ULSI technology are influenced

detrimentally by high current densities (electromigration)

or by excessive chemical reactions between adjacent

materials or by moisture and oxygen from the operational

environment (corrosion). Similarly, the solder volumes

are continuously decreasing on board level (PWBs), and

therefore electromigration as well as thermomigration in

solder joints is becoming a more serious concern [Fig. 1].

In addition to higher current densities the homologous

temperatures of solder interconenctions are low, and

therefore relatively fast diffusion via vacancies occurs

even at ambient temperatures. Besides, in small solder

Lithography

BGA

"fine-pitch"

(FC)2

Flip Chip

1

Inte

rco

nn

ecti

on

vo

lum

e[m

m3]

Conductor width or pad size [ m]

10-6

10-3

VLSIMSI

"ultra fine-pitch"

[10 m]3

Paste-printing

IMB

10102103

THT

SMT

CSP

10-4

10-5

10-2

10-1

[50 m]3

[100 m]3

Flip Chip

FCHD Boards

Build-upcontacts

DIL

QFB

FR4

flexible or rigid

Technology transition

FC Pac

ka

gin

gd

en

sit

y

Conductive

polymer pastes,

films, TFB, etc.

"Green Electronics"

SL

I

Cu-on-Cu contacts

Defect rate

No

volu

me

Fig. 1. Impact of miniaturisation on interconnection and

packaging technology.

79


joints brittle intermetallic reaction products take already a

marked volume fraction of the joints in high density bare

chip assemblies (e.g. area array Flip Chip, FC2)

diminishing their reliability. Due to this small volume

effect (SVE), the electromigration and increasing stresses

experienced by ever smaller solder interconnections the

reliability at the component and board level is expected to

become a greater concern than on a chip level.

In order to manufacture reliably and cost-effectively

highly functional integrated module structures, realistic

design and simulation methods will become

indispensable. Electrical, thermal, mechanical and even

chemical properties of such multimaterial structures must

be known thoroughly - ultimately due to the fact that

dissimilar materials of diminutive amounts are used in

contact with each other. It is most essential that design

and simulation tools are used collaborately by developing

so-called Concurrent Design Approach. Therefore, the

development of such an approach was selected as one of

the main targets of the project.

II. CONCURRENT DESIGN AND SIMULATION

In order to develop the above-mentioned concurrent

modelling approach all the subsections were first

considered separately and after that combined together as

follows.

Electrical design and modelling

The IMB or an equivalent technology requires new

procedures for designing and manufacturing of ultra-high

density boards or modules. A test board for Power

Amplifier (PA) working at 2.45 GHz was designed.

Simulations were realized for specific applications,

geometries and positions on the board. Using CAM board

designer together with HP-HFSS (High Speed Structure

Simulator) for component modelling and simulation and

HP ADS (Advanced Design Systems) for electrical

parameters calculations, the board design and analyses

was completed. Input and output network and digital

control for the PA were designed and modelled using the

IMB embedded passive components. The design was done

also for surface mount technology (SMT) based board.

Both designs are shown in Figs.2 and 3. Then the control

of characteristic impedance and input-output matching

circuits were analysed to ensure good signal integrity.

Besides the PA test board electrical modelling of

IMB interconnections were modelled and calculated for

Ku and K band. A comparison with the flip chip assembly

was then carried out. The electrical parameters of the

interconnections were extracted and electrical

performances analysed. Furthermore, considering the

signal integrity in high-speed digital applications the

electrical parameters of the embedded resistors were

analysed. The concurrent electrical and thermal analysis

was then performed for the best component geometry – by

considering also the manufacturing capabilities.

Fig. 2. IMB board design

Fig. 3. SMT board design.

Thermal design and modelling

The thermal energy produced by different

components and its effect on the components environment

must be taken into account by initiating the thermal

modelling already at the beginning of the electrical design

of a product.

The thermal modelling for both SMT and IMB test

board designs was carried out with the CFD

(Computational Fluid Dynamics) technique in

FLOTHERM (Fig. 4). The parameters obtained in the

electrical design were used as input data for the

calculation of thermal power of different components.

Details of the board layout in the vicinity of the chip,

including location of vias and other passive components,

are also obtained from the electrical design. The natural

convection of surrounding air is simulated and the

contribution of radiation is included. The final results of

both structures (IMB and SMT) are compared with each

other in the terms of chip temperature.

80


Fig. 4. Thermal simulation of the power amplifier

designed in EPT-laboratory during operation (a) SMT and

(b) IMB

In addition, the test board with an active component,

thermal modelling of embedded resistors used in IMB

applications are also performed by using ANSYS (Fig. 5).

Different parameters of resistors including resistance,

sheet resistivity and line width were examined and the

optimal configuration was determined by combining the

results of both the thermal and electrical modelling. In

order to enable concurrent multiphysical modelling,

considerable amount of work was needed [with MATLAB

program] for converting the results in FLOTHERM into

the format, which the finite element analysis program

ANSYS could use so that more subtle thermal modelling

in test board level and subsequent mechanical modelling

become possible.

Mechanical modelling

As the electrical solder interconnections are the only

mechanical connection between SMT components and the

board their reliability is very important - in addition to

their electrical performance. By knowing the temperature

distribution of the assembly and its changes during

operation the strains and stresses induced by the thermal

expansion of the dissimilar materials in the assembly can

be calculated with the Finite Element Method (FEM).

Fig. 5. Transferred temperature field in ANSYS from

FLOTHERM for SMT

The temperature distributions calculated by

FLOTHERM and ANSYS (Figs. 4 and 5) were input to

the mechanical FE models of the studied structures and

the stress and strain (Figs. 6 and 7) distributions were

calculated with ANSYS.

Fig. 6. Strain distribution in SMT assembly induced by

thermal power shown in Figs. 4 and 5.

a)

b)

81


Fig. 7. Strain distribution in IMB assembly induced by

thermal power shown in Figs. 4 and 5.

The interconnections where the stresses are highest

are most prone to failure, but the time to the failure

depends on the whole loading history and the

interconnection geometry and, naturally, on the materials

used. Therefore it is very difficult task to predict the time

to failure, and more work is needed to solve this very

important issue. However, the calculated stress

distributions provide means to analyse the critical parts in

the designed layout.

Physicochemical modelling

In addition to the above-mentioned modelling

approaches the physicochemical compatibility evaluation

is important part of the over-all modelling of integrated

component assemblies or modules. This is due to the fact

that intermaterial reactions during the fabrication as well

as in the use of the modules may generate reaction

products, which tend to reduce the cohesion between thin

material layers or even deteriorate the functions of the

components. Especially the adhesion between various

new interfaces between materials used in the IMB

structure was found out to be crucial. Thermodynamic

calculations were carried out in order to find out the

stabilities of the different multimaterial interfaces found

in the module structures. In addition, surface energy

measurements and calculations were executed to

understand the effect of different surface treatment

techniques to the adhesion between different polymers

and metals in IMB structures.

III. EXPERIMENTAL

The first objective of the research project - to

interconnect reliably bare copper metallised chips with

multilayer flexible and rigid substrates with integrated

passive components utilising the IMB technology -

required extensive experimental work to be carried out.

The development of different component manufacturing

technologies – both for Si-chips and for PWB substrates -

was conducted individually as well as jointly by HUT and

VTT. The investigation of diffusion barriers for Cu

metallisation as carried out in the previous Telectronics-

project "Integration of Microcircuits with Multilayer

Substrates Using Advanced Thin-Film Processing" was

also continued. In addition to the above mentioned

activities the adhesion studies between Cu and polymers

used in the IMB technology were incorporated into the

present project. This was done owing to the observation

that the adhesion between dissimilar material layers used

in the modules was becoming one of the major reliability

concerns.

Investigation and development of components for

IMB modules was based on extensive materials research

utilising scanning (SEM) and transmission electron

microscopy (TEM), Rutherford backscattering (RBS),

atomic force microscopy (AFM) and x-ray diffraction

(XRD). Although the focus in developing components

was in utilizing them in the IMB modules, the

components can be adapted universally also to other thin

film integration technologies.

The development of the concurrent modelling and

simulation tool also required a lot of experimental work.

After designing and modelling the structures were

fabricated and analysed in order to verify experimentally

the models used. Further, because of the compliance

problems between the different modelling tools,

additional programming was required to convert the data

from one program to another.


The objectives of the project were attained very well.

The project gave new insight and significant fundamental

results on the interactions between different material

layers used in the IMB modules. Furthermore, the project

produced valuable practical results concerning the

fabrication of integrated passives and their utilisation in

the module board technology and in other analogous

technologies. Most important results of the project are

considered to be the new knowledge and experience

achieved about the concurrent design and modelling of the

electronic circuits. In this project we were able to develop

a simulation protocol that included electrical, thermal,

mechanical and physicochemical tools and to combine

them into one unified approach. Based solely on the

results and experience achieved in this project a new

design and simulation project funded by the National

Technology Agency and Finnish Electronics Industry has

been initiated in the beginning of this year.

82


The first objective of the present work was to

interconnect reliably bare copper metallised chips with

multilayer flexible and rigid substrates with integrated

passive components utilising the IMB technology. This in

turn required the investigation of various interfaces found

inside the module structure. The research on diffusion

barriers carried out in the Telectronics I program was

continued also herein. The results verified that Ta-based

barriers offer a very feasible solution to the diffusion

barrier problem. The crucial effect of oxygen on the

reactions in all the investigated Ta-based metallization

schemes was demonstrated and the thermodynamic basis

for understanding the origins of this behaviour was given.

As the research project advanced it became more and

more clear that the adhesion of Cu to different polymers

used in the IMB structures was one of the key issues in

ensuring reliability of the module board structures.

Therefore, extensive research was carried out on the ways

to improve the adhesion in the module structures. Thus,

the work performed in this project has supported

markedly also the development of the IMB technology,

which is being implemented into volume production by

the Imbera Electronics established jointly by the Elcoteq

Networks and Aspocomp Group. Furthermore, as it is

expected that in near future photonics is becoming

increasingly important field of scientific and technological

activity, and because IMB-type technologies can be

utilised in the fabrication of optical modules, some

considerations concerning the optical properties and

optical applications of the modules were taken. This in

turn led to the attempts to improve some of the properties

of epoxy-based polymers used in the IMB-process for

optical interconnections.

Full range of components is needed in the IMB

modules, and therefore new processes using copper

metallisation were investigated. For example, we

developed a process to fabricate high dielectric constant

tantalum pentoxide thin films for integrated capacitors

(Fig. 8).

Insulating substrateTiW-1

Cu-2TiW-2

TaCu-1

Ta O2 5

Fig. 8. Schematic sketch of the Ta2O5 thin film capacitor

structure investigated.

The films obtained showed a stoichiometric orthorhombic

-Ta2O5 phase at an O2-Ar sputtering gas flow ratio of 20

%. The processed thin film tantalum pentoxide MIM

(Metal Insulator Metal) capacitors with copper electrodes

showed good potential for further improvement. Also thin

film resistors and diffusion barriers have been developed,

fabricated and investigated.

The test structures shown in Figs. 2 and 3 were

fabricated by utilizing both the IMB and SMT

technologies. The corresponding structures a re shown in

Figs. 9 and 10. Some problems were encountered during

the manufacturing of the IMB structure and it was not

possible to finalize the assembly in time. This was partly

owing to the reasons already discussed above, i.e.

adhesion problems and related subjects. In addition, the

fabrication process itself revealed some reliability

concerns. However, the fabrication is still continuing and

will be completed in April 2004.

Fig. 9. X-ray picture from the fabricated IMB structure

showing the place of the chip, one integrated resistor and

two integrated inductors.

Fig. 10. SMT board after assembly. The chip can be seen

in the middle and is surrounded by passive components.

83


The second object of the research project was to

develop new concurrent approach to manufacture reliable

solderless electronic products by combining electrical,

thermal and mechanical design and simulation tools and

aspects into a one coherent approach. To achieve this goal

took much more time that was initially expected mainly

due to the compliance problems between different

simulation programs.

Therefore, a program code had to be developed in the

project to enable the transfer of simulation data from one

program to another. After that the full simulation loop i.e.

electrical, thermal and mechanical was finalised. The

results from the concurrent simulations indicated that

apparently, for the system fabricated with IMB

technology, the stresses produced were much higher than

those of SMT, especially in the Cu conductor layer and in

the die itself. This can degrade the system performance of

the circuit fabricated with the IMB process. However, for

passive component on top of board, the stresses in the

IMB assembly are smaller than those of SMT, which

means that these passive components, such as capacitors,

can be expected to show better reliability in the IMB case.

The source of this behaviour can be seen from Fig. 2 a)

and b) where distribution of thermal energy is shown. It is

obvious that in SMT case the chip is not as hot as in the

IMB case. On the contrary the surface mount passives are

hotter in SMT than in IMB assembly. The results from the

above simulations were also combined with

physicochemical considerations to find out how different

materials in the modelled structure would behave.

In order to verify the models used two sets of test

structures were fabricated. The one was an IMB-module

board and the other was the SMT-based assembly. The

performance of the test circuits was then compared with

each other with the modelling and with experimental tests.

The results of the project are currently being utilized also

in a new European Lead-Free Network (ELFNET)

project. Without any doubt the research in this field will

continue in the future and is expected to become even

more intensive.

V. PUBLICATIONS

[1] A. Kujala, R. Tuominen, J. K. Kivilahti, ”Solderless

interconnection and packaging technique for embedded

active components”, 14 June 1999; In 49th Electronic

Component Technology Conference: San Diego, USA

A. PEER-REVIEWED PAPERS IN THIS PROJECT

[2] T. Laurila, J. Molarius and J.K. Kivilahti, ” Interfacial

Reactions in the Si/TaC/Cu system”, Microelectronic

Engineering, in press

[3] T. Riekkinen and J. Molarius, ” Reactively sputtered

tantalum pentoxide thin films for integrated capacitors”,

Microelectronic Engineering, Vol. 70 (2003), 392 - 397

[4] T. Laurila and J. Molarius, ” Reactive phase formation

in thin film metal/metal and metal/silicon diffusion

couples”, Critical Reviews in Solid State and Materials

Science Vol. 28 (2003) No: 3, 185 – 230

[5] J. Ge, M. Turunen, and J K. Kivilahti, “Surface

modification of a liquid crystalline polymer for copper

metallisation”, Journal of Polymer Science: Part B:

Polymer Physics, 41, (2003), 623-636.

[6] J. Ge, M. Turunen, M. Kusevic, and J. K. Kivilahti,

”Effects of surface treatments on adhesion of copper to a

hybrid polymer material”, Journal of Materials Research,

18, (2003), 2697-2707.

[7] J. Ge, M. Turunen, and J. K. Kivilahti, ”Surface

modification and characterisation of photodefinable

epoxy/copper systems”, Thin Solid Films, 440 (1-2),

(2003), 198-207.

[8] M. Turunen, P. Marjamäki, M. Paajanen, J. Lahtinen,

and J. K. Kivilahti, ”Pull-off test in the assessment of

adhesion at printed wiring board metallisation/epoxy

interface”, Microelectronics Reliability, accepted for

publication 2003, in press.

[9] M. Turunen, T. Laurila, and J. K. Kivilahti,

”Evaluation of the surface free energy of spin-coated

photodefinable epoxy”, Journal of Polymer Science: Part

B: Polymer Physics, 40, (2002), 2137-2149.

[10] T. Laurila, K. Zeng, J.K. Kivilahti, J. Molarius, and I.

Suni, ” Amorphous layer formation at the TaC/Cu

interface in the Si/TaC/Cu metallization system”,

Applied Physics Letters. Vol. 80 (2002), 938 - 940


Suni, “ Effect of oxygen on the reactions in Si/Ta/Cu and

Si/TaC/Cu systems”, Microelectronic Engineering, Vol.

64 (2002) No: 1 - 4, 279 - 287

[12] T. Riekkinen, J. Molarius, T. Laurila, A. Nurmela, I.

Suni, and J.K. Kivilahti, ” Reactive sputter deposition and

properties of TaxN thin films”, Microelectronic

Engineering. Vol. 64 (2002) , 289 -297


Suni, “TaC as a diffusion barrier between Si and Cu”,

Journal of Applied Physics. Vol. 91 (2002), 5391 - 5399

84



Suni, “Tantalum carbide and nitride diffusion barriers for

Cu metallization” , Microelectronic Engineering. Vol. 60

(2002) No: 1-2, 71 - 80


Suni, “Effect of Oxygen on the reactions in the Si/Ta/Cu

metallization system”, Journal of Materials Research.

Vol. 16 (2001) No: 10, 2929 – 2946.

[16] T. Waris, M. Turunen, T. Laurila, and J.K. Kivilahti

"Evaluation of electrolessly deposited NiP integral

resistors on flexible polyimide substrate",

Microelectronics Reliability 2004 (submitted).

[17] D. Burlacu, T. Waris, J. Kivilahti, “High frequency

characterization of IMB technique” (to be submitted

2004).

[18] D. Burlacu, H. Yu, J. Kivilahti, “Concurrent

Electrical-Thermal Design of Embedded Resistors for

High Frequency Applications”(to be submitted 2004).

[19] H.Yu, D.Burlacu and J.K.Kivilahti, “Concurrent

Thermal and Electrical Design of Embedded Resistors for

High Density Boards”(to be submitted 2004).


Thermal and Electrical Design of 2.45 Power Amplifier

using SMT and IMB techniques”(to be submitted 2004).

B. CONFERENCE PAPERS

[21] T. Laurila and J.K. Kivilahti, “Analyses of interfacial

reactions at different levels of interconnection” invited

presentation, in Symposium C, 2004 E-MRS Spring

Meeting, 24-28 May, 2004, Strasbourg, France.


Thermal and Electrical Analysis of Integral Resistors”,

IMAPS Nordic, Stockholm 2002, 71-82

85


Advanced Radio Channel Identification and Estimation (ARCHIE)

Timo Laakso (Project leader)

Visa Koivunen

Signal Processing Laboratory

PO Box 3000, 02015 HUT

[email protected], [email protected]

Aarne Mämmelä

VTT Electronics

P.O. Box 1100, 90571 Oulu

[email protected]

ABSTRACT

This report reviews the research work of the ARCHIE

project done at the Helsinki University of Technology and VTT Electronics. The goal of the project was to develop

advanced channel identification and equalization methods

for future mobile communication systems and wireless local area networks, and their future extensions.

The work can be divided into three parts, namely

system design, signal design and receiver design. One important result was a novel classification of receiver

algorithms. In addition, several original papers on

iterative equalization and decoding algorithms were published in best journals and conferences.

I. INTRODUCTION

This paper includes a summary of the research work

done in the ARCHIE project. The goal of the project was

to develop advanced channel identification and

equalization methods for future mobile communication

systems and wireless local area networks, and their future

extensions.

A general block diagram of a modern system based on

serially concatenated codes and iterative processing is

shown in Fig. 1. The research covers mainly the digital

baseband processing algorithms of the physical layer of

the Open Systems Interconnection (OSI) architecture

model.

I. ACTIVITIES

The work can be divided into three parts, namely

system design, signal design and receiver design. Each of

these parts will be described below.

Outer

channel

coder

Inner

channel

coderModulatorI

Outer

channel

decoder

Inner

channeldecoder

DemodulatorD

I

Channel/

SNR

estimatorSynchron.

Soft decisions

Text, voice,music, video

Radio channel - path loss

- shadowing

- multipath fading

Controller

Iterative processing

RF/IF

RF/IF

Feedback channel

Parameters

ParametersSNR estimate

Channel estimate

Text, voice,

music, video

Figure 1 – A block diagram of a general telecommunication link

(I = interleaver, D = deinterleaver, RF = radio frequency, IF =

intermediate frequency, SNR = signal-to-noise ratio).

a) System design

Two papers were published about system design. The

cellular channel models were summarized in [1]. Such

models are needed in signal and receiver design. The book

chapter includes a review of the statistics, measurement

and simulation of time-variant channel in microcells and

macrocells. The chapter also includes recent trends and a

short bibliography of the most important references.

A taxonomy of algorithms in digital receivers was

presented in [2], including data, channel and joint

estimators, see Fig. 1. We believe that the classification in

this form is novel. The classification clearly shows the

theoretical background, relationships and symmetry of

algorithms. A longer review paper is in preparation based

on this idea.

The receiver is seen as an elaborate estimator, whose

primary purpose is to estimate or ”detect” the data. In

communications, the impulse response of the linear

channel is normally seen as a nuisance parameter set.

87


Data and channel

estimators

Data estimation (DE)Channel estimation

(CE)

Joint data and

channel estimation

(JDCE)- nonrandom parameters

(joint ML)

- random parameters (joint

MAP)

Estimator-correlator(MAP)

- implicit channel estimation

Correlator- nonrandom data (ML)

- random data (MAP)

Decision

directed (DD)

estimator

Data aided (DA)- nonrandom channel (ML,

LS)

- random channel (MMSE)

Non data aided (NDA)

or blind (MAP)- implicit data estimation

Random channel removed by averaging

Channel assumed to be known

Noncoherent

detector

Energy

detector

Coherent

detector

Phase

reference

Data assumed to be known

Random data removed by averaging

Symmetry

Symmetry

Matched filter

estimator

Differential

detector

Figure 2 – Classification of data and channel estimators.

The optimal receiver is defined to be a maximum a

posteriori probability (MAP) detector where the channel

is either assumed to be perfectly known or, if statistically

known, be removed by averaging. The corresponding

optimal receivers are the correlator and estimator-

correlator. On the other hand, in channel estimation data

are assumed to be known or removed by averaging.

Finally, joint estimators, which are generally optimal data

detectors only asymptotically, can be defined.

All the estimators are initially defined to be of the

block-type, but they can be approximated with recursive

versions. The estimators are based on some statistical

knowledge on the channel, for example on the first- or

second-order statistics of the impulse response and noise.

Adaptive estimators do not necessarily rely on this a priori

knowledge, but they are approximations of the optimal

estimators and explicitly or implicitly estimate also the

statistics. The adaptive algorithms are separately defined

for unknown slowly and fast fading channels.

b) Signal design

Two papers were published on signal design. Optimal

receivers cannot be defined unless the transmitted signal

and the statistics of the channel are first defined.

In [3] we analyzed the effect of time and frequency

domain windowing, or weighting, of the transmitted

signal for least squares (LS) and minimum mean-square

error (MMSE) estimators when the channel is time-

variant. We considered the estimation error for different

windows and we found that the windows can be selected

independently. We explained the performance of the

estimators with the help of the radar ambiguity function of

the transmitted signal including windowing.

Pilot symbol assisted modulation and an MMSE

channel predictor were used to employ feedback MMSE

power control over a frequency nonselective slow

Rayleigh fading channel [4]. Lag error was noticed to

cause severe performance degradation, even when the

channel is very slowly fading. In order to decrease the lag

error, the number of estimator coefficients was found to

become quite large.

c) Receiver design

Several papers were published on receiver design. The

basic principle in these studies was to derive receiver

algorithms, which would be nearly optimal in

performance with reduced complexity compared to the

optimal solutions.

In [5, 6, 7], channel estimation based on the

expectation-maximisation (EM) algorithm was

considered. Then, adaptive Bayesian and expectation

maximisation (EM) based soft decision directed (SDD)

channel estimators were derived and studied in [6, 8, 9,

10]. They approximate the maximum a posteriori

probability (MAP) symbol detection in frequency-

selective fading channels and they are applied to iterative

turbo-processing receivers in a computationally attractive

way [8, 11, 12]. Usually the second order statistics, i.e.,

the Doppler power spectrum and more generally the

scattering function of the channel, are assumed to be

known in the receiver. The EM-based estimators can be

used to estimate the autoregressive moving average

(ARMA) parameters of the spectrum [6].

In [11, 12], variational inference and estimation

approach was used to derive low-complexity turbo

receivers for single-input single-output and multiple-input

multiple-output (MIMO) systems. Simulation results

showed that the presented receivers achieve practically

the same performance as the optimal MAP turbo

receivers, while providing significant computational

savings.

The application of the Berrou soft output Viterbi

algorithm (SOVA) to implement an iterative turbo

decoder was considered in [13]. The Berrou SOVA

decoder is conceptually different from the conventional

turbo decoders. The performance was found to be

competitive with the traditional algorithms although the

complexity is relatively low.

Joint channel and delay estimation in multiantenna

CDMA receivers

In uplink (mobile-to-base station) transmission of DS-

CDMA networks, the users signals are arriving to the

base-station (BS) with different delays. Therefore, the

system is asynchronous. The channel impulse response

(CIR) of each user is different also. The asynchronous

system has the advantage that the need for network

signaling is reduced. On the other hand, the

propagation delays of each user have to be estimated

88


by the BS receiver. Hence the quality of the delay

estimation has a significant impact on the overall receiver

performance. This work has produced a good number of

publications and doctoral thesis of Marius Sirbu.

In long-code system, the delay spread of the channel

introduces inter-chip-interference (ICI) and the

channels are always time varying. Multiple antennas are

employed at the receiver. Consequently the performance

is improved by taking advantage of the spatial diversity

as well as the increased SNR.

In this work we developed novel delay and channel

estimation methods [15-23]. The CIR and the propagation

delays are estimated jointly. The method lends itself to an

adaptive implementations since adaptive update rule may

be used. The method is robust and the performance is

significantly improved over existing methods. Moreover

the design is simple since no user-specified threshold

values are needed and the performance remains reliable

even for non-minimum phase channels. The method is

called the delay profile method and it determines the

delay by looking for a certain pattern in the matrix

containing both the CIR and delay information. Low-

order AR-model is used to model the channel dynamics.

In order to study symbol error rate performance, a

MMSE multi-user equalizer is found based on the

estimated channel matrix. The simulation results

demonstrate the reliable performance of at different SNR

levels, in the presence of near--far effects and in different

user scenarios. The method is flexible in a sense that it

may be used both in short-code and long-code DS-CDMA

systems.

These methods are applicable to uplink CDMA systems

such as UMTS as well as satellite navigation systems such

as GPS and Galileo. Significant improvement in

navigation accuracy may be achieved.

Adaptive Filtering Algorithms

Development of efficient adaptive algorithms for

channel estimation and equalization is a key part of

modern digital receiver design. New receiver structures

based on the concept of Set Membership Filtering (update

estimate only when needed) and data reuse (utilize same

input several times to speed up convergence) were

developed [24-33]. Part of this work was done in

cooperation with prof. Paulo Diniz’ group in the Federal

University of Rio de Janeiro, Brazil.

Data Selective Adaptive Filtering Algorithms

This research investigated new data selective adaptive

filtering algorithms using the framework of set-

membership filtering (SMF). These algorithms combine a

bounded error specification on the adaptive filter with the

concept of data reusing. The resulting algorithms have

low average computational complexity because

coefficient update is not performed each iteration. The

adaptation algorithms can be adjusted to achieve a desired

computational complexity by allowing a variable number

of data-reuses for the filter update.

Analysis of Partial-Update Adaptive Filters

This research analyzed partial-update normalized adaptive

filters. Partial-update adaptive filtering is a technique

suitable for applications where the order of the adaptive

filter is so high that it may impair even the

implementation of low computational complexity

algorithms, such as the NLMS algorithm. Partial-update

adaptive filters reduce the algorithm complexity by

properly decreasing the number of filter coefficients that

is updated each iteration so that the filter order may be

kept fixed. Order statistics are used to analyze the mean-

squared error of the adaptive filter output.


Two Dr.Tech. students (Stefan Werner and Marius

Sirbu) got their degrees within the project.

Some contract research and development projects

were started during the project with the industry. In the

European WINNER project we are taking part in the

systems engineering workpackage, which was possible

due to our systematic work. WINNER includes some 40

partners, mainly from the European Union and it is led by

the industrial partners, for example Siemens and Nokia.

We have given several postgraduate courses at the

Helsinki University of Technology and University of

Oulu. A number of postgraduate students from the

industry have taken part in the lectures. In addition, three

one-day short courses on adaptive receiver algorithms

have been given to the industry.

PUBLICATIONS

[1] Mämmelä, A., and Järvensivu, P., 2003, “Cellular

communications channels”, Wiley Encyclopedia of

Telecommunications, vol. 1, J. G. Proakis, Ed., John

Wiley & Sons, New York.

[2] Mämmelä, A., Polydoros, A., and Järvensivu, P.,

2002, “Data and channel estimators: A systematic

classification” (invited plenary paper), Proceedings

of the X National Symposium of Radio Science, pp.

13-25.

[3] Järvensivu, P., Matinmikko, M., and Mämmelä, A.,

2002, “Signal design for LS and MMSE channel

estimators”, Proceedings of the IEEE International

Symposium on Personal, Indoor and Mobile Radio

Communications, pp. 956-960.

[4] Saarinen, I., Mämmelä, A., Järvensivu, P., and

Ruotsalainen, K., 2001, “Power control in feedback

communications over a fading channel”, IEEE

89


Transactions on Vehicular Technology, Vol. 50, No.

5, pp. 1231-1239.

[5] Nissilä, M., Pasupathy, S., and Mämmelä, A., 2001,

“An EM approach to carrier phase recovery in

AWGN channel”, Proceedings of the IEEE

International Conference on Communications, pp.

2199-2203.

[6] Nissilä, M., and Pasupathy, S., 2003, “EM-based

estimators for ARMA parameters of multipath

fading channels”, Proceedings of the IEEE

International Symposium on Signal Processing and

Information Technology.

[7] Nissilä, M., and Pasupathy, S., 2004, “Joint

estimation of frequency offset and fading rate in

multipath fading channel using autoregressive

channel modeling”, IEEE Vehicular Technology

Conference, accepted.

[8] Nissilä, M., and Pasupathy, S., 2003, “Adaptive

Bayesian and EM-based detectors for frequency-

selective fading channels”, IEEE Transactions on

Communications, Vol. 51, No. 8, pp. 1325-1336.

[9] Nissilä, M., and Pasupathy, S., 2002, “Adaptive

Baum-Welch algorithms for frequency-selective

fading channels”, Proceedings of the IEEE

International Conference on Communications, pp.

79-83.

[10] Nissilä, M. and Pasupathy, S., 2002, “Bayesian EM-

based demodulators for frequency-selective fading

channels”, Proceedings of the IEEE Global

Telecommunications Conference, pp. 1147-1151.

[11] Nissilä, M., and Pasupathy, S., 2004, “Reduced-

complexity turbo receivers for single and multi-

antenna systems via variational inference in factor

graphs”, IEEE International Conference on

Communications, accepted.

[12] Nissilä, M., and Pasupathy, S., 2004, “Low-

complexity turbo receivers for multiple antenna

space-time coded systems via variational inference”,

IEEE Vehicular Technology Conference, accepted.

[13] Nordman, R., 2003, “Application of the Berrou

SOVA algorithm in decoding of a turbo code”,

European Transactions on Telecommunications, Vol.

14, No. 3, pp. 245-254.

[15] Sirbu, Marius; Koivunen, Visa, Multichannel

Estimation and Equalization Algorithm for

Asynchronous Uplink

DS/CDMA*. Wireless Personal Communications,

2003. Nro 26, pp.33-52.

[16] Sirbu, M., Mannerkoski, J., Zhang, Y. & Koivunen,

V. Feasibility of fractionally spaced blind

equalization with GMSK modulated signals. 15th

European Conference on Circuit Theory and Design

ECCTD'01, Espoo, Finland, 28-31 August 2001. pp.

45-48.

[17] Sirbu, Marius; Enescu, Mihai; Koivunen, Visa, Real-

Time Semi-Blind Equalization of Time Varying

Channels. IEEE-EURASIP Workshop on Nonlinear

Signal and Image Processing, Baltimore, MD USA,

June 3-6, 2001.

[18] Sirbu, Marius; Mannerkoski, Jukka; Zhang, Yinglu;

Koivunen, Visa, On the Feasibility of Blind

Equalization for EDGE Systems. 2001 IEEE Third

Workshop on Signal Processing Advances in

Wireless Communications, SPAWC'01, Taoyuan,

Taiwan, R.O.C, March 20-23, 2001. pp. 90-93.

[19] Sirbu, Marius, Enescu, Mihai, Koivunen, Visa

Estimating Noise Statistics in Adaptive Semiblind

Equalization. 35th Asilomar Conference on Signals,

Systems and Computers, Pacific Grove, CA USA,

November 4-9. 2001.

[20] Sirbu, Marius; Koivunen, Visa, Channel estimation

and tracking in uplink asynchronous DS/CDMA

using multiple antennas. 14th International

Conference on Digital Signal Processing DSP2002,

Santorini Greece, July 2002. pp.635-638.

[21] Sirbu, Marius; Koivunen, Visa, Propagation delay

estimation in asynchronous DS/CDMA using

multiple antennas. XI European Signal Processing

Conference EUSIPCO 2002, Toulouse France 3-6

September 2002.

[22] Enescu, Mihai; Sirbu, Marius; Koivunen, Visa,

Resursive Estimation of Noise Statistics in Kalman

Filter Based MIMO Equalization. XXVIIth General

Assembly of the International Union of Radio

Science, Maastricht the Netherlands, 17-24 August

2002.

[23] Sirbu, Marius; Koivunen, Visa, One-Step

Refinement Method for Joint Channel Estimation

and Timing Acquisition in OFDM Transmission. 1st

International Workshop on Signal Processing for

Wireless Communications 2003, London UK, May

19-20, 2003.

[24] S. Werner, M. L. R. Campos , J. A. Apolinário Jr.,

"On the equivalence of RLS implementations of

LCMV and GSC processors," IEEE Signal Processing Letters, vol. 10, pp. 356-359, December

2003.

[25] Paulo S. R. Diniz, Stefan Werner, "Set-membership

binormalized data-reusing LMS algorithms," IEEE

Transaction on Signal Processing, vol. 51, pp. 124-

134, January 2003.

90


[26] S. Werner, M. L. R. de Campos, and P. S. R. Diniz,

"Mean-Squared Analysis of the Partial-Update

NLMS Algorithm,'' Brazilian Telecommunications

Journal - SBT, vol. 18, pp. 77-85, June 2003.


"On an Efficient Implementation of the Multistage

Wiener Filter Through Householder Reflections for

DS-CDMA Interference Suppression," IEEE Global

Telecommunications Conference, GLOBECOM'03,

San Francisco, CA, USA, 2003.

[28] M. L. R. de Campos, S. Werner, J. A. Apolinário Jr.,

"Constrained adaptation algorithms employing

Householder transformation," IEEE Transaction on

Signal Processing, vol. 50, pp. 2187-2195,

September 2002.

[29] S. Werner, P. S. R. Diniz, "Set-membership affine

projection algorithm," IEEE Signal Processing

Letters, vol. 8, pp. 231-235, August 2001.

[30] S. Werner, M. L. R. Campos, P. S. R. Diniz, "Mean-

squared analysis of the partial-update NLMS

algorithm," IEEE International Telecommunication Symposium, ITS’2002, Natal, Brazil, September

2002.


"On the equivalence of the constrained RLS and the

GSC-RLS beamformers," IEEE International

Telecommunication Symposium, ITS’2002, Natal,

Brazil, September 2002.

[32] S. Werner, M. L. R. de Campos, P. S. R. Diniz,

"Partial-update NLMS algorithms with data-

selective updating," IEEE International Conference

on Acoustics, Speech, and Signal Processing,

ICASSP'2002, pp. 1413-1416, Orlando, USA, May

2002.

[33] S. Werner, J. A. Apolinário Jr., M. L. R. Campos,

"Data-selective constrained affine projection

algorithm," IEEE International Conference on

Acoustics, Speech, and Signal Processing,

ICASSP'2001, pp. 3745 -3748, Salt Lake City, Utah,

USA, May 2001.

91


Development of the second generation frequency synthesis techniques J. Kostamovaara

Department of Electrical and Information Engineering, Electronics Laboratory

Electronics Laboratory, PO.Box 4500, FI-90014 UNIVERSITY OF OULU, FINLAND

[email protected]

ABSTRACT

This project has produced knowledge on the

improvement of the performance of frequency synthesizers with emphasis on the development of speed-

up techniques and reduction of the in-band phase noise

and output spur level resulting in the development of a synthesizer chip with state-of-the art performance. In

addition, new synthesizer architectures have been developed and studied. Also a new sampler with

embedded programmable FIR-filtering function has been

developed.

I. INTRODUCTION

Frequency synthesizers are a component of wireless

integrated circuits that face constantly increasing

requirements for low noise and acquisition speed as new

standards evolve. Recently, this has caused frequency

synthesizers to be chosen as a solution for local oscillators

in IC design. The benefits offered by frequency

synthesizers result from the fact that they reduce the

divide ratio N between the VCO and the phase detector.

This reduction in N increases the comparison frequency in

the synthesizer, allowing lower phase noise and higher

loop bandwidths. Higher loop bandwidths, in turn, allow

faster acquisition time and more suppression of noise

contributed by the VCO.

Despite the fact that these synthesizers have been

studied extensively, many of the detailed problems were

not understood. Academic and commercial researchers

have both faced apparently mysterious problems when

trying to build frequency synthesizers. The aim of this

project has been to shed light on these problems,

especially on the problems of high in-band noise and spur

level found typically in published modulators, and

therefore to enable one to develop synthesizers with better

performance than earlier available. This project has

provided a course and several papers that address these

issues. A very good synthesizer was developed to

validate this work.

Despite the increased loop bandwidth offered by

frequency synthesizers, it is often insufficient for some

applications. One of the goals and achievements of this

project has been to show how to significantly improve

acquisition times for both integer-N and fractional-N

synthesizers.

In addition, also totally new architectures were

identified and suggested as described below. The other

architecture relies on an RF/IF sampler, one of the

components in the original proposal, which actually was

seen in the course of the project to become more useful as

a radio receiver component. As a result, its research was

focused more on this purpose than functioning as a

synthesizer component.

II. ACTIVITIES AND RESULTS

a) Speed-up techniques for frequency synthesis

Traditional PLL based synthesizers suffer from

unwanted reference frequency related spurs around the

synthesized carrier frequency. This is the case even with

the nowadays popular fractional-N techniques. Since the

loop acts as a low-pass filter for the spurs, the simple way

to diminish the level of these harmful signal components

is to reduce the loop bandwidth. However, as the

bandwidth of the loop is reduced, the loop is made slower

in the process. This is not acceptable in systems (e.g.

GSM), where telecommunication standards pose limits to

the time it takes for the system to switch channels. Thus,

in traditional PLL based synthesizers, a trade-off must be

made between channel switching speed and the purity of

the output spectrum.

A new speed-up method has been proposed by us,

which allows separate optimization of loop bandwidth and

switching speed [1]. The so-called two-pulses method is

based on using charge pulses to control the dynamics of

the loop. The method can readily be applied to the

fractional-N designs popular nowadays, as was proven in

[2]. The additional circuitry is also well suited for

integration since it only consists of programmable current

sources.

Principle of operation of the two-pulses speed-up method

In the proposed method, the voltage at the input of the

VCO is controlled using out-of-the-loop circuitry which

affects the charge stored in the loop filter during the

frequency hop (see Fig. 1). The response time can be very

short even when the loop bandwidth is small, if the

93


current waveforms i1(t) and i2(t) have the shape shown in

Fig. 1. The current sources in Fig. 1 are only connected to

the loop for a short period of time after a frequency hop is

initiated. Thus, they do not disturb the normal operation

of the loop by adding noise or modifying the transfer

function of the loop. Since the speed-up electronics is

contained in a completely separate piece of circuitry, it

does not necessitate changes in existing loop components

such as the VCO, phase detector and dividers.

Additionally, as the selected double-pulse waveform

keeps the additional circuitry very simple, the method is

also well suited for system level integration.

PD VCO

N

fref fref

R1C2

C1

CS2

i2(t)

CS1

i1(t)

i1(t)

I1

I2 t

t

t

t

Figure 1 – Architecture of the loop and the selected speed-up

current waveform.

The theory presented in [1] was first derived for a

mathematically simpler 2nd order PLL (i.e. CS2 and C2 not

present in the loop). Fig. 2. (a) presents the phase error

e(t) at the output of the phase detector after a 10 MHz

frequency step at the output at t = 0 s. The curve labelled

‘phase error without speed-up’ shows the unforced

behaviour of the loop, which was intentionally made very

slow to increase spurious suppression. As the height of the

1st pulse (I1) increases, the phase error response bends

more and more rapidly downwards. This is exactly what is

intended by the initial current pulse – a very rapid decay

of phase error below zero. The increased rate of phase

error decay is achieved by overdriving the output

frequency of the loop as shown in Fig. 2. (a). Thus, the 1st

current pulse increases the charge of C1 sufficiently to

provide the VCO with an input voltage which produces a

somewhat higher output frequency than the final one.

The 2nd pulse is applied at t = 2 s, and its effect is

also shown in Fig. 2. (a) The pulse has a double purpose.

First, it aligns the output frequency exactly with the final

value, thus zeroing the frequency error at t = 3 s.

Second, to avoid the generation of any frequency errors

after this point, the phase error must also go to zero at

exactly the same moment. Thus, by properly selecting the

magnitudes of the 1st and 2nd pulse – I1 and I2, respectively

– the phase and frequency error are both cancelled out

completely at the end of the 2nd pulse, and any residual

errors will be avoided as shown in Fig. 2. (a).

Qualitatively, this means that the pulses force the areas

inside the shaded boundaries in Fig. 2 (a) equal. As the

sum of the areas (they have different signs) goes to zero,

the phase error, being proportional to the integral of the

frequency error, follows suit.

The system presented above is not directly applicable

when C2 (shown in Fig. 1) is added to the loop filter, thus

producing a 3rd order system typical of many practical RF

synthesizers. However, by adding a second current source

(CS2 in Fig. 1.) to the architecture, delivering a current

i2(t)=i1(t)/10, and by selecting C2=C1/10, a common

choice, the behaviour of the system will approximate that

of a 2nd order system. This particular selection of i2(t)

ensures that the voltage across R1 will be very close to

zero. Thus, i1(t) will only flow to C1, and a proper voltage

change will be produced at the input of the VCO. Fig. 2

(b) shows the resulting phase error and output frequency

error responses for the theoretical 2nd order and the

simulated 3rd order system, when the current levels

derived from the 2nd order theory are directly used in both

cases.

frequency error without speed-up

frequency error with speed-up

phase error without speed-up

phase error with speed-up

-10

-8

-6

-4

-2

0

2

4

0 2 4 6 8 10

time/ s

outp

ut

freq

uen

cy e

rror/

MH

z

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

phas

e er

ror/

rad

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2nd

order mathematical (frequency error)

3rd

order simulation (frequency error)

3rd order measured (frequency error)

2nd order mathematical (phase error)

3rd

order simulation (phase error)

3rd

order measured (phase error)

-1

0

1

2

3

4

5

0 2 4 6 8 10time/ s

outp

ut

freq

uen

cy e

rror/

MH

z

-0,3

-0,2

-0,1

0

0,1

0,2

0,3p

has

e er

ror/

rad

0.1

-0.1

0.3

0.2

-0.2

-0.3

Figure 2 – (a) Phase error and output frequency error after a step

change in input frequency and (b) phase error and output

frequency error of theoretical 2nd order, simulated 3rd order and

measured 3rd order loop.

94


Measurement results

A two-pulses speed-up system was built around an 800

MHz PLL ASIC designed in the project. Fig. 2 (b) shows

the measured response of the example 3rd order loop. As

expected, the measurements indicate that the presented

ideas can be applied to real-life synthesizers, with an

example reduction in frequency hop time to 1/7 of its

original value. In practice, however, phase and frequency

errors can be cancelled completely only by fine-tuning the

pulse levels. As a result, the usability of the two-pulse

method is limited by the sensitivity of the final phase and

the frequency error at the end of the frequency hop period

(in our case 10 s) to the levels of the current pulses. This

sensitivity will be a function of the loop parameters, and

its maximum allowed level depends on system

specifications. In our case, for example, when the 3rd

order loop was used during the measurements, a

frequency error of 12 kHz was produced by a 1% error

in pulse level. The figure agrees with that predicted by 2nd

order loop approximation ( 17 kHz).

In the future the aim of this work is to further develop

the two-pulses speed-up method so that it would

automatically minimize the effects of changing loop

parameters to the frequency hop speed, which was the

main shortcoming of the 1st generation implementations.

According to simulations, the adaptive method under

development has the potential of significantly enhancing

the usability of the two-pulses speed-up in real-life

applications.

b) Effect of nonlinearities on the in-band noise of a

synthesizer

In the field of synthesis much of the theoretical

work carried out in the project was devoted to how

various factors contribute to the Banerjee Figure of Merit

(BFM) which is a good measure of synthesizer

performance for in-band noise [3]. A theory has been

developed how jitter in digital logic, charge-pump current

noise, offset current noise and reference noise contribute

to the in-band noise of the synthesizer. Moreover, it has

been shown for the first time both analytically and

experimentally how the nonlinearities of the phase

detector in particular mix the high frequency quantization

noise peculiar to frequency synthesizers into its in-

band noise [4]. The analysis developed lets the designer to

set specific requirements for all of the above noise sources

when trying to achieve a specified in-band noise level. In

addition, several circuit techniques have been developed

and realized by which the above noise sources or their

effects can be minimized. To serve as a base for further

work, and to validate the theoretical understanding of

synthesizers, a state of the art prototype was also

developed.

A phase noise plot of the tested synthesizer chip is

shown In Fig. 3 [4].

Figure 3 – Phase noise plot of the tested synthesizer.

A comparison of this synthesizer with other recently

published work is shown in Table 1 below.

The developed synthesizer chip clearly demonstrates the

power of the developed circuit techniques. For example,

its performance with regard to the in-band noise is almost

equivalent in integer-N or fractional-N operation modes.

The main source for the elevated in-band noise in the

fractional synthesizer is the nonlinear mixing of the

quantization noise into the signal band. The circuit

techniques developed in the project to minimize this effect

were shown to be very effective. The most important of

the developed circuit techniques is the transfer of the

operation point of the phase detector into its linear range

by an additional offset current in the charge pump and the

minimization of the active range of the jitter coming

out of the divider by post-filtering techniques. As

expected, turning off this offset in integer-N mode had no

impact on in-band phase noise. However, if the offset was

disabled in fractional-N mode, the in-band noise increased

by as much as 20 dB, which clearly demonstrates the

Table 1. Comparison of the performance of published

synthesizers Ref Techn. Fout Fref Resol. In-band

Noise

BFM Max.

Power

(GHz) (MHz) (Hz) (dBc/Hz) (dB) (mW)

[14] 0.5 m

CMOS 900 7.99 <1 -92 -202 43

[15] 0.35 m

BiCMOS 2.47 8 <10 -82 -201 16

[16] 0.25 m

CMOS 1.8 26 400 -60 -171 70

[17] 0.6 m

CMOS 1.84 20 -75 -187

[18] 0.35 m

CMOS 1.76 13 <51000 -79 -193 22.6

[19] 0.6 m

CMOS 1.715 20 10 -90 -202 140

[20] 0.5 m

CMOS 2.4 48 50 -100 -211 135

This

work

0.35 m

SiGe

BiCMOS 2.432 16 < 100 -97 -213 18

95


detrimental effect of the non-linear mixing on the in-band

noise of the synthesizer.

c) Avoiding spurs by periodical behavioural analysis

The modulator is one of the key units of the

fractional-N synthesizer. The synthesized frequency is a

product of a stable reference frequency and a fractional

number provided by the modulator. However, it is not

just a plain, static number. In fact the modulator generates

a sophisticated control signal with the mean

corresponding to the desired fractional number. The

spectral purity of the modulator generated signal

directly affects the spectral purity of the synthesized

channel. Therefore, first and foremost the modulator

generated signal should be properly noise shaped and free

from spurious tones.

Short limit cycles are identified as the most severe

reason for the spurious tones appearing in a modulator

generated signal. A common method for randomizing

modulator signal and breaking the limit cycles is known

as dither. The drawbacks for using dither are extra

hardware, additional noise introduced to the system and

possible problems with modulator stability. Some

designers use intuitive and experimental methods for

randomizing modulator behaviour by inserting “seed

values” into modulator registers [5]. modulator is a

nonlinear system and any rigorous analysis is very

difficult. Existing exact solutions are too narrow and too

sophisticated to be practically applicable. Many aspects of

modulator operation are still not well understood.

In this work the problem of limit cycles has been

eliminated for two common modulator architectures used

in fractional-N frequency synthesis. The approach is

based on the original observation that the modulator

sequence length can be controlled for all channels by

applying predefined initial conditions and modulator

scaling. This observation gave rise to a practical method

for modulator design and sequence length prediction [6].

Long sequences guarantee that the quantization noise does

not get concentrated on only a few dominant spurious

tones. At the same time the modulator behaves in a fully

predictable way. This allows collecting full information

about modulator spectrum for all channels. The worst case

performance for all channels can be presented in the form

of spectrum envelope, see Fig. 4. The envelope show

modulator the spurious-free range in a most reliable way.

As shown in Fig. 4, the SFR can be controlled with

respect to the modulator sequence length.

The developed design method allows a quick

modulator design for the fractional-N synthesizer.

Modulator SFDR is easily determined and reliable. A

trade-off between the SFDR requirement and modulator

resolution allows a planned and reasonable use of

hardware resources.

Figure 4 – Sequence length impact on the spurious free

range.

d) New architectures

Quantization noise reduction by decreased phase step

The other research topic in the field of frequency

synthesis has been the development of a new

synthesizer architecture where phase quantization noise is

being reduced by utilizing a fractional-N divider instead

of the integer-N divider typically used in synthesizers

[7]. The proposed architecture can also be considered a

modification of fractional-N synthesis based on a

fractional-N divider with the added feature that the control

of the fractional-N divider is based on techniques.

The use of the fractional-N divider realized with a

digitally controlled delay line, for example, in connection

with techniques decreases the phase step and

quantization noise, respectively, proportionally to the

number of delay elements used in the line. With 16

elements, for example, the phase quantization step size is

2 /16, giving a 24 dB reduction in quantization noise.

As a result the project introduced a new synthesizer

architecture shown in Fig. 5. This architecture combines

other fractional-N techniques with techniques to

remove the spurs introduced by the other fractional-N

techniques. This new architecture significantly reduces

the quantization noise by employing techniques on a

fraction of a VCO cycle rather than on a whole VCO

cycle. On the other hand, if the proposed architecture is

considered a modification of the fractional-N divider

based synthesis, the advantages of the method are higher

resolution and reduction of the level of spurs caused by

delay error in the fractional divider.

In the published system the VCO cycle fraction was

intended to be produced by a delay line but recent results

suggest even higher performance when unit element

charge pump structures are being used to achieve the

same effect. The reason for the improved performance

comes from the fact that in the latter realization the

mismatch error between the unit element charge pumps

will be noise-shaped, whereas in the delay element

65 650 6500-120

-100

-80

-60

-40

-20

0

20

2^9

2^13

2^17

Seq. length:

2^21

-81 dBc @200KHz offset

-69 dBc

Offset from the carrier, frequency [KHz]

Pow

er [dB

c]

96


realization it is only randomized. These results have,

however, not been published yet.

Figure 5 – New architecture.

FD Based Synthesizer

Yet another research topic in the field of frequency

synthesis has been the digitization of the whole PLL loop

(expect the VCO) by measuring the VCO frequency with

a frequency discriminator [8]. One advantage of the

digitization is the flexibility achieved in the design of the

loop filter, for example. This is useful for rapid

acquisition and for directly producing FSK waveforms

through the synthesizer without up-conversion. Another

important advantage is the possible reduction in the

achievable phase noise level especially if the sampler that

combines sampling filtering and mixing (see below) is

used to down-mix the VCO output for the frequency-to-

digital conversion. This is useful to produce synthesizers

with on-chip loop filters even when charge pump currents

are high in order to have low noise.

A frequency synthesizer architecture based on the

above concept as shown in Fig. 6 has been studied in the

project. The kernel of this architecture is the frequency

discriminator, which converts frequency to a digitized bit

stream. It enables the use of a digital loop filter, and offers

great flexibility with digital signal processing.

Figure 6 – Block Diagram of a Frequency Discriminator-

based Synthesizer

A 3rd order MASH architecture frequency

discriminator has been developed and investigated. An

accurate linear model with phase noise analysis was also

developed. Quantization noise degrading caused by the

digital component delays is reported, which limits the use

of this FD in RF frequency range [9]. Figure 7 shows the

simulated quantization noise degradation in the 3rd order

MASH frequency discriminator with a 880 MHz carrier,

10 kHz frequency modulation in the presence of 30 ps

skew and 0.2 ns stage delay mismatch.

Figure 7 – Quantization Noise Degradation in MASH

Frequency Discriminator.

A specific feature of the FD based synthesizer

architecture suggested in this work is that a down-

conversion mixer is introduced between the VCO and the

FD [9]. This mixer decreases the division ratio, thus

decreasing the well-known 20logN in-band phase noise

amplification. The mixer also decreases the input

frequency of the frequency discriminator and enables the

use of a higher-order frequency discriminator in the RF

frequency synthesizer.

The synthesizer and discriminator are modelled in

SIMULINK in time domain and frequency domain.

Modelling in VHDL-AMS/Verilog-AMS is also going on.

97


This kind of modelling enables simultaneous high-level

behavioural and more accurate circuit level simulations. A

prototype synthesizer PCB with discrete components is

also under construction. In the ASIC realization of the

synthesizer the mixer will be realized based on the

following sampling filter concept that has, however, also

other potential applications and has therefore gained

considerable attention in the project.

e) Sampling filters

The work in this particular field has concentrated on

investigating sub-sampling (i.e. band-pass sampling) with

integrated signal processing, such as partial channel

selection and anti-aliasing filtering, as a potential

alternative for signal conditioning and down-conversion

in radio receivers. The use of a sub-sampling circuit in a

receiver chain prior to baseband signal processing and

A/D conversion can relieve the bandwidth constraints and

minimize the power consumption of the baseband

discrete-time circuit blocks by lowering their sampling

frequency. However, the use of conventional simple sub-

sampling circuits have usually been avoided due to their

modest dynamic range, especially noise, performance

resulting mainly from the lack of proper anti-aliasing

filtering in front of the sampler.

Different from conventional voltage-mode sampling

circuits, the sampler structure investigated in this project

is based on integrative sampling of current, or charge,

signal. Integrating current into a sampling capacitor

within a determinate time window itself produces a

continuous-time sin(x)/x-type low-pass response, which

limits the noise (and signal) bandwidth of the sampler

[10]. Integrating several charge samples into the sampling

capacitor during the output sampling period extends the

filtering properties of the sampler to discrete-time finite-

impulse-response (FIR) filtering. Fig. 8 shows the

principle of a general active-integrator-based charge

sampling circuit with an embedded N-tap complex FIR

filtering function.

In the sampler operation the front-end trans-

conductance (Gm) cell’s output current is alternately

integrated into the real (I) and imaginary (Q) channel

sampling capacitors connected in negative feedback

configuration. The integrated charge samples of both

channels are weighted by coefficients with values +1, -1

and 0 by sets of switches controlled by I and Q channel

clock signals. After the charge accumulation cycle the two

quadrature outputs are sampled, or decimated, at the final

output sampling rate Ts which fully determines the

location of the sampler’s output signal spectrum. Thus

down-conversion by sub-sampling can be combined into

the operation of the sampler by decimating a band-pass

input signal at a rate below its Nyquist frequency.

Gm

preCs

Vin

Voutre(nTs)

preset

p imCs

Voutim(nTs)

preset

pout

+1 0

0+1

-1

-1

+1

-1

+1 00

NTit=(n-1)Ts t=nTs

pre

pim

preset

pout

pout

p re

pre+

-1

pre-

pre0

Ti

Figure 8 – Principle of a general charge sampling circuit.

With an appropriate clock scheme, the sampler circuit

of Fig. 8 can implement an arbitrary complex FIR filter

function, the impulse response of which consists of

coefficients restricted to the set {±1,0,±j}. The filter taps

can be obtained e.g. by quantizing an arbitrary target

impulse response by using modulation [11]. Due to its

asymmetric response for positive and negative

frequencies, a charge sampling circuit with an integrated

complex FIR filter can be utilized in radio receivers for

image rejection and quadrature down-conversion in

addition to its partial channel selection and anti-aliasing

filtering properties. Also, with a proper choice of circuit

implementation, the proposed sampler can be configured

to perform complex filtering and further quadrature down-

conversion to baseband or to low-IF for complex (I/Q) IF

signals.

Fig. 9 presents two simulated sample amplitude

responses of complex charge sampling circuits with two

different 3072-tap FIR filtering functions. The targeted IF

input centre frequency of the designed samplers is fc = 100

MHz, while the baseband output sampling frequency

equals to fs 1.042 MHz. The dashed line shows the

response of the simplest possible complex band-pass

sampler realization with all FIR filter coefficients having

absolute value of unity. The solid line illustrates the

amplitude response of a charge sampler with a more

advanced FIR function utilizing quantized tap

coefficients. Fig. 9 shows that both filtering responses

ideally provide almost similar suppression of negative

frequencies (i.e. image rejection), but the wanted signal

band selectivity of the sampler with the integrated FIR

filter is superior to the simple sampler. The example

sampler realization ideally provides over 40 dB of

inherent anti-aliasing and out-of-band attenuation with a

98


modest increase in the circuit complexity. Note that due to

the semi-analog-semi-digital filtering operation of the

sampler, its filtering properties, such as bandwidth and

centre frequency, can be modified in real time by

changing the FIR filter coefficients and/or sampling

frequency of the sampler. This kind of sampling filter is

applicable to radio receiver structures simultaneously

supporting several communication standards, and possibly

eventually to fully software-defined radios.

fc-4fs fc-3fs fc-2fs fc-fs fc=100 MHz fc+fs fc+2fs fc+3fs fc+4fs

-100

-80

-60

-40

-20

0

|Frequency|, fs=1.042 MHz

No

rmal

ized

am

pli

tud

e [d

B]

positive frequencies negative frequencies

Figure 9 – Examples of complex sampler responses.

During the project period two charge sampling circuit

realizations have been designed and measured. According

to the measurements, the implemented fully differential

complex IF sampler with an embedded 192-tap complex

FIR filter function in 0.35 m CMOS has a stable

dynamic range performance with 66 dB of spurious-free

dynamic range (SFDR) up to 100 MHz operating

frequency [10,12]. The other test circuit, fabricated in a

0.8 m BiCMOS process, integrates a 192-tap complex

FIR filter and a complex narrowband SC filter on the

same chip providing over 44 dB of image rejection on its

26.3 kHz –3 dB bandwidth [13]. A summary of the

measured results for both test circuits is given in the Table

2 below.

III. IMPACTS

The main technical results of the project are:

1) Development of a new speed-up method for integer- N

and fractional-N type synthesizers including

synthesizers [1].

2) Analysis of the contribution of various synthesizer

noise sources to the in-band noise of a synthesizer,

especially the analysis of how the nonlinearities of the

phase detector in particular mix the high frequency

quantization noise peculiar to frequency synthesizers

into its in-band noise. This work has resulted in the

development of a state-of-the-art synthesizer chip [4].

3) Development of a methodology to decrease the level

of spurs in a modulator to a negligible level [6].

4) Development of a new modulator architecture that

decreases the amount of quantization phase noise by

reducing the phase quantization step size [7].

5) Suggestion for a new synthesizer architecture that is

based on frequency-to-digital conversion. An essential

part of the suggested architecture is a mixer that avoids

the 20logN noise problem faced with standard PLL type

synthesizer architectures [9].

6) Development of a new sampling filter concept that

originally was intended to be part of the above new

synthesizer architecture but which in the course of the

project has been found to have importance as a new

discrete time, programmable FIR filtering concept that has

a lot of potential applications in filtering the stages of

radio receivers, especially in multi-radio environment.

The concept has been verified by realized and tested

circuits [10,12-13].

All the above results have been published or submitted

to be published in the leading journals of the field as well

as in international conferences, only a few of which are

referred to below. The main results have also been

published as a post-graduate course held at the University

of Oulu in the autumn of 2003. The course was open also

for participants from industry. So far the project has

resulted in one doctoral degree (Juha Häkkinen) and one

Master of Science thesis (Maciej Borkowski) and 4 other

doctoral theses are currently under preparation about the

research subjects of the project. Two of them will be

finalized during 2004-2005 (Sami Karvonen, Tom Riley).

In general the project has made it possible for the research

group involved with the project to start serious work in

the field of frequency synthesis. That work will continue

after this particular project, also with some totally new

promising ideas not presented above.

Table 2. Performance of the realized sampling

filtersTechnology 0.8 m BiCMOS 0.35 m CMOS

-3 dB bandwidth 26.3 kHz 923 kHz

IIP3 -8 dBV (in-band) +25 dBV (out-of-band)

SFDR 59 dB 66 dB

Image band

rejection

>44 dB >36 dB

Power

consumption

85 mW @ 5 V 30 mW @ 3.3 V

99


REFERENCES

[1] J. Hakkinen and J. Kostamovaara, “Speeding up an

Integer-N PLL by Controlling the Loop Filter

Charge”, IEEE Transactions on Circuits and

Systems, II Analog and Digital Signal Processing

Vol. 50, Issue 7, July 2003, pp. 343-354.

[2] J. Hakkinen and J. Kostamovaara, “General-Purpose

Fast-Switching PLL IC for Frequency Synthesis”,

The 45th IEEE International Midwest Symposium

on Circuits and Systems, vol 3, pp. 532-535, 2002.

[3] D. Banerjee, “PLL Performance, Simulation and

Design” http://www.national.com/appinfo/

wireless/deansbook.pdf

[4] T. Riley, N. Filiol, Q. Du, J. Kostamovaara,

“Techniques for In-Band Noise Reduction in

Synthesizers”, invited paper in IEEE Transactions on

Circuits and Systems II: Analog and Digital Signal

processing, Vol. 50, No. 11, November 2003, pp.

794-803.

[5] M. A. Kozak and I Kale, "A pipelined noise shaping

coder for fractional-N frequency synthesis", IEEE

Transactions on Instrumentation and Measurement,

Vol. 50, May 2001, pp. 1154-1161.

[6] M. Borkowski, T. Riley, J. Häkkinen, J.

Kostamovaara, "A Practical modulator Design

Method Based on Periodical Behaviour Analysis",

submitted to IEEE Transactions on Circuits and

Systems I in 2004.

[7] T. Riley and J. Kostamovaara, "A hybrid

fractional-N frequency synthesizer", IEEE

Transactions on Circuits and Systems II: Analog and

Digital Signal processing, Vol. 50, No. 4, April

2003, pp. 176-180.

[8] W. T. Bax, M. A. Copeland, “A GMSK Modulator

Using a Delta-Sigma Frequency Discriminator-

Based Synthesizer”, IEEE Journal of Solid-State

Circuits, Vol. 36, No.8, August 2001

[9] S. Zheng, T. Riley, J. Kostamovaara, “On Phase

Noise of Sigma-Detal Frequency Discriminator for

Applications in Frequency Synthesizers”, submitted

to ICCCAS 2004, Chengdu, China

[10] S. Karvonen, T. Riley, J. Kostamovaara, “A CMOS

Quadrature Charge Sampling Circuit with 66 dB

SFDR up to 100MHz”, submitted to IEEE

Transactions on Circuits and Systems I in 2004.

[11] S. Karvonen, T. Riley, J. Kostamovaara: "Charge

sampling mixer with delta-sigma quantized impulse

response", Proceedings of the IEEE International

Symposium on Circuits and Systems (ISCAS 2002),

26 May 2002 - 29 May 2002, Scottsdale Princess

Resort, Scottsdale, Arizona, USA, 4p.

[12] S. Karvonen, T. Riley and J. Kostamovaara, “A 50-

MHz CMOS Quadrature Charge Sampling Circuit

with 66 dB SFDR”, accepted for presentation at the

2004 IEEE International Symposium on Circuits and

Systems (ISCAS 2004), Vancouver, Canada, May

23-26, 2004.

[13] S. Karvonen, T. Riley, S. Kurtti and J.

Kostamovaara, “A 50-MHz BiCMOS Quadrature

Charge Sampler and Complex Bandpass SC Filter

for Narrowband Applications”, accepted for

presentation at the 2004 IEEE International

Symposium on Circuits and Systems (ISCAS 2004),

Vancouver, Canada, May 23-26, 2004.

[14] W. Rhee, Bang-Sup Song, and Akbar Ali, “A

1.1GHz CMOS Fractional-N Frequency Synthesizer

with a 2-b Third-Order Modulator,” IEEE

Journal of Solid-State Circuits, Vol. 25, No.10,

October 2000.

[15] W. Rhee, B. Bisanti, and Akbar Ali, “An 18mW

2.5GHz/900-MHz BiCMOS Dual Frequency

Synthesizer With <10Hz Carrier Resolution,” IEEE

Journal of Solid-State Circuits, Vol. 37, No.4, April

2002.

[16] B. De Muer and M. Steyaert, “A CMOS Monolithic

-Controlled Fractional-N Frequency Synthesizer

for DCS-1800,” IEEE Journal of Solid-State

Circuits, Vol. 37, No.7, July 2002.

[17] M. Perrott, M. Trott and C. Sodini, “A Modeling

Approach for Fractional-N Frequency

Synthesizers Allowing Straightforward Noise

Analysis,” IEEE Journal of Solid-State Circuits, Vol.

37, No.8, August 2002.

[18] R. Ahola and K. Halonen, “A 2GHz Fractional-N

Synthesizer in 0.35 m CMOS,” in Proc. European

Solid-State Circuits Conference, Stockholm,

Sweden, September, 2000, pp. 472-475.

19] Chun-Huat Heng and Bang-Sup Song, “A 1.8GHz

CMOS Fractional-N Frequency Synthesizer with

Randomized Multi-Phase VCO,” in Proc. Custom

Integrated Circuits Conference, 2002.

[20] S. Willingham et al, “An Integrated 2.5GHz ��

Frequency Synthesizer with 5 s Settling and 2Mb/s

Closed Loop Modulation,” in Proc. International

Solid-State Circuits Conference, San Francisco,

USA, February, 2000, pp. 200-201.

100


On-Chip Communication Architecture for HW/SW Co-Design

Jarmo Takala , Timo Hämäläinen , and Karen Egiazarian

Institute of Digital and Computer Systems

Institute of Signal Processing

Tampere University of Technology, P.O.B. 553, 33101 Tampere, Finland

[email protected], [email protected], [email protected]

ABSTRACT

Currently design of system-on-chip (SoC) products is

based on the premise that the communication structure

between functional blocks can be described in very imprecise fashion. This can cause severe errors in

predicting the performance of the system.

In this project, future SoC designs are considered; chip interconnection architectures, formal design

methodology, and spectral testing methods are developed.

The project is still on-going and ends at 2004.

I. INTRODUCTION

Embedded products are often built around specialized

computational nodes and interconnection architectures.

The shrinking size of transistors drives the electronic

systems into a single integrated circuit or system-on-chip

(SoC) solutions. To cope with the increasing complexity

of systems, some design objects are prepared such that

they are reusable. They are usually called as intellectual

property (IP) blocks. The IP blocks can be shared within

the organization or obtained from external sources.

However, interfacing, testing, and verification of IP

blocks from a variety of sources have proven to be

difficult.

From the technology point of view, an efficient

interconnection architecture plays a central role in

successful continuous-media applications, where large

amount of data is transferred back and forth in the system.

Selection of the interconnection that supports the given

application domain can be of crucial importance. General-

purpose interconnections might not map the utilized

algorithms adequately. Furthermore, power consumption

of interconnections may be too high. Wide buses can

exhibit crosstalk and other implementation problems due

to the pressure to route long signal lines close to each

other. In addition, to be reusable, the interconnection must

be well standardized and readily expandable. The design

process must not be forced to start from the beginning if

changes occur along the interconnection.

Formal design methods would be ideal for describing

the design from specification to the final implementation.

To complete the SoC design flow, testing the circuits at

various levels of abstraction is essential. It consists of

verification of equality of the output produced by the

circuit to the designed output. The main effort in testing is

to minimize the number of test patterns, yet covering all

the possible faults.

This project has been considering all these problems.

The objective of the project was to develop on-chip

interconnection architectures and methods for future SoC

designs. The project considered three research topics: a)

communication architecture, b) formal design

methodology, and c) spectral testing methods. The results

of the topics are discussed in the following sections.

II. COMMUNICATION ARCHITECTURE

The goal for this task was to design and implement

modular, flexible, and efficient communication

architecture for contemporary and future system-on-chip

implementations that can be seamlessly integrated to a

system design flow. In order to achieve this goal, the task

has been divided in five subtasks that are analysis of

topologies, specification and implementation of the new

communication architecture, optimization methods and

integration to a system design. Each of the subtasks is

elaborated in the following.

a) Analysis

The key problems in on-chip communications were

first identified with the help of evaluation of existing

multiprocessor systems. Table 1. summarises the main

issues of this evaluation. It was concluded that the

topology should be flexible and provide standardised

means to attach heterogeneous functional blocks to the

system. The primary target for optimizations was chosen

to be communication efficiency (energy and performance)

as there are many conflicting requirements.

In the next phase, detailed analyses were conducted

for existing interconnection schemes. Theoretical

comparisons provide rough theoretical connectivity and

complexity estimates in an application independent way.

Bus, crossbar and mesh topologies with variations were

chosen for further analysis.

101


Table 1 - Key differences in past and present multiprosessor

systems.

Multiprocessor systems (past) System-on-Chip (portable

device)

Scaleability important after fab

(increase nodes)

Scaleability an issue only at

design time (reuse, easy addition

of nodes)

Load balancing and even distribution

of computation (max performance)

Energy most important

Power save, several clock domains

Communication network used as

means of balancing computation and

communication (both adjusted for

optimal performance)

Computation fixed per node

(functional partition)

Network serves nodes (only

network adjusted)

Dataflow computing Computation is very

heterogeneous, both dataflow and

control style

Uniform nodes Specialized nodes

Clusters of different nodes

Single vendor, no interfacing

problems

Several vendors, extra adapters

needed to interface blocks

together

Application optimized memory

hierarchy

Heterogeneity of nodes requires

several memory hierarchy

approaches

The next analysis level was conducted with real

synthesised and simulated architectures that give the

complexity and performance in physical area and

throughput measures. These architectures are based on a

set of generic communication building blocks including

IP-block wrappers, distributed and centralized arbitration

units, and network segments. Generic blocks allow design

of comparable, parameterized architectures and very

reliable results.

The communication load was tested with different

transfer patterns resembling potential system-on-chip

applications. As a conclusion, a bus based and mesh based

architectures were found most feasible. The former gives

the best cost/performance ratio, but the latter is better in

performance for intense localised data traffic.

b) Specification

Analyses led to an interconnection approach that

utilizes a hierarchy of bus structures. In this type of

architecture, the local interconnections are bus segments

making use of their known good properties. The global

on-chip connections use a more complex network

structure containing buffering bridges resembling the

router/switch units of dynamical topologies. This type of

heterogeneous architecture can be modified according to

the requirements of the application, scaling from point-to-

point links to an arbitrary topology.

To name key features, data transfers in the bus

segment take place in a circuit switched manner

(synchronous), but transfers across bridges are packet

switched (asynchronous). The arbitration is distributed

which saves dedicated point-to-point signals and greatly

helps modularity. In addition, all signals are identical and

shared between wrappers in the network side. This makes

the wrapper layout independent of the number of IP-

blocks and simplifies design reuse.

Table 2 - Implementations.

Bit width FIFO depth Utilization

8 5 Emulation with Celaro

Gate-level simulation (0.35 µm CMOS)

Synthesis (Celaro emulator)

Synthesis (0.25, 0.35 µm CMOS)

8 Synthesis (0.25 µm CMOS)


16 5 Gate-level simulation (0.25 µm CMOS)

Synthesis (0.25 µm CMOS)

Layout (0.25 µm CMOS)

Gate-level simulation (0.18 µm CMOS)





32 5 Synthesis (0.25 µm CMOS)


6 Power estimation (0.18 µm CMOS)


Power estimation (0.18 µm CMOS)


12 Power estimation (0.18 µm CMOS)


Power estimation (0.18 µm CMOS)


The performance and energy efficiency has been

reached by making the lowest level data transfers simple

and performing all higher level functions above these

basic mechanisms. TDMA-based arbitration ensured zero

latency in transfer preparation phase. There is not allowed

any wait cycles in the basic transfers, which means that

every clock edge carries payload data.

c) Implementation

Implementation of the interconnection architecture

was focused on the wrapper that connects the network and

the IP-Block together. It should be noted that the bridges

can also be implemented using the wrapper.

Several implementations were carried out for

comparison and development purposes. Table 2.

summarises the implementations according to the wrapper

bit width, internal FIFO memory sizes and technology.

Most of the implementations were carried out for

comparison of area, speed and power consumption.

An implementation was also made for VLSI lay-out

and testing the design flow with a hardware emulator

equipment (Celaro from Mentor Graphics). As a

conclusion, the implementations gave very accurate

picture about the capabilities of the new interconnection.

Compared to the related reported research results, the

interconnection architecture was found to be among the

best in performance/area ratio.

d) Optimization

The wrapper implementation gives basic mechanisms

to configure the wrapper both at design and run time. Bit

102


widths and FIFO depths can be set only before synthesis,

but other parameters affecting arbitration and power

saving can be configured on the fly.

Optimization of the interconnection focused on power

saving. An experimental study was conducted that

compared power saving methods with the interconnection

wrapper. Basic mechanisms include shutting down parts

of the wrapper through clock gating, slowing down the

clock speed and scaling voltage as well as total shut down

of a wrapper. For run time optimizations, fine-tuning of

the time slot period (TDMA arbitration) using bus

monitoring is carried out.

A low bit rate video encoder was used as a test

application, and a test case implementation with several

processors, memories and wrappers was designed. The

experiments show that power saving of around 40 % can

be achieved when the operation of application and the

components of the implementation are optimized. It

should be noted that even better power saving is possible,

but not without violating the real time requirements of the

application.

e) Integration

The designed interconnection architecture offers

convenient interfacing for system design flow at various

abstraction levels. For architecture description, the

interconnection wrappers and segments are given as

library components. At the lowest level, the components

are physical HW descriptions that can be synthesized and

implemented in real technology. At the highest level, the

interconnection is given as channels and bounded FIFO

interfaces.

After HW/SW partitioning, the HW will be

implemented as IP-blocks, SW as processes in processor

blocks and communication between all blocks using

wrappers, bridges and network segments. The decision of

partitioning is carried out in the co-design phase. After

this, the communication optimization takes place. In this

step, communication related parameters are optimized

based on the data transfer pattern present in the current

application.

III. FORMAL DESIGN METHODOLOGY

The work in this task was based on DisCo language

and toolset [9] developed at Institute of Software Systems

at Tampere University of Technology. DisCo is a formal

specification and design methodology for reactive and

distributed systems. It consists of an incremental design

method based on superposition, specification language,

and a collection of supporting tools.

The objective of this task was to develop a design

methodology for DisCo, which allows a tool supported

path towards hardware implementation. The actual design

work is performed with refinement steps; the design focus

shifts along with the stages of the methodology from

high-level refinement steps to code generation for third-

party tools. The developed design flow is illustrated in

Fig. 1.

The main result is the DisCo-VHDL Compiler, which

generates hardware descriptions from intermediate

representation generated by the DisCo tools.

Initial

Specification

Full

Functionality

Interfaces

Hardware

Description

DisCo

Animation

DisCo-VHDL

Compiler

DisCo

Verification

DisCo

Compiler

Validation

Feedback

Informal

Validation

Logic SynthesisCosimulation

Design Steps: Functionality

Design Steps:

Partitioning and Architecture-Specific Details

Flat Intermediate

Representation

Library of Reusable

Hardware Schedulers

Figure 1 – Principal formal design flow.

a) Specification

The system is first described with DisCo specification

language, which is based on the concept of temporal logic

of actions (TLA) proposed in [10]. TLA is a linear-time

temporal logic with an expressive power that is suitable

for the transformational design style where specifications

are refined using correctness-preserving steps. TLA

combines two logics: logic of actions for representing

relations between pairs of states and temporal logic for

reasoning on infinite sequences of states.

The initial DisCo specification of the system is a

collective behaviour of objects. In this model, the system

state is defined by objects participating in joint actions.

The superposition steps are given in a layer, which

includes also the initial specification. The specification

can be validated with DisCo tools.

The developed methodology towards hardware

implementation consists of partitioning, allocation,

scheduling and mapping phases. These are described in

the following.

b) Partitioning

The system is first partitioned in specification space,

i.e., the functionality of the system is specified without

any apparent link to implementation. This results in a

layered design style where parallel layers of superposition

are used to structure the system. When the partitioning in

103


specification space is completed, all the parallel layers

have been composed into a single, flattened DisCo layer

consisting of objects and actions.

The previous layer is used as the starting point for

partitioning in implementation space. We use here object-

oriented partitioning, i.e., objects are partitioned first and

actions are considered later. First the joint actions need to

be composed into elementary actions that can be assigned

to components for execution. After this phase the objects

are assigned to components.

c) Allocation

When proceeding towards the implementation, we

need to allocate components to target architecture. If there

are several subsystems, a communication channel is

needed, which implies need for interface, thus we need to

create the needed interface actions.

d) Scheduling

The next task is scheduling. DisCo supports liveness

in terms of strong fairness assertions; neither generalized

fairness assertions can be expressed nor weak fairness

assertions are supported. Therefore, these fairness

assertions must be maintained interactively by the

designer or theorem proving environment. The scheduling

of joint actions can be performed with the aid of atomicity

refinement since the responsibilities of execution can be

found out easily. The active participant is the one, which

modifies its state, while the other participant only allows

its variables to be read.

e) Mapping

The final task is to map the DisCo specifications to a

hardware description language. In this work VHDL is

used. In the mapping process, the following principles are

used. DisCo components are mapped to VHDL entities. If

the component has interface variables, the entity has an

output port. Vice versa, if the component depends on an

interface variable, it has an input port. Objects are mapped

onto synchronous VHDL processes. Various variables and

states are naturally mapped to VHDL signals. In a similar

fashion, we map the guards of instances of actions to

signals. Relations, in turn, are realized with the aid of

Boolean valued registers. Finally, fairness assertions are

implemented with scheduler structures. These are reusable

hardware structures, which are stored into a library. A

scheduler obtains guard signals, evaluates them, and

selects the corresponding enable action for execution. The

principles of scheduler structures are discussed in detail in

[11], the DisCo-VHDL Compiler is described in [12], and

the entire design methodology is reported in [13].

IV. SPECTRAL TESTING METHODS

Spectral techniques are a mathematical discipline,

which may be described as an area of abstract harmonic

analysis devoted to the applications in engineering,

primarily electrical and computer engineering.

Transferring a problem from the original into the spectral

domain may provide several advantages. Some numerical

calculation tasks, difficult to perform in the original

domain, may be simpler in the spectral domain.

Additionally, many properties of the functions, realizing

circuits, are much more easily detected in the spectral

domain than in the Boolean domain, see, e.g. [14][15].

With the advent of VLSI and corresponding drastic

increase in the density of gates on a chip, high-level

functional testing is one of the most viable approaches to

the testing of computer hardware. It may be remarked,

that testing is the “bottleneck” of computer industry. The

cost of testing is often higher, than the cost of design.

Interconnection of components in the device-under-test

(DUT) is too complex or not known for a user, which

makes the testing a rather difficult and complex task in

terms of both space and time. Traditional methods of

design and testing require brute force computer search for

solving optimization problems. Unlike to that, spectral

methods may provide simple “analytic” solutions.

Figure 2 – Binary Decision Diagram.

a) Binary Decision Diagrams

Major problem with spectral techniques in the area of

digital design is the computational complexity. Most of

the spectral transform algorithms used for signal

processing are not feasible here, mostly due to a much

larger size of the problem instances. One possible way of

dealing with this problem is to develop separate transform

algorithms for various classes of functions (divide-and-

conquer approach) [16]. However, such an approach is not

always appropriate. An alternative way is to utilize

sophisticated data structures, able to handle a wide variety

of functions, where the state of the art is Binary decision

diagram (BDD). BDDs have evolved over the years into a

very successful data structure for Boolean function

manipulation. They allow for rapid and successful

computation of spectral coefficients for a wide variety of

functions, realizing circuits, e.g., in [18][19][22][23][24].

However, even BDDs do not always provide a

satisfactory solution. For some circuits we cannot build a

BDD for a given function within a reasonable amount of

space and time resources. Thus, in the case of most

arithmetic circuits, BDDs express an exponential

complexity in terms of input counts. For this exponential

104


complexity, the improvement in computer speed and

memory does not considerably contribute to the solution

of the problem. On the other hand, in certain tasks only a

single or a few coefficients of the spectrum are of an

interest. In this case, BDD based solutions are still

possible even for huge circuits [15]. Otherwise, when

complete spectrum must be computed, new data structures

for representation of Boolean (or discrete) functions are

required.

Figure 3 – Group-theoretic approach to logic design.

b) Super Decision Diagrams

Super Decision Diagrams (SrDDs) are a generalization

of BDDs, based on the redistribution of information

content in a complex graph with simple nodes, as a BDD,

into a simple graph with complex nodes.

The increased functionality of nodes in SrDDs will

provide solutions where the existing BDDs cannot be used

[20][21]. This approach is supported by the existing

technology which permits realizations of such nodes

without increasing their cost. For example, in

commercially available Look-up Table Field

Programmable Logic Arrays (LUT-FPGAs), the

realization of any subfunction with a given number of

variables has the same cost, a complete LUT is required

irresective of the complexity and features of the

subfunction realized. Due to the increased functionality of

nodes, SrDDs will provide an efficient use of LUTs,

unlike existing BDDs, and for the simplified structure of

the graph, the total complexity of realizations will be

reduced.

V. RESULTS AND IMPACTS

The main results of the project have been published in

international conferences and scientific journals. The

impacts of the research include citations and invited

papers and presentations. Several professionals with

expertise in the field have been produced, i.e., the project

has produced one Dr.Tech. dissertation [13], one Dr.Tech.

dissertation is under construction [1], and two graduate

degrees.

The project created closer international collaboration

with Univ. CA, Berkeley, USA; Dr.Tech. Kimmo

Kuusilinna joined Prof. R. Brodersen’s group in Berkeley

Wireless Research Center for 21 months during 2001-

2002. Project had also collaboration with Prof. M.

Karpovsky (Boston Univ., USA), Prof. R. Stankovic

(Univ. of Nis, Serbia), and Prof. E. Dubrova (KTH, Royal

Institute of Technology, Sweden).

REFERENCES

[1] V. Lahtinen, “Design and Analysis of

Interconnection Architectures for On-Chip Digital

Systems,” 2004, manuscript for Dr.Tech.

dissertation.

[2] V. Lahtinen, E. Salminen, T. Kangas, K. Kuusilinna,

and T. Hämäläinen, “Interconnection Scheme for

Continuous-Media Systems-on-a-Chip”,

Microprosessors and Microsystems, vol. 26, no.3,

2002, pp. 123-138.

[3] V. Lahtinen, E. Salminen, K. Kuusilinna, and T.

Hämäläinen, "Bus Structures in Network-on-Chips",

in Interconnect-Centric Design for Advanced SoC and NoC, J. Nurmi, J. Isoaho, A. Jantsch, and H.

Tenhunen, Eds. Kluwer Academic Publishers, 2003,

ch. 8.

[4] T. Kangas, V. Lahtinen, K. Kuusilinna, and T.

Hämäläinen, “System-on-Chip Communication

Optimization with Bus Monitoring”, in Proc. IEEEInt. Workshop on Design and Diagnostics of

Electronic Circuits and Systems, Brno, Czech

Republic, April 17 - 19, 2002, pp. 304-309.

[5] E. Salminen, V. Lahtinen, K. Kuusilinna, and T.

Hämäläinen, "Overview of Bus-based System-on-

Chip Interconnections", in Proc. IEEE Int. Symp. Circuits Syst., Scottsdale, Arizona, May 26-29,

2002, vol. 2, pp. 372-375.

[6] T. Kangas, K. Kuusilinna, and T. Hämäläinen,

"TDMA-based Communication Scheduling in

System-on-Chip Video Encoder", in Proc. IEEE Int. Symp. Circuits Syst., Scottsdale, Arizona, May 26-

29, 2002, vol. 1, pp. 369-372.


Hämäläinen, "Comparison of Synthesized Bus and

Crossbar Interconnection Architectures", in Proc.

IEEE Int. Symp. Circuits Syst., Bangkok, Thailand,

May 25-28, 2003, vol. 5, pp. 433-436.


Hämäläinen, "Reducing SoC Power Consumption

with Generic Interconnection Components and

TDMA-based Arbitration, in Proc. IEEE Int.

Workshop Design Diagnostics Electronics Circuits Syst., Poznan, Poland, Apr 14-16, 2003, pp. 261-268.

[9] R. Kurki-Suonio and H.-M. Järvinen, “Action

System Approach to the Specification and Design of

Distributed Systems,” ACM Software Engineering

Notes, vol. 14, no. 3, pp. 34-40, May 1989.

[10] L. Lamport, “The Temporal Logic of Actions,” ACMTrans. Programming Languages Systems, vol. 16,

no. 3, pp. 872-923, May 1994.

[11] H. Klapuri, J. Takala, and J. Saarinen.,

“Implementing Reactive Closed-System

Specifications,” J. Network and Computer Applications, vol. 24, no. 2, pp. 101-123, Apr. 2001.

105


[12] J. Nykänen, H. Klapuri, and J. Takala, ”Mapping

Action Systems to Hardware Descriptions,” in Proc.

Int. Conf. Par. Distributed Process. Techniques

Applications, Las Vegas, NV, U.S.A., June 23-26,

2003, vol. 3, pp. 1407-1412.

[13] H. Klapuri, “Hardware-Software Codesign with

Action Systems,” Dr.Tech. dissertation, Tampere U.

Tech., 2003.

[14] M. G. Karpovsky, R. S. Stankovic, and J. T. Astola,

“Reduction of sizes of decision diagrams by

autocorrelation functions,” IEEE Trans. on

Computers, vol. 52, no. 5, 2003, pp. 592-606.

[15] E. Pogossova, E. Dubrova, K. Egiazarian, and J.

Astola, “Fast Uniform BDD-based Algorithm for

Computing Spectral Coefficients,” in Proc. 3rd Int. Workshop on Spectral Methods and Multirate Signal

Processing, September 13-14, Barcelona, Spain,

2003, pp. 181-188.

[16] E. Pogossova and K. Egiazarian, “Reed-Muller

representation of symmetric functions,” J. Mul. Val.

Logic, 2003.

[17] M. Stankovic, R. S. Stankovic, J. Astola and K.

Egiazarian, “Circuit realization of spectral

transforms in Fibonacci interconnection topologies,”

in Proc. IEEE Int. Symp. Circuits Syst., Sydney,

Australia, 2001.

[18] M. Stankovic, B. J. Falkowski, D. Jankovic, and R.

S. Stankovic, “Calculation of the paired Haar

transform through shared binary decision diagrams,”

Computers and Electrical Engineering, vol. 29, no.

1, Jan. 2003, pp. 13-24.

[19] R. S. Stankovic and J. Astola, “Relationships

between logic derivatives and ternary decision

diagrams,” in Proc. 5th Int. Workshop on Boolean

Problems, Freiberg, Germany, September 19-20,

2002, pp. 53-60.

[20] R. S. Stankovic and J. Astola, “Group-theoretic

approach to the optimization problems in logic

design,” in 6th. Int. Symp. Representations and

Methodology for Future Computing Technologies,

RM2003, Trier, Germany, March 10-11, 2003, pp.

35-42.

[21] R. S. Stankovic, and J. Astola, “Design of decision

diagrams with increased functionality of nodes

through group theory,” IEICE Trans. Fundamentals,

Vol. E86-A, No. 3, 2003, pp. 693-703.

[22] R. S. Stankovic and J. T. Astola, SpectralInterpretation of Decision Diagrams, Springer,

2003.

[23] R. Stankovic and J. Astola, “Some Remarks on

Linear Transform of Variable in Representation of

Adders by Word-level Expressions and Spectral

Transform Decision Diagrams,” in Proc. 32nd Int.

Symp. Multiple-Valued Logic, Boston,

Massachusetts, USA, 2002, pp. 116-122.

106

The Academy of Finland carried out the first

Research Programme for Telecommunication

Electronics, Telectronics, in 1998-2000. The

objective was to create and support high-level

basic research on scientifically essential and

rapidly developing areas of telecommunications

and electronics research, by combining research

and expertise on different areas.

The activity of Telectronics programme was

continued by Telectronics II during 2001-2003.

The programme was targeted to increase the

knowledge in the main technologies of broadband

data transfer and to produce new information to

apply for general use.

This research report collection includes the

scientific reports of 16 research projects included

in Telectronics and Telectronics II research

programmes. Together the reports cover a six-

year period of targeted basic research funding

for telecommunication electronics area.

ISBN 951-715-508-5 (print)ISBN 951-715-509-3 (pdf)

research programmes for telecommunication …...elemental ta diffusion barriers, we were able to...

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