research article low voltage floating gate mos transistor ...using nmos transistor has been proposed...
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Research ArticleLow Voltage Floating Gate MOS Transistor BasedDifferential Voltage Squarer
Maneesha Gupta, Richa Srivastava, and Urvashi Singh
Electronics and Communication Engineering Department, NSIT, New Delhi, India
Correspondence should be addressed to Richa Srivastava; richa [email protected]
Received 11 November 2013; Accepted 24 December 2013; Published 9 February 2014
Academic Editors: H.-C. Chen and S. Gift
Copyright ยฉ 2014 Maneesha Gupta et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.
This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics insaturation region.The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator.The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellationso as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate thedifferential signals.The proposed circuit provides a current output proportional to the square of the difference of two input voltages.The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such aslow supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ยฑ0.75V in TSMC0.18๐m CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.
1. Introduction
Technology scaling and growing demand of portable elec-tronic equipments have motivated the researchers towardsthe design of low voltage and low power analog signalprocessing circuits. Low supply voltage increases the batterylifetime and hence reduces the power consumption of theportable equipment. Various low-voltage lowpower designtechniques reported in literatures include subthresholdMOS-FETs, level shifters, self-cascode, bulk-driven, and FGMOStechniques [1โ10]. Among these, FGMOS concept has gainedprime importance due to its ability to reduce or removethe threshold voltage requirement of the circuit. Scaling oftransistor dimensions has motivated the designers towardsthe design of low voltage nonlinear CMOS circuits. Voltagesquarer is one of the most versatile nonlinear blocks thatfind application in several fields like neural and image signalprocessing [11โ18]. It can be used to implement variousnonlinear circuits such as multipliers, balanced modulators,and phase comparators. Analog hardware implementationof these blocks offers advantage of reduced silicon area andlow power consumption. CMOS squarer circuit based oncross-coupled differential pair has been proposed in [11]but the circuit is complex and has large supply voltage
requirement. Squarer with low supply voltage and highrejection of common-mode variations has been proposed in[12] and [13], respectively, but again these circuits requirelarge number of transistors. Recently, the squarer topologyusing NMOS transistor has been proposed in [16] but itrequires positive and negative bias voltage generator forthreshold voltage cancellation and can process only singleended input signal. This paper presents very simple and newFGMOS based differential squarer which is the combinationof the FGMOSbased squarer proposed in [17] and differentialvoltage attenuator proposed in [18].Theproposed squarer canprocess differential signals and has low supply voltage, lowpower consumption, and low circuit complexity.
The operation of FGMOS transistor is described inSection 2. FGMOS based differential squarer is proposed andanalyzed in Section 3. In Section 4, the simulation resultsare given to verify theoretical results and to demonstrate theeffectiveness of the proposed circuit. Finally, the conclusionsare drawn in the last section.
2. FGMOS Transistor
FGMOS is a multiple-input floating gate transistor whosethreshold voltage can be controlled and tuned by the values
Hindawi Publishing CorporationISRN ElectronicsVolume 2014, Article ID 357184, 6 pageshttp://dx.doi.org/10.1155/2014/357184
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2 ISRN Electronics
FG
V1
VN
S
D
(a)
FG
V1
VN
V2
C1
C2
CN
S
D
B
CFGD
CFGB
CFGS
(b)
Figure 1: (a) Symbol of FMGOS; (b) FGMOS equivalent circuit.
of capacitors and bias voltage applied. The symbol of ๐-inputFGMOS transistor and its equivalent circuit are shown inFigures 1(a) and 1(b), respectively.The voltage on floating gate(FG) ๐FG is given by [10]
๐FG =๐
โ
๐=1
๐ถ๐
๐ถ๐
๐๐+
๐ถGS๐ถ๐
๐๐+
๐ถGD๐ถ๐
๐๐ท+
๐FG๐ถ๐
, (1)
where ๐ถ๐is the set of capacitors associated with effective
inputs and the floating gate.๐ถ๐
= ๐ถ1+ ๐ถ2+ ๐ถFG๐ + ๐ถFG๐ท + ๐ถFG๐ต is the total floating
gate capacitance. ๐ถFG๐ท, ๐ถFG๐, and ๐ถFG๐ต are the overlapcapacitances of floating gate with drain, source, and bulk,respectively, ๐
๐ทis the drain voltage, ๐
๐is the source voltage,
๐๐ตis the bulk voltage, and๐FG is the residual charge trapped
in the oxide-silicon interface during fabrication process. Thetrapped residual charges give rise to the problem of offset inthreshold voltage of the device. The removal of the residualcharge can be done by using themethod suggested in [19, 20],in which the first polysilicon layer is connected to the metal-๐ (where ๐ represents number of metals available in thetechnology). By this contact, the floating gate is not connectedto any part of the circuit so it will not affect the operation ofFGMOS transistor. Therefore, neglecting the residual charge(1) can be modified as
๐FG๐ =๐
โ
๐=1
๐ถ๐
๐ถ๐
๐๐๐+
๐ถFG๐ท๐ถ๐
๐DS +๐ถFG๐ต๐ถ๐
๐BS. (2)
Thedrain current (๐ผ๐ท) of the FGMOS transistor operating
in saturation region is given by [10]
๐ผ๐ท
=๐0Co๐ฅ2
๐
๐ฟ
(๐FG๐ โ ๐๐)2 (3)
Assuming ๐ถ๐โซ ๐ถFG๐ท, ๐ถFG๐ต [10, 21], the drain current of
FGMOS transistor in saturation region can be expressed as
๐ผ๐ท
=๐ฝ
2
(
๐
โ
๐=1
๐๐๐๐๐โ ๐๐)
2
, (4)
where ๐๐= ๐ถ๐/๐ถ๐, ๐ฝ is the transconductance, and ๐
๐stands
for the threshold voltage. In (4), it can be seen that by
C1
C1
Vin
C2
C2
VSS
VDD
V1
V2C
C
Iout
CB
CBVC
VB
VB
M1
M2M3
M4
Figure 2: Proposed differential squarer.
Table 1: Aspect ratios of the transistor of the proposed circuit.
Transistor ๐ (๐m) ๐ฟ (๐m)M1-M2 4.4 0.18M3-M4 0.54 0.18
choosing proper values of multiple input voltages along withcapacitance ratio the threshold voltage term can be cancelledso as to get the perfect squarer equation.The proposed circuitutilizes this property of FGMOS transistor to implement thesquarer function.
3. Proposed FGMOS BasedDifferential Squarer
The proposed differential squarer is shown in Figure 2. It isconstructed by FGMOS based squarer (M1, M2) and linearvoltage attenuator (M3,M4).The squarer function is obtainedby taking the advantage of FGMOS square law characteristicsin saturation region. ๐
๐ตand ๐in are bias and signal voltages
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ISRN Electronics 3
Table 2: Comparison of various conventional and proposed squarers.
Parameters [12] [13] ProposedTechnology (๐m) 1.2 0.5 0.18Supply voltage (V) 1.5 ยฑ2.5 ยฑ0.75Number of transistors 11 MOS 6 MOS 4 FGMOSPower dissipated (๐W) NA NA 15Input signal range (๐PP) 0.26 1.5 0.75Attenuation factor (๐ผ) NA NA 1/4
FGMOS capacitances (fF) NA NA ๐ถ๐ต = 432, ๐ถ = 144๐ถ1= ๐ถ2= 100
Bias voltages (V) NA NA ๐๐ถ = โ0.25๐๐ต= 0.75
C1
R1VF
C2
R2
R0
CFGB
Figure 3: Simulation model of FGMOS.
applied at the two inputs of FGMOS transistor M1 andM2. Ifthe input voltage๐in is positive,M2 is offwhileM1 operates insaturation region and if the input voltage ๐in is negative, M1is off while M2 operates in saturation region.
The output current of the squarer (neglecting the parasiticcapacitances, channel-length modulation, mobility degrada-tion, and the body effect) is given by
๐ผout =๐ฝ1
2
(๐1๐inS1 + ๐2๐BS1 โ ๐๐1)
2, if ๐in > 0 (5)
๐ผout =๐ฝ2
2
(๐1๐BS2 + ๐2๐inS2 โ ๐๐2)
2, if ๐in < 0. (6)
If ๐ฝ1
= ๐ฝ2
= ๐ฝ, ๐๐1
= ๐๐2
= ๐๐, ๐1
= ๐2
= ๐, and๐๐๐ต
= ๐๐, then the output current of the squarer can be
approximated as
๐ผout =๐ฝ
2
(๐๐in)2. (7)
The input voltage๐in of the squarer is generated by voltageattenuator formed by FGMOS transistor M3 and M4. Theoutput voltage of the attenuator is given by [18]
๐in = ๐ผ (๐1 โ ๐2) +๐๐SS โ ๐๐ต๐๐ถ
๐ + ๐๐ต
, (8)
where ๐ = ๐ถ/(๐ถ + ๐ถ๐ต), ๐๐ต= ๐ถ๐ต/(๐ถ + ๐ถ
๐ต) are the capacitive
coupling ratio and ๐ผ = ๐/(๐ + ๐๐ต) is the attenuation factor
which can be adjusted by choosing proper values of ๐ and ๐๐ต.
From (8), it can be seen that the offset voltage term (๐๐SS โ๐๐ต๐๐ถ)/(๐ + ๐
๐ต) can be cancelled by choosing proper value
of bias voltage ๐๐ต. For zero output offset, the bias voltage ๐
๐ถ
must be equal to
๐๐ถ=
๐
๐๐ต
๐SS. (9)
Assuming zero-output offset for the voltage attenuatorand combining (7) and (8), the output current of the squareris modified as
๐ผout =๐ฝ
2
{๐๐ผ (๐1โ ๐2)}2. (10)
If ๐๐ผ = ๐eq, then (10) can be written as
๐ผout =๐ฝ
2
{๐eq (๐1 โ ๐2)}2
. (11)
From the above equation, it can be seen that the proposedsquarer gives the output current proportional to the differ-ence of input voltages ๐
1and ๐
2and The voltage range of
input signals can be determined by the factor ๐eq.
3.1. Second Order Effects. The operation of squarer has beenanalyzed by neglecting the deviations from ideal square-law characteristics due to parasitic capacitance and mobilitydegradation. These nonideal effects are the basic source ofdiscrepancy between the ideal and simulated output currentsof the proposed squarer.
3.1.1. Parasitic Capacitance. Parasitic capacitances have aminor effect on the squarer operation. The modified currentequation after considering the parasitics is given by
๐ผout =๐ฝ
2
(๐eq (๐1 โ ๐2) +๐ถGD๐ถ๐
๐DS +๐ถGB๐ถ๐
๐BS)2
. (12)
The ratios ๐ถGD/๐ถ๐ and ๐ถGB/๐ถ๐ can be neglected if thetransistors are operating in saturation mode [21]. Therefore,the parasitic capacitances do not contribute significantly tothe squarer operation andhave only a small effect on the inputrange.
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400.0
200.0
0.0
โ200.0
โ400.0
โ750.0 โ500.0 โ250.0 0.0 250.0 500.0 750.0
Vin
(mV
)
V1 (mV)
V2 = โ0.75V
V2 = 0V
V2 = 0.375VV2 = 0.75VV2 = โ0.375V
(a)
V2 = โ0.75V
V2 = 0V
V2 = 0.375VV2 = 0.75VV2 = โ0.375V
โ750.0 โ500.0 โ250.0 0.0 250.0 500.0 750.0
V1 (mV)
I out
(๐A
)
15.0
12.5
10.0
7.5
5.0
2.5
0.0
(b)
Figure 4: (a) DC response of the attenuator; (b) DC response of the proposed squarer.
V1,V
2(V
)
1
0.5
0
โ0.5
โ1
0.0 100 200 300 400 500
Time (๐s)
(a)
Time (๐s)
1.4
1.2
1.0
0.8
0.6
0.0 100 200 300 400 500
I out
(๐A
)
(b)
Figure 5: (a) Waveform of input signals ๐1and ๐
2; (b) transient response.
3.1.2. Mobility Degradation. Considering the mobilitydegradation effect, the ๐ผ-๐ characteristic of NMOS transistorcan be modelled by
๐ผ๐ท
=
(๐ฝ/2) (๐GS โ ๐๐)2
1 + ๐ (๐GS โ ๐๐), (13)
where ๐ is mobility degradation parameter which has a valueof about 0.1โผ0.001 Vโ1. According to the above equation, theoutput current of the squarer can be modified as
๐ผout =๐ฝ
2
{๐eq (๐1 โ ๐2)}2
[1 โ ๐ {๐eq (๐1 โ ๐2)}
+ ๐2{๐eq (๐1 โ ๐2)}
2
]
(14)
๐ผout =๐ฝ
2
{๐eq (๐1 โ ๐2)}2
+ ๐, (15)
where the output current error of the squarer can be given by
๐ = โ๐ฝ
2
๐{๐eq (๐1 โ ๐2)}3
[1 โ ๐ {๐eq (๐1 โ ๐2)}] . (16)
From the above equation, it can be seen that total harmonicdistortion due to mobility degradation will be negligiblebecause of small value of mobility degradation parameter.
4. Simulation Results
The designed circuits are simulated using Cadence Spectresimulator in TSMC 0.18 ๐mCMOS technology using ยฑ0.75V
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ISRN Electronics 5I o
ut/(V1โV2) (
dB)
โ102.5
โ105.0
โ107.5
โ110.0
โ112.5
โ115.0
100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
Figure 6: Frequency response of the proposed squarer.
power supply. The aspects ratios of the transistors of theproposed circuits are given in Table 1. Since the floating gate(FG) of FGMOS does not have any connection to ground,the simulator cannot understand the floating gate and reportsdc convergence problem during simulation. To avoid dcconvergence error during simulation model suggested in [10]has been used in this work.Thismodel is based on connectinglarge value resistors in parallel with the input capacitorsas shown in Figure 3. In this model, the relation betweenresistances and capacitances can be given as follows: ๐
๐=
1/๐๐ถ๐= 1000Gฮฉ.
The DC response of the attenuator and squarer against๐1
with ๐2varying from โ0.75V to 0.75V is shown in Figures
4(a) and 4(b), respectively. It can be seen from the curvesthat the output voltage of attenuator varies from โ320mVto 320mV and the maximum value of the output currentof the squarer is approximately 12 ๐A. The proposed squareroperates at low supply voltage with total power consumptionof 15 ๐Wonly.The transient response of the squarer is shownin Figure 5. Figure 5(a) shows that๐
1and๐2are the two input
sinusoidal signals with amplitude 0.75V and 0.25V peak-to-peak, respectively, and frequency 5 kHz and the outputcurrent is shown in Figure 5(b). The frequency response ofthe proposed squarer with ๐
1= 1mV is shown in Figure 6. It
can be seen from the figure that the proposed squarer exhibitsthe bandwidth of 199.426MHz.The performance parametersof the proposed circuit and various conventional circuitsare compared in Table 2. It can be seen that the proposedconfiguration has the lowest transistor count, operates at lowsupply voltage, and also has low DC power consumption.
5. Conclusions
In this paper, novel differential voltage squarer based onsimple FGMOS squarer and voltage attenuator has beenproposed. The proposed circuit operates at ยฑ0.75V withmaximum power consumption of 15๐W and bandwidth of199.426MHz. The circuit can process differential signal andhence it can be useful in various low voltage lowpower analogsignal processing/generating applications.
Conflict of Interests
The authors declare that there is no conflict of interestsregarding the publication of this paper.
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