research article impact of split gate in a novel soi...

Hindawi Publishing CorporationJournal of EngineeringVolume 2013, Article ID 307451, 6 pageshttp://dx.doi.org/10.1155/2013/307451

Research ArticleImpact of Split Gate in a Novel SOI MOSFET(SPG SOI) for Reduction of Short-Channel Effects:Analytical Modeling and Simulation

Mohammad K. Anvarifard and Ali A. Orouji

Electrical Engineering Department, Semnan University, Semnan, Iran

Correspondence should be addressed to Mohammad K. Anvarifard; [email protected]

Received 6 October 2012; Revised 15 January 2013; Accepted 23 January 2013

Academic Editor: Daniela Munteanu

Copyright © 2013 M. K. Anvarifard and A. A. Orouji. This is an open access article distributed under the Creative CommonsAttribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work isproperly cited.

In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET)is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. Inthe proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated thatthe surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs,hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analyticalmodel is verified byATLAS device simulation software.The obtained results of themodel are comparedwith those of the single-gate(SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.

1. Introduction

In recent years the silicon-on-insulator metal oxide semi-conductor field effect transistors (SOI MOSFETs) have beenregarded as good counterpart with respect to other semicon-ductor devices in VLSI/ULSI technology. With progress insemiconductor device technology, the device scales shrinksto submicrometer regime. When channel length shrinks tosubmicrometer, undesirable effects which are named short-channel effects (SCEs) will be explored. These effects occurbecause controllability of the gate over-channel is reduced byshrinking the channel length.

Thin-film fully depleted SOI MOSFETs have supe-rior electrical characteristics than the bulk MOS devices,such as reduced junction capacitances, excellent latchupimmunity, increased channel mobility, and reduced short-channel effects (SCEs) [1]. However, when the channel lengthbecomes smaller than 100 nm, SCEs will occur [2]. By usingstructures such as dual material gates, multiple gates, andfin field-effect transistors (FINFETs), short-channel effectsdecrease [3–5]. The scaling of SOI MOSFETs has beeninvestigated, and several SOI structures have been studied in

terms of a natural length scale [6]. An analyticalmodel for thethreshold voltage of short-channel single-gate SOIMOSFETshas been derived with considering the two-dimensional(2D) effects in both SOI and buried-oxide layers [7]. Thepotential distribution has been investigated in multiple-gate SOI MOSFETs [8]. A threshold voltage model of amesa-isolated SOI MOSFET based on an analytical solutionof the three-dimensional (3D) Poisson’s equation has beenpresented [9].The separation of variables technique is used toanalytically solve the 3D Poisson’s equation with appropriateboundary conditions. The SCEs can be reduced using aninversion layer as an ultrashallow source/drain (S/D) inthe sub-50 nm regime [10–16]. An analytical model of thesurface potential and threshold voltage of a SOI MOSFETwith electrically induced shallow S/D junctions has beenpresented to investigate the SCEs [17]. The effectivenessof the dual-martial-gate (DMG) structure in fully depletedSOI MOSFETs has been investigated to suppress SCEs bydeveloping a 2D analytical model of surface potential andthreshold voltage [18]. Also references such as [19–21] havepresented new devices to suppress the short-channel effectwell.

2 Journal of Engineering

In this paper the split-gate transistor is proposed to reduceSCEs. In this structure the gate is spilt into two parts with asmall gap between them. Indeed the proposed structure is likethe DMG-SOI [18] but by a new idea. In our structure, thevoltage difference between the gates will control the channelwell. In this study, a SPG SOI transistor with different gatebiases is considered and also an analytical model is developedto investigate the transistor performance. The model is usedto calculate the surface potential distribution in the lowerSOI thin film of two the gates and to investigate the exclusivecharacteristics of the SPG structure in suppressing SCEssuch as the hot-carrier effect, DIBL, and threshold voltage(𝑉TH) roll-off in SOI MOSFETs. Also this model providesan efficient tool for design and characterization of the novelSPG MOSFETs. The obtained results of analytical model areverified by ATLAS software [22]. Two-dimensional numer-ical simulations of the proposed structure are done withATLAS simulator. In addition to Poissons, and drift/diffusionequations, SRH (Shockley-Read-Hall) and Auger models areconsidered for generation/recombination, and also IMPACTSELB for impact ionization. These simulation methods allowtaking into account carrier velocity saturation, carrier-carrierscattering in the high doping concentration, and constantmobility.

2. Analytical Model

A cross-section view of a fully depleted SPG SOI MOSFET isillustrated in Figure 1 with two gates,𝐺

1and𝐺

2, of lengths 𝐿

1

and 𝐿2, respectively.There is a small gap of length𝑍 between

the gates. We assume that the impurity density in the channelregion is uniform, and the effects of charge carriers and fixedoxide charges on the electrostatics of the channel can beneglected. With these assumptions the potential distributionin the silicon thin film before the onset of strong inversioncan be written as

𝑑2𝜙 (𝑥, 𝑦)

𝑑𝑥2+

𝑑2𝜙 (𝑥, 𝑦)

𝑑𝑦2=

𝑞𝑁𝐴

𝜀Si, for 0 ≤ 𝑥 ≤ 𝐿,

0 ≤ 𝑦 ≤ 𝑡Si,

(1)

where 𝑁𝐴is the silicon film doping concentration, 𝜀Si is the

dielectric constant of silicon, 𝑡Si is the film thickness, and 𝐿is the device channel length. If the channel length, siliconthickness, and oxide gate thickness become very small, thenthe current analytical approach is not true, and the quantummodels must be regarded. Also silicon thickness must not beverymuch because the structure is fully depleted. Also higherdoping in source/drain is not very critical because the channelunder the gate is very important for the structures usually.

The potential profile in the vertical direction, that is, the𝑦-dependence of 𝜙(𝑥, 𝑦) can be approximated by a simpleparabolic function as proposed by Young for fully depletedSOI MOSFETs [23]:

𝜙 (𝑥, 𝑦) = 𝜙𝑆(𝑥) + 𝑐

1(𝑥) 𝑦 + 𝑐

2(𝑥) 𝑦2, (2)

where 𝜙𝑆(𝑥) is the surface potential and the arbitrary coeffi-

cients 𝑐1(𝑥) and 𝑐

2(𝑥) are functions of 𝑥 only. Since the gap

𝑀1 𝑀2

𝐿1 𝐿2 𝑡𝑓

𝑡𝑏

𝑥

𝑦

SUB

P substrate

Buried oxide

S D

n+ n+𝑡Si

Figure 1: Cross-sectional view of an n-channel fully depleted SPGSOI MOSFET.

length (𝑍) is extremely small, we assume that the potentialdistribution in the region of 𝐿

1≤ 𝑥 ≤ 𝐿

1+ 𝑍 and 0 ≤ 𝑦 ≤ 𝑡Si

(under the gap) for each 𝑦 is a linear function of 𝑥. At 𝑦 = 0,this potential distribution in region of 𝐿

1≤ 𝑥 ≤ 𝐿

1+𝑍 reads

𝜙3(𝑥, 0) = 𝑎

1𝑥 + 𝑏1, (3)

where the coefficients 𝑎1and 𝑏

1are constant values. Since

we just need the potential at 𝑦 = 0, (3) is true. Because ofthe same gate metals, the work functions of the two gates areequal. Therefore, the flat-band voltages for the two gates arethe same:

𝑉FB = 𝜙𝑀 − 𝜙𝑆. (4)

The semiconductor work function can be written as

𝜙𝑆= 𝜒Si +

𝐸𝑔

2𝑞+ 𝜙𝐹. (5)

𝜙𝐹

= 𝑉𝑇ln(𝑁𝐴/𝑛𝑖) is the Fermi potential. 𝐸

𝑔is the silicon

band gap. 𝜒Si is the electron affinity.𝑉𝑇 is the thermal voltage.𝑛𝑖is the intrinsic carrier concentration.In the SPG SOI structure, the potential under the gates

can be written as

𝜙1(𝑥, 𝑦) = 𝜙

𝑆1(𝑥) + 𝑐

11(𝑥) 𝑦 + 𝑐

12(𝑥) 𝑦2, for 0 ≤ 𝑦 ≤ 𝑡Si,

0 ≤ 𝑥 ≤ 𝐿1,

𝜙2(𝑥, 𝑦) = 𝜙

𝑆2(𝑥) + 𝑐

21(𝑥) 𝑦 + 𝑐

22(𝑥) 𝑦2,

for 𝐿1+ 𝑍 ≤ 𝑥 ≤ 𝐿

1+ 𝐿2+ 𝑍,

0 ≤ 𝑦 ≤ 𝑡Si.

(6)

Poisson’s equation is solved separately under the two gatesusing the following boundary conditions.

Journal of Engineering 3

(1) The electric flux at the gate/front oxide interface iscontinuous for both gates:

𝑑𝜙1(𝑥, 𝑦)

𝑑𝑦

𝑦 = 0

=𝜀ox𝜀Si

𝜙𝑆1

(𝑥) − 𝑉

GS1𝑡𝑓

, for 𝐺1, (7)


𝑑𝑦

𝑦 = 0

=𝜀ox𝜀Si

𝜙𝑆2

(𝑥) − 𝑉

GS2𝑡𝑓

, for 𝐺2, (8)

where 𝜀ox is the dielectric constant of the oxide, 𝑡𝑓 is the gateoxide thickness,𝑉GS1 = 𝑉GS1−𝑉FB,𝑓, and𝑉

GS2 = 𝑉GS2−𝑉FB,𝑓.Note that 𝑉GS1 is the gate (𝐺1)-source bias voltage, 𝑉GS2

is the gate (𝐺2)-source bias voltage, and 𝑉FB,𝑓 is the flat band

voltage of 𝐺1and 𝐺

2.

(2) The electric flux at the interface of the buried oxideand back-channel silicon is continuous for both gates:


𝑑𝑦

𝑦 = 𝑡Si

=𝜀ox𝜀Si

𝑉

SUB − 𝜙𝐵 (𝑥)

𝑡𝑏

, for 𝐿1, (9)


𝑑𝑦

𝑦 = 𝑡Si

=𝜀ox𝜀Si

𝑉

SUB − 𝜙𝐵 (𝑥)

𝑡𝑏

, for 𝐿2, (10)

where 𝑡𝑏is the buried-oxide thickness and 𝜙

𝐵(𝑥) is the poten-

tial distribution along the back-side oxide-silicon interface.𝑉

SUB = 𝑉SUB − 𝑉FB,𝑓. 𝑉SUB is the substrate bias and 𝑉FB,𝑏 isthe back-channel flat-band voltage. 𝑉SUB is set to 0V.

(3) The surface potential at the interface of the two gatesand the gap is continuous:

𝜙1(𝐿1, 0) = 𝜙

3(𝐿1, 0) , 𝜙

2(𝐿1+ 𝑍, 0) = 𝜙

3(𝐿1+ 𝑍, 0) .

(11)

(4) The electric flux at the interface of the two gates andthe gap is continuous:

𝑑𝜙1(𝑥, 0)

𝑑𝑥

𝑥 = 𝐿1=

𝑑𝜙3(𝑥, 0)

𝑑𝑥

𝑥 = 𝐿1,

𝑑𝜙2(𝑥, 0)

𝑑𝑥

𝑥 = 𝐿1 + 𝑍=

𝑑𝜙3(𝑥, 0)

𝑑𝑥

𝑥 = 𝐿1 + 𝑍.

(12)

(5) The potential at the source end is

𝜙1(0, 0) = 𝜙

𝑆1(0) = 𝑉bi. (13)

(6) The potential at the drain end is

𝜙2(𝐿1+ 𝐿2+ 𝑍, 0) = 𝜙

𝑆2(𝐿1+ 𝐿2+ 𝑍) = 𝑉bi + 𝑉DS. (14)

𝑉bi = (𝐸𝑔/2) + 𝑉𝑇 ln(𝑁𝐴/𝑛𝑖) is the built-in potential acrossthe body-source junction.

The constants 𝑐11(𝑥), 𝑐12(𝑥), 𝑐21(𝑥), and 𝑐

22(𝑥) in (6) can

be obtained from the boundary conditions in (7)–(10). Withsubstituting these values in (6) and then in (1), we obtain

𝑑2𝜙S2 (𝑥)

𝑑𝑥2− 𝛼𝜙S2 (𝑥) = 𝛽2,

𝑑2𝜙S1 (𝑥)

𝑑𝑥2− 𝛼𝜙S1 (𝑥) = 𝛽1,

(15)

where

𝛼 = 2𝑎13

𝑎11

, 𝛽1= 𝑞

𝑁𝐴

𝜀Si− 2

𝑎12

𝑎11

,

𝛽2= 𝑞

𝑁𝐴

𝜀Si− 2

𝑎21

𝑎11

, 𝑎11

= 2𝑡Si +𝜀ox𝜀Si𝑡𝑏

𝑡2

Si,

𝑎12

=𝜀ox𝜀Si𝑡𝑏

𝑉

SUB +𝜀ox𝜀Si𝑡𝑓

(1 +𝜀ox𝑡Si𝜀Si𝑡𝑏

)𝑉

GS1,

𝑎13


+𝜀ox𝜀Si𝑡𝑓


) ,

𝑎21


𝑉

SUB +𝜀ox𝜀Si𝑡𝑓


)𝑉

GS2.

(16)

𝜙𝑆1(𝑥) and 𝜙

𝑆2(𝑥) are obtained by solving the differential

equations in (15). Finally, the surface potential distribution isobtained as

𝜙𝑆1

(𝑥) = 𝐴 exp (𝜆𝑥) + 𝐵 exp (−𝜆𝑥) −𝛽1

𝛼, (17)

𝜙𝑆2

(𝑥) = 𝐶 exp {𝜆 [𝑥 − (𝐿1+ 𝑍)]}

+ 𝐷 exp {−𝜆 [𝑥 − (𝐿1+ 𝑍)]} −

𝛽2

𝛼,

(18)

𝜙𝑆3

(𝑥) = 𝜙3(𝑥, 0) = 𝑎

1𝑥 + 𝑏1, (19)

where 𝜆 = √𝛼 and 𝜆1= −𝜆2= 𝜆.

By use of the boundary conditions in (11)–(14) and (17)–(19), we reach a system of six equations and unknowns.

The constant coefficients 𝐴, 𝐵, 𝐶, 𝐷, 𝑎1, and 𝑏

1are calcu-

lated by solving this system of six equations and unknowns.The surface potential along the channel can be calculatedwiththe help of these variables.

The electric field along the channel determines the elec-tron transport velocity. The electric field components in the𝑥-direction, under the 𝐺

1, 𝐺2, and the gap, are given as

𝐸1(𝑥) =

𝜕𝜙𝑆1

(𝑥)

𝜕𝑥

𝑦 = 0

= 𝐴𝜆1exp (𝜆

1𝑥) − 𝐵𝜆

1exp (−𝜆

1𝑥) , 0 ≤ 𝑥 ≤ 𝐿

1,

𝐸2(𝑥) =

𝜕𝜙𝑆2

(𝑥)

𝜕𝑥

𝑦 = 0

= 𝐶𝜆2exp (𝜆

2(𝑥 − (𝐿

1+ 𝑍)))

− 𝐷𝜆2exp (−𝜆

2(𝑥 − (𝐿

1+ 𝑍)))

𝐿1+ 𝑍 ≤ 𝑥 ≤ 𝐿

1+ 𝐿2+ 𝑍,

𝐸3(𝑥) =

𝜕𝜙𝑆3

(𝑥)

𝜕𝑥

𝑦 = 0= 𝑎1, 𝐿

1≤ 𝑥 ≤ 𝐿

1+ 𝑍.

(20)


Table 1: Parameters for simulation of two transistors (SPG and SGtransistors).

Parameter ValueGate length, 𝐿

1100 nm

Gate length, 𝐿2

100 nmFront-gate oxide thickness, 𝑡

𝑓5 nm

Back-gate oxide thickness, 𝑡𝑏

5 nmSilicon film thickness, 𝑡Si 12 nmGap length, 𝑍 10 nmBody doping, 𝑁

𝐴6 × 1016 cm−3

Source/drain doping, 𝑁𝐷

1 × 1020 cm−3

Gate metal work function, WF 4.5 evVoltage difference 0.75VGate-(𝐺

1-) to source voltage, 𝑉GS1 0.15 V

Gate-(𝐺2-) to source voltage, 𝑉GS2 0.9V

Substare voltage, 𝑉SUB 0V

3. Simulation Results and Comparison withAnalytical Results

It is important that each analytical model applied in thedevices must be verified by simulation software. Therefore inthis paper the analytical model and simulation results havebeen brought and compared.

In all simulations,𝑍 (gap length) is assumed to be 0.01 𝜇mand the channel length is 𝐿 = 𝐿

1+ 𝐿2+ 𝑍.

To verify our analytical model, the ATLAS device simula-tion software has been used to simulate the surface potentialdistribution within the silicon thin film. A fully depleted(FD) n-channel SPG SOI structure is implemented in ATLAShaving uniformly doped source/drain and body regions.

In this study the voltage difference between the two gatesis assumed to be 0.75V, that is, 𝑉GS2 − 𝑉GS1 = 0.75V.This voltage difference can be obtained by a normal diode.In Table 1 parameters needing simulation of two transistors(SPG and SG transistors) have been listed.

In Figure 2, the surface potential profile has been plottedalong the horizontal distance 𝑥 in the channel for a channellength 𝐿 = 0.21 𝜇m (𝐿

1= 0.1, 𝐿

2= 0.1, and 𝑍 = 0.01 𝜇m)

at different biases. It can be seen from this figure that, in theSPG structure, there is no significant change in the potentialunder the gate𝐺

1as the drain bias is increased.Therefore the

channel region under 𝐺1is “screened” from the changes in

the drain potential, that is, the drain voltage is not absorbedunder 𝐺

1. The DIBL effect can be demonstrated by plotting

the surface potential minimum as a function of the positionalong the channel for different drain bias conditions. It isevident from the figure that the shift in the point of thepotential minimum is almost zero. This is a clear proof thatthe DIBL effect is considerably reduced for the SPG SOIMOSFET.

As shown in Figure 2, theATLAS simulation results verifythe accuracy of our proposed analytical model.

In Figure 3, the electric field distributions along thechannel near the drain are shown for SPG and SG SOIMOSFETs with a channel length 𝐿 = 0.21 𝜇m (𝐿

1= 0.1,

00 0.1 0.2

0.5

1

1.5

2

2.5

3

Position in channel (𝜇m)

Surfa

ce p

oten

tial (

volts

)

ATLASModel

𝑉DS = 1.75 V

𝑉DS = 0.95 V

0.25 V𝑉DS =

−0.1

Figure 2: Surface channel potential profiles along the channel atchannel length 𝐿 = 0.21 𝜇m.

0

0.5

0.15 0.17 0.19 0.21 0.23

1

1.5

2

2.5

3

Position in channel (𝜇m)

Elec

tric

fiel

d (M

V/c

m)

ATLAS (SPG)Model (SPG)ATLAS (SG)

𝑉DS = 1.75 V

Figure 3: Longitudinal electric field along the channel at channellength 𝐿 = 0.21 𝜇m.

𝐿2

= 0.1, and 𝑍 = 0.01 𝜇m). As shown in this figure, thepeak electric field at the drain end for the SPG SOI MOSFETis less than that for the SG SOI MOSFET. It is evident fromthis figure that the presence of a voltage difference between𝐺

1

and𝐺2reduces the peak electric field considerably.Therefore

hot-carrier effect in SPG SOI MOSFET is less than that forthe SG SOI MOSFET. The results of the analytical model arein close proximity with the ATLAS simulation results.

Figure 4 shows the surface potential profiles along thechannel position for different gate length ratios of 𝐿

1to 𝐿2

(𝐿1/𝐿2). The sum of the channel length (𝐿

1+ 𝐿2+ 𝑍) is

constant. As shown in the figure, by reducing the length

Journal of Engineering 5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Surfa

ce p

oten

tial (

volts

)

0 0.1 0.2Position in channel (𝜇m)

ATLASModel

−0.1

𝐿1/𝐿2 = 0.08/0.12

𝐿1/𝐿2 = 0.10/0.10

𝐿1/𝐿2 = 0.12/0.08

Figure 4: Variation in surface potential with position in channel fordifferent combinations of gate lengths 𝐿

1and 𝐿

2. The sum (𝐿

1+ 𝐿2)

is constant.

0.20.2

0.4

0.4

0.6

0.6

0.8

0.8

1

0Channel length (𝜇m)

Min

imum

surfa

ce p

oten

tial (

volts

)

ATLAS (SPG)ModelATLAS (SG)

= 20nm

= 12nm𝑡Si

𝑡Si

Figure 5: Variation in the minimum potential with constant 𝐿1

=

50 nm.

𝐺1, the position of the potential minimum shifts toward the

source. This causes the peak electric field in the channel toshift toward the source end and thus results in amore uniformelectric field profile in the channel. This redistributes thesurface potential, which results in a more uniform potentialalong the channel. Note that 𝐿

1cannot be reduced to a very

small value, since in the case of𝐿1≈ 0, we have a SG transistor

with a gate bias that is higher than the applied gate bias 𝑉GS1.This higher gate bias reduces 𝑉TH to a very small value andtherefore increases the off current.

In Figure 5 the variations in potential minimum as afunction of the channel length 𝐿 with constant 𝐿

1= 50 nm

0.6

0.55

0.5

0.45

0.4

0.3

0.35

0 100 200 300 400 500 600Channel length (𝜇m)

Thre

shol

d vo

ltage

(vol

ts)

ATLAS (SPG)ATLAS (SG)

𝑉DS = 0.05V

Figure 6: Threshold voltage versus channel length.

for fully depleted SPG and SG SOI MOSFETs with siliconfilm thicknesses 𝑡Si = 12 and 20 nm are shown. In the caseof the SPG SOI MOSFET, the dependence of the potentialminimum on the silicon thin-film thickness reduces withdecreasing 𝑡Si. This is due to the existence of a voltagedifference between the two gates in SPG structure. Thevalidity of model for the surface potential minimum underthe gate for different combinations of 𝐿

1and 𝐿

2is verified by

ATLAS simulation results.In Figure 6 the threshold voltage𝑉TH has been shown as a

function of the channel lengthwith constant𝐿1= 25 nm.𝑉TH

was obtained for two structures SPG SOI MOSFET and SGSOI MOSFET with help of ATLAS simulator. The thresholdvoltage is extracted by calculating the maximum slope of the𝐼𝐷/𝑉𝐺curve, finding the intercept with the axis, and then

subtracting half of the applied drain bias [23].As shown in this figure, the variations in threshold voltage

𝑉TH for SPG SOI MOSFET are less than, those of the SG SOIMOSFET. Therefore DIBL is reduced in SPG SOI. Also wehave a desirable rollup in the threshold voltage with reducingchannel length for SPG SOI MOSFET. Note that when thethreshold voltage with shrinking channel length increases,off-current variations decreases, and this is a good benefit.But in the SG SOI MOSFET the threshold voltage decreases,with shrinking channel length. This results in increasing theoff-current variations in the SG SOI MOSFET structure.Therefore the performance of SPG SOI MOSFET is superiorto that in SG SOI MOSFET.

4. Conclusion

The impact of the split gate in fully depleted SOI MOSFETshas been examined to suppress SCEs by developing a 2-D analytical model for surface potential and by comparingthe results with ATLAS device simulation software. In theproposed transistor (SPG transistor) a voltage difference isintroduced between the two gates. In SPG structure, theshift in the surface channel potential minimum position is


negligible with increasing the drain bias. The electric field inthe channel at the drain end is reduced. Therefore the hot-carrier effect reduces. The DIBL effect in our transistor isreduced because the voltage difference between the two gatesis applied. In addition, the variation in the channel potentialminimum with decreasing film thickness in our transistoris less than that in the SG SOI MOSFET. Also we obtaineda desirable rollup in the threshold voltage with decreasingchannel length for SPG SOI MOSFET. All obtained resultsof analytical model have been verified by ATLAS simulationsoftware.These results show that the analytical model in SPGtransistor is completely proper and also the SPG transistorperformance is superior to that SG transistor.

References

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