2828

REPROGRAMMABLE LOGIC ARRAY USING M-R ELEMENTS

I.W. Ranmuthu, K.T.M. Ranmuthu A.V. Pohm, C.S. Comstock, M. Hassoun, M. Eray

Electrical and Computer Engineering Department Engineering Research Institute, Iowa State University

Ames, IA, 5001 1, USA

Abstract - A reprogrammable logic a r ray has been designed with features such as rapid infinite reprogrammability with a single power supply, non- volatile configuration storage and radiation hardness using magneto-resistive (MR) memories. A prototype layout was made for simulation and analysis. The results indicated that all the above features could be achieved along with an approximately 20 ns. delay time in the logic array structure using 2 prn CMOS. It was also discovered tha t the MR memory consumed only 10% - 15% of the die area.

INTRODUCTION

Magnetoresistive memories have shown to be non- volatile, to have short write times, to have no wear out, and to have non-destructive readability and random accessibility. These unique features of MR elements are fully utilized in the design of a reprogrammable logic array (RPLA).

The logic array is user configurable similar to a conventional PLA. However, the configuration could be changed rapidly in this RPLA, even when on board. The rapid reprogrammability reduces the programming time and provides complete testability without having to use random testing. This is achieved by using semiconductor storage elements along with cross points in the logic array. These storage elements are MOS semiconductor latches containing the state of an associated cross point. These latches are loaded from a non-volatile MR memory on power up. An exact image of the cross point configuration is maintained in the MR memory so in case of a power loss the configuration will be preserved (Fig I).

The RPLA basically has three modes of operation; namely, power up mode, write mode and normal operation mode. In power up mode, the information stored in the MR memory is loaded into the semiconductor memory. The addresses required are generated by a counter which is fed with a lMHz clock. In write mode, the user can reprogram the RPLA, and this mode is selected by asserting WRITE/PITA pin of the RPLA chip low. The user then feeds the data and the location address where the data is intended. This data could be fed asynchronously and it is stored in the MR memory as well as in the semiconductor memory. In normal operation mode, the RPLA operates as a normal PLA.

i I I

FIG. 1 RPLA BLOCK DIAGRAM

---+---

I --J Cross Point

Col 1%

Row

T2 B i t Inv

d Word

FIG. 2 CROSS POINT AND SRAM CELL

001 8-946419010900-2828$0 1 .OO Q 1990 IEEE

2829

LOGIC DESIGN

To demonstrate this design a prototype chip was layout. This chip had the configuration of a 6 input x 16 product terms x 4 outputs. The number of cross point required was (6 x 2 + 4) x 16 = 16 x 16; and a 16 x 16 array of cross point cells were designed with a' NOR-NOR configuration. The AND plane of this configuration had 12 x 16 cross point cells and the OR plane had 4 x 16 cross point cells. Each cross point cell contained a six transistor RAM cell as the storage element and a two transistor cross point (Fig. 2). When the SRAM contains a logic one and if the corresponding input to the array goes high, the horizontal product form line is pulled to logic zero. Since the chains of all cross point transistors need to be connected together to form a product term line, this introduced a large capacitance on the line. This in turn severely limited the switching speed of the cross point. To avoid this, each product term line was divided in two parts and they were ANDed together to form a complete product term line.

A control circuit controls the operation of the chip through all these modes. In power up mode the control circuit starts up the counter by gating the clock using a power up pulse. The data is transferred a bit at a time and each transfer takes only a microsecond, thus requiring a power up time of only 256 microseconds. During this power up time the current consumption is approximately 50 mA.

The addresses generated by the counter are decoded by a row and column decoder. The row decoder selects the word and bit lines in the cross point cell array to be connected to the incoming data. This data is generated by the sense amplifier in the MR interface (Fig. 1).

In write mode the data is written to the semiconductor and MR memories in a similar way. The control circuit selects this data (instead. of that from MR memory) to be the user supply data. In this mode the output of the counter is also disabled. The write time is low for both memories in the order of 100 nanoseconds, and does not require any clocking.

DESIGN CONSIDERATIONS FOR M-R MEMORY

A magneto resistive memory uses the magneto resistive effect to read the state of the memory cell. Magneto resistance is the change in resistance of a magnetic material when subjected to a magnetic field. This resistance is dependent on the direction of magnetization.

The MR memory cell is of a sandwich structure with orthoganal sense lines and word lines to provide a magnetic field for switching (Fig. 3). When writing to the element the sense currents provide the easy direction magnetic field which determine the state of the bit stored and the word current lowers the threshold to allow switching [l]. To read from a MR element, the sense current is supplied in a specific direction (determined by domain) along with word current which causes a rotation of the magnetization. This changes the resistance of the element along the sense lines depending on the state of the bit stored. This is reflected as a change in voltage across the element. This change in voltage vs. word field which is proportional to word current is shown in Fig. 4.

Word Line On Top

SenselDigit Line

- Thin

v' Word . I . I Current

F I G . 3 A M-R MEMORY ELEMENT

/I Hs = 6 0 e

3.04 - A

2.20 Resultant -

\ \ > '

E '. 1.52 - '

(0)

0.00 I I -15 -12 -9 -6 -3 0 + 3 + 6

Word Field in Oe

F I G . 4 M-R ELEMENT RESPONSE

Figure 5 depicts the sense line arrangement and the sensing technique used in a representative test of the MR memory array. Four MR elements are strung together in series to form a sense line. In the case of a read or write to this MR memory, the sense line to be activated is selected by the switching transistors in the middle (Fig. 5) . The sense current direction is selected by transistors Tt,T2,T3,T4. The change in voltage due to MR effect is observed from center points X, Y and 2 (Fig. 5 ) of the sense lines. For actual elements with center points X, these voltages are multiplexed such that when a particular sense line is selected the corresponding multiplexer transistor is turned on.

In the structure examined, small memory cells were used to minimize the MRAM area. As a consequence the signal levels were in the millivolt range and the sensing circuits had to be designed with care. In designing sensing circuit thermal noise voltage drift due to thermal effects and the voltage offset due to manufacturing variations had to be taken into account. When the elements heat up, the voltage at point X (Fig. 5 ) tends to drift, hence sensing a change of voltage at X with respect to a fixed reference voltage cannot be done. To avoid this, two dummy lines,

2830

one storing a logic one and the other storing a logic zero are used. A resultant voltage (Fig. 4) of voltages at z and y of the two dummy lines (Fig. 5 ) is obtained. Since heating affects the dummy lines in a similar manner to the actual] sense lines, the voltage difference between the resultant voltage and voltage from x (Fig. 5) due to heating effect could be minimized.

Because manufacturing differences, sense lines tend to have slightly different resistances which give rise to offset voltages. To zero out the offset voltage difference between actual sense line signal a t x and dummy line voltages from y and z, an auto-zero circuit is used.

The technique used in this auto zero circuit is to first apply the sense current without the word current and store the voltage difference between the selected sense line and the dummies, which amount to approximately the voltage deference due to to changes in resistance. Then the negative word current is applied and above voltage difference is subtracted from the new output giving the actual voltage change due to MR effect.

Signal Output = approximately 1 mV

This voltage MR signal is amplified by a differential amplifier to full logic levels.

CONCLUSIONS

The prototype layout was successfully simulated and the sense amplifier reliably detected simulated stored bits subjected to all errors and offsets arising from temperature and manufacturing inconsistencies. The logic array of RPLA showed a delay less than 20 ns. with two micron technology. Finer lithography obviously would reduce the delay. The CMOS circuitry used in logic array, sense amplifier and sense current supply was fully compatible with a single five volt supply. The area of the die came up to 1800x 1800micron2 with two micron technology. With 1.2 micron technology this could be further reduced to 1100 x 1100 micron*. It was also shown that the MR memory increases the die area by only 1Wo- 15%. Thus MR RPLAS provide integrated circuits which quickly and indefinitely reprogrammable without the use of special circuitry or supplies at a very little additional cost. Also, because of the small area occupied by MRAM, longer memory elements can be used with larger outputs to further reduce the power up cross point loading times.

ACKNOWLEDGEMENTS

Teresa Warren for typing the manuscript. The authors would like to thank Jeanne Cacavas and

VDD 4 Actual Sense Dummy Lines Lines

T i ) k D - - I I

REFERENCES

A.V. Pohm, J.M. Daughton, C.S. Comstock, H.Y. Yoo, “Threshold Properties of 1, 2 and 4 Micron Multilayer Magneto-Resistive Memory Cells,” I.E.E.E.. Trans. on Map.,Vol. Mag-23, Nov. 5, 1987.

A.V. Pohm, J.S.T. Huang, J.M. Daughton, D.R. Krahnm, V. Mehra, “The Design of a 1M Bit Non- Volatile M-R Memory Chip Using 1.5 x 5 Micron Cells,” Fourth Joint MMM Intermae Conference, Vancouver, July 1988.

FIG. 5 SENSE LINE SELECTION AND AMPLIFIER