reliability capability evaluation model for highly ... · pdf filepackage leadframe packages...

WS on 3D SiP, ESREF 2012 Cagliari, Italy, October 1st, 2012,

Author: Hans-Jürgen AlbrechtCompany: Siemens AG, Corporate Technology, Corporate Research and Technologies,

CT RTC ELE EOM-DE

Email: [email protected]

Reliability capability evaluation model

for highly integrated packages


Overview

Outline•

Introduction

•

Package and assembly parameters•

3D packages / reliability requirements / application

•

Accelerated test conditions•

Physical experimental research

•

Emperical

research•

Collection and analyze data

•

Comparison of findings and requirements•

Outlook


More

Functionality

and Miniaturization

causeincreasing

integration

density

=> 3D will be

needed

Consequence: Increasing

Interconnect

density

Source: Pressel, Graz, 2012

9,34 mm

QFP ~ 5,5

13 mm

FCoB/ WLP fan in = 1

BGA ~ 2

Package form factor: Package area

chip area

CSP < 1,2

Stacks: could become <1 and external I/O no may be reduced

22 mm

3D with TSV allows further density increase

Package-on-Package (PoP)

9,34 mm

QFP ~ 5,5

13 mm13 mm

FCoB/ WLP fan in = 1

BGA ~ 2

Package form factor: Package area

chip area

CSP < 1,2

Stacks: could become <1 and external I/O no may be reduced

22 mm

3D with TSV allows further density increase

Package-on-Package (PoP)

PackagePackagePlatforms

QFPDSO

ProcessesThinning and DicingDie attachWire bondingFlip chip in PackageMoldingThin film technologyWLP processes…

Physics of PackageSignal IntegrityRF capability Heat dissipationReliability PhysicsFA incl. adhesionMiniaturisationPower

Methods/Cross Cut Needs

Co-design Simulation&ModelingBackend Design RulesTestAusbeute (Yield)Known Good DieStandards

Green Laminate substrates (xBGA )LeadframesDielektrikaFotoresists

LeadlessPackage

s

Laminate WLP = Wafer Level Packages (e.g. WLB = WL BGA)

System in Package

LeadframePackages

Integration enabler

QFNTSLP

BGA/SGA/LGARF-Modules

SG-WLBPG-eWLB

PackagePackage QFPDSO

Processes/EquipmentThinning and DicingDie attachWire bondingFlip chip in PackageMolding für eWLB Thin film technologyWLP processes…

Physics of PackageSignal IntegrityRF capability Heat dissipationReliability PhysicsFA incl. adhesionMiniaturisationPower

Methods/Cross Cut Needs

Co-design Simulation&ModelingBackend Design RulesTestAusbeute (Yield)Known Good DieStandards

Materials & Substrates Green Laminate substrates(xBGA )LeadframesDielektrikaFotoresists

LeadlessPackage

s

Laminate WLP = Wafer Level Packages(e.g. WLB = WL BGA)

LeadframePackages

IntegrationEnabler

QFNTSLP

BGA/SGA/LGARF-Modules

SG-WLBPG-eWLB

System inPackage

3D System Integration requires the reliable processes material, understanding of failure modes and testing capabilities

Higher

packaging

integration

needs

optimized

packages

in terms

of internal

strain

and stress.

First level-

and second level

reliability

evaluation

based

on the

progress

in the

project.


System-in-Package

tree

for

array

packages Front-end

and backend (Packaging) merge


>1 die

side-by-side

stacked die

µ-FlipChip

embedded

Thru Si via

PoP

Pack. on SiP

eWLB

MCM

Modulespassive integration

>2 dies

WB/ WB

FC/ WB

stacked package

face-to-face

Embedded power

Front‐end and Back‐end merge

>1 die

side-by-side

stacked die

µ-FlipChip

embedded

Thru Si via

PoP

Pack. on SiP

eWLB

MCM

Modulespassive integration

>2 dies

WB/ WB

FC/ WB

stacked package

face-to-face

Embedded power

Front‐end and Back‐end merge

Different constructional

parameters

and materials

implemented

with

well defined

internal

andexternal

interfaces

as the

input

for

the

„Reliability capability evaluation model for highly integrated packages”


Overview Source: IFX

Work

package

1Steering

activities, requirements

ESiP

has the

general

focus

on reliability, failure

analysis

and test, covering

a broad

variety

of technologies

and potential applications

in parallel.

ESiP-

work packages

Issues

and challenges

in 3D integration

Work

package

2First level

reliabilityWork

package

5

Second level reliabilty

Work

package

3Failure

analysisWork

package

4Probing

and test


Coherent

View

Chip-Package-Board: 1st and 2nd level

reliability

& Failure

Analysics

Chip-Package-Board interaction => new reliability challenges

1st level

reliability(Chip/Package) 2nd level

reliability(Package/Board)

Testing

Failure

analysis„Physics

of Failure“requested

Low CTE

High CTE



Definition of process level

Hirarchy-Level AVT

Source: Pahlke, Siemens, 2010

Board Level Reliability

contains

theinterconnect

reliability

between

thepackage

and the

module

and/orPCB

WS on 3D SiP, ESREF 2012 Cagliari, Italy, October 1st, 2012, ARCHER 1999: Thema: 8.1Dr. Albrecht Folie: 002

ConstructionalDescription of

Package, PCB,Stencil Thickness,Aperture, SolderWet Thickness

Com

pone

nts,

... D

atas

Solder PasteTransfer

PlacementReflow

Single-SidedDouble-Sided

(Wave Soldering)

Inspection FPY,Repair/ Rework,

Initial Stage

Plac

emen

t

Visu

al In

spec

tion

Wet

Thi

ckne

ss

Rew

ork

Elec

trica

l Tes

t

Data Collection

Prin

t-Par

amet

er

T-Pr

ofile

Sin

gle-

Side

d

T-Pr

ofile

Dou

ble-

Side

d

Mec

hani

cal E

valu

atio

n

X-R

ay, M

icro

sect

ion

Package Design(Analyse)

Electrical/ MechanicalDepend Features forStability/ Instability

InterconnectionMaterials

Solder PasteConductive/ Non-conductive Glue

LaminateMLL

FinishPad-Layout

ComponentsPassives

Leaded SMDArea Array

Stencil

Incoming

data

for

assembly-

and test procedures(Constructional

and material analysis

of components

/ laminates

and interconnect

materials

with

the

relation

to the

processability)Discussion

of consequencies

related

to the

„Design for

Reliability“

Schematic

View: Processability

and Zero Defect

Strategy

WS on 3D SiP, ESREF 2012 Cagliari, Italy, October 1st, 2012, ARCHER 1999: Thema: 8.1Dr. Albrecht Folie: 003

On-/ Offline- DC-Resistance

TCT500, 1000,2000, 4000

PCT, T0

PCT, T0 + ΔT

R-Measurement

Data Collection

AcceleratedAgeing

Sheartest

Pulltest

Microsections

X-Ray / REM

Life Time PredictionTransformation TCT - PCT

Definition of accelerated

tests

ACT / compatability

to the

field

conditions

and acceptability

criteriasof the

Board Level ReliabilityLife time analysis

and comparison

to the

expected

Mission Profile

Field

conditionsAuswahl ACT-TestCriteriasData Evaluation

NDE-/DE-Analysis

Damage-Mechanism

Read-Outs

Acceptance

CriteriasCustomer

Requirements

Schematic

characterization

Darstellung: Board Level Reliability

EM


Assembly

scheme

•

Solder

paste

printing, bottom

package•

Flux

dipping

for

stacked

packages•

Dipping

height

~60% of ball height

Page 29WS on 3D SiP, ESREF 2012 Cagliari, Italy , October 1st, 2012, ESiP confidential

Overview

These devices are:•CMR3000 of VTI (test boards ESIP02 and ESIP03)•SO8 (with anti counterfeiting tags) of ST-France•BRDL Demonstrator of AMS (postponed)•BGA module of 3D Plus (cancelled)•MLF SiP of Melexis (test board ESIP05)

Figure 2: CMR3000 test baord for temperature shock test (design “ESiP02”)

Figure 5: test board ESIP-05 Infi neon and Melexis

Figure 6: test board ESIP-06 Infineon eContact


Assembly

/ X-ray

Daisychain Bottom

Daisychain Top

Bottom Package 12x12mm² Stack

Daisychain Bottom

Daisychain Top

Bottom Package 12x12mm² Stack

3x Stack 12x12mm² - Different Conactlayers can hardly be distiguished

Foreground: 3x Stack 12x12mm²

Background: 2x Stack 14x14mm²

• Head‐in‐Pillow orVoiding detectable?

Stacked structure masks balls, potential defects practically notvisible in X‐Ray 3x Stack 12x12mm²,

alignment of balls of upper packages

Perimeter Arrayof Middle- and Top-Package


Comparison of Solder Volume

Dissolution data of Cu and Ni into SAC solders (SAC SnAgCu; SP SnPb) and the expected metallurgical modification in terms of reflow processes

Left: BGA/FlipChip

interconnects; Middle: micro-bumps 25 µm /2/ Right side: 15 µm bumps /3/

Pad-∅

Ball-∅

Pitch 1,27 0,80 0,65 0,50 0,25

0,75

0,35 0,30 0,300,15

0,50 0,30 0,30 0,25 0,15

Ball-Vol.PadflächeBall-Vol.

Padfläche = 1,125 0,318 0,200 0,288 0,149

InterconnectionInterconnection StructureStructure / / AdvancedAdvanced PackagesPackages

0,12

0,085

0,045

0,187

0,060,02

(2010)

0,063

0,0350,01

0,100

0,40LFBGAJapan

0,20wlCSPJapan

BGA, LFBGA wlCSP, Flip Chip

Status 2010

Interface Driven Reliability Features

L2PC0.09V LPND

Influence

of Solder

Volume

Related

tothe

Grain

OrientationMüller, M: LIVE-Meeting, 20.02.06


Open Contacts, potentially

due

to warpage(Package

mechanically

damaged

in tray?)

Stack 14x14, 2x 12x12, 4x 12x12, 3x 12x12, 2x 12x12, 1xYield [%] 97,6377953 88,8888889 96,6480447 100 100Samples assembled 127 9 179 25 51

Warpage

behavior of integrated packages

Stacking

Yield

(measured

by

electrical

function):

ReflowGradient (max): 2,3K/sQT (max): 812Ks

VPSGradient (max): 3K/sQT (max): 831Ks

Warpage along package diagonal at peak temperature Warpage over soldering profile, measured at package center

Warpage along package diagonal at peak temperature Warpage over soldering profile, measured at package center

Warpage

3x Stack

12x12mm²

Warpage

2x Stack, 14x14mm²

Comparison warpage 1st and 2nd reflow

Warpage

increased

due

by

multiple reflows

Warpage

2xStack 14x14mm²


Warpage

behavior of integrated packages

PoP 14x14 Top-Ebene - Muster 2

-50

-30

-10

10

30

50

70

90

0 2 4 6 8 10 12 14 16 18 20

Bauelementediagonale [mm]

Verw

ölbu

ng [µ

m]

40° C250° C

Verwölbung < 20µm

Verwölbung ~ 20µm


-50

-30

-10

10

30

50

70

90

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C250° C

Verwölbung < 20µm


-50

-30

-10

10

30

50

70

90

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C250° C

Verwölbung < 20µm

Verwölbung ~ 20µm

PoP 14x14 Top- Ebene - Muster 1

-50

-30

-10

10

30

50

70

90

0 2 4 6 8 10 12 14 16 18 20

Bauelementdiagonale [mm]

Verw

ölbu

ng [µ

m]

40° C

249° CVerwölbung ~ 20µm

PoP 14x14 Top- Ebene - Muster 1

-50

-30

-10

10

30

50

70

90

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C

249° CVerwölbung ~ 20µm

PoP 14x14 Bottom - Muster 1

-50

-40

-30

-20

-10

0

10

20

30

40

50

0 5 10 15 20

Bauelemente Diagonale [mm]

Verw

ölbu

ng [µ

m]

250° C

28° C nach Reflow

40°C

Verwölbung ~ 50µm

PoP353 14x14 Bottom Muster 2

-50

-40

-30

-20

-10

0

10

20

30

40

50

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C

238° C

28° C nach Reflow

Verwölbung ~ 50µm


-50

-40

-30

-20

-10

0

10

20

30

40

50

0 5 10 15 20


Verw

ölbu

ng [µ

m]

250° C

28° C nach Reflow

40°C

Verwölbung ~ 50µm


-50

-40

-30

-20

-10

0

10

20

30

40

50

0 5 10 15 20


Verw

ölbu

ng [µ

m]

250° C

28° C nach Reflow

40°C

Verwölbung ~ 50µm


-50

-40

-30

-20

-10

0

10

20

30

40

50

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C

238° C

28° C nach Reflow

Verwölbung ~ 50µm


-50

-40

-30

-20

-10

0

10

20

30

40

50

0 2 4 6 8 10 12 14 16 18 20


Verw

ölbu

ng [µ

m]

40° C

238° C

28° C nach Reflow

Verwölbung ~ 50µm

Warpage

results

in diagonal axis

of the

component


Comparison

of Practical

Used

Reflow

Pofiles for

SnPb

vs

SnAgCu

QT - AnalyseLot: SnAg3,8Cu0,7 (TL=217°C)

Testboard

210

215

220

225

230

235

240

245

250

0 10 20 30 40 50 60

t in s

T in

°C

800700600500400300200100BE

PBGA

CSP64

CR0402

SO20

Densi PacCSP144-Ball

SOD 87ELKO A

SOD 80

CR1206

TQFP

Auftreten grober IMPVermehrtes Auftreten von IMPwenige und fein verteilte IMP Quelle: Dr. Müller (UBT)

Auftreten grober IMV

Vermehrtes Auftreten von IMV

wenige und fein verteilte IMV

TL(SnAgCu)

Voids / % / 5 01015

QT-Werte und Peaktemperaturen aller aufgebauten LPBeispiel SnAg3,8Cu0,7 - 96SC + Vergleich SnPb37

0

1000

2000

3000

4000

5000

6000

200 210 220 230 240 250 260 270

T^ in °C

QT

in K

*s

Keller_LKeller_KRgb_V 2Rgb_V 3Bln_3.99Rgb_4.99Rgb_V3-10Rgb_V3-20Rgb_V4Key 240Key 260SV-Modul 1SV-Modul 2Khe 240_4Khe 240_6Khe 260_4Khe 260_6SnPb-Simatic MODLOT 225MODLOT 235MODLOT 240MODLOT 250MODLOT 260INNOLOT TB1SnPb-Vgl

SnPbAg235°C

SnAgCu235°C

Adäquate Grenzflächencharakteristik ?

t oberhalb TliquidBestimmt die Benetzungsquantität

ΔT (Tliquid -Tpeak)QT-Relevanz

QT Analysis, Tsolidus –dependend Differencies relatedto the Energy Transfer

QT –

Analysis performing the metallurgical aspects

Energy based analysis concerning void formation in Pb

free interconnectsMetallurgical uniformity of interconnects


QT –

Analysis Stacked

Packages

Reflow

soldering

Vapor

phase

soldering

Thermoelement 1

(an Glasplatte)

Thermoelement 2

(an Dummy BE)


Warpage

improvement

TMV-PoP

• Improved Warpage behavior of through mold via (TMV)stackable Package• Perhaps less warpage due to smaller die

3 layer

stack

Hidden

defects

3 layer

stack

/ x-ray


Overview

Example

for

assembly

/ interconnect

variations


Status of Lead-free Interconnects

Influence of Interfaces Increasing

0,0500,1440,2600,5630,0090,0240,2900,369Solder Volume / Pad-Area0,0350,0980,2510,3930,1311,7804,40012,800Total Interface Area in mm20,0020,0140,0650,2210,0010,0431,2754,725Solder Volume in mm3

150 µm300 µm500 µm750 µmCR1005CR0603CR1206CR2512Component / Ball-∅

0,0500,1440,2600,5630,0090,0240,2900,369Solder Volume / Pad-Area0,0350,0980,2510,3930,1311,7804,40012,800Total Interface Area in mm20,0020,0140,0650,2210,0010,0431,2754,725Solder Volume in mm3

150 µm300 µm500 µm750 µmCR1005CR0603CR1206CR2512Component / Ball-∅

After Assembly

After ATC (TCT-40/+125,N1000

Crack

Initiationand Growth

Micro-/ (Nano-)Demands


Field

related

strain

and stress factors

01 Interposer

02 Interface (IF) Finishes

Interposer

03 Interface Solder

mask

Interposer

04 Quality

metallization

Interposer

05 IF-

Qualität Interposer

finish/IMC (X-times

Reflow)

06 IF-

Quality

inside

IMC

07 IF-

Quality

IMC/ bulk

solder

08 IMC in the

bulk

(e.g. Cu6

Sn5

, Ag3

Sn)

09 Solder

matrix

and micro-/macro-voiding)

10 IF-

Quality

IMC/ Bulk

(X-times

Reflow and PoP)

11 IF-

Quality

in the

IMC (Mikro-Voiding)

12 IF-

Quality

laminate

finishes/IMC

13 Metallizations

PCB16InterfaceSolder

mask/laminate

14

InterfaceLaminate

finishes

15

Defects

in thelaminate

Areas

of Interest

(AoI)

First level

/ second level?? Stacked

structure


Overview Samples

Source: IFX

Demonstrators delivered by Infineon for reliability test setupsExample 1:Large side by sidefirst samples at Siemens CT Berlin available

Example 2:eContactfirst samples at Siemens CT Berlin available

Example 3:3D SiP: “Pot-bellied pig(Hängebauchschwein)” underpreparation at IFX

Example 4: Stacked dice with passivesunder preparation at IFX

Layout of drop test board

Layout of TCT board

Abstand Via-Leiterzug: 75µm

Leiterzugbreite: 75µm

BGA Pitch: 500µm



BGA Pitch: 500µm



BGA Pitch: 500µm

75µm

75µm

Layout Footprint PoP 12x12

Daisychain1 (Bottomlage)

Daisychain2 (Toplage)

Daisychain3

(Mittenlage)


Summary

Findings•

Qualification demands increasing with package complexity•

Functional materials must be qualified in terms of thermal stability•

TCT and PCT are applicable for higher integrated packages on board•

Stacking layers controlled by metallurgical analysis after reflow•

Warpage

measurements

to control

thermal stabilities

in terms

of x-times

reflow•

Interconnect

are

free

of failure

after

qualified

reflow

application•

3D interactions

as tool

to qualify

z-axis•

Reliability

comparable

to conventional

packages

reliability capability evaluation model for highly ... · pdf filepackage leadframe packages...

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