refia-d(nvp2190)refia-d(nvp2190) data sheet 3 high end ccd image signal processor refia-d is a high...

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REFIA-D(NVP2190) High end CCD image signal processor Data Sheet Web : www.nextchip.com E-mail : [email protected] Tel : +82-2-3460-4700 Information contained here is subject to change without notice. Make sure to check and use an updated version of the Data sheet.

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Page 1: REFIA-D(NVP2190)REFIA-D(NVP2190) Data Sheet 3 High end CCD image signal processor REFIA-D is a high end and high performance image signal processor (ISP) to upgrade your CCTV camera

REFIA-D(NVP2190) High end CCD image signal processor

Data Sheet

Web : www.nextchip.com E-mail : [email protected] Tel : +82-2-3460-4700 Information contained here is subject to change without notice. Make sure to check and use an updated version of the Data sheet.

Page 2: REFIA-D(NVP2190)REFIA-D(NVP2190) Data Sheet 3 High end CCD image signal processor REFIA-D is a high end and high performance image signal processor (ISP) to upgrade your CCTV camera

REFIA-D(NVP2190) Data Sheet

www.nextchip.com

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Revision History

REFIA-D(NVP2190) Data Sheet

Date Rev. From To

Feb. 2012 0.5 - Initail release

© Copyright Nextchip Corporations, Ltd., 2012 All Rights Reserved. Printed in Korea 2012 Nextchip and the Nextchip Logo are trademarks of Nextchip Corporation in Korea and/or other countries. Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support application where malfunction may result in injury or death to persons. The information contained in this document does not affect or change Nextchip's product specification or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Nextchip or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will Nextchip be liable for damages arising directly or indirectly from any use of the information contained in this document. Nextchip Corporation Ltd 4F, KAMCO YangJae Tower, 949-3, DoGok-Dong, GangNam-Gu, Seoul, Korea Nextchip's home page can be found at: http://www.nextchip.com

Page 3: REFIA-D(NVP2190)REFIA-D(NVP2190) Data Sheet 3 High end CCD image signal processor REFIA-D is a high end and high performance image signal processor (ISP) to upgrade your CCTV camera

REFIA-D(NVP2190) Data Sheet

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High end CCD image signal processor REFIA-D is a high end and high performance image signal processor (ISP) to upgrade your CCTV camera. With F-DNR (Fog Digital Noise Reduction), you will have a distinctive image in any severe circumstances : counterlight, fog, rain, etc). This enhanced image can be also improved by DWDR and 3D-NR together. In addition, new special features includes DIS (Digital Image Stabilizer), polygon privacy mask zone, which will enhance your overall system performance. Other freatures like sense-up function, digital zoom for magnifying image without zoom lens, motion detecton, etc. will help you to get the image you need.

Features - Input : NTSC/PAL, 760H/960H CCD format - Output : NTSC/PAL analog S-Video or CVBS ITU-R.656 digital out (27/28.6363/28.375/36MHz) - Support horizontal 700TVL(960H) resolution - Blemish compensation 512 points (Auto/Manual) - Auto DC-IRIS controller - Color rolling/breathing suppress - De-moire - Sense-up (up to x256) - Programmable gamma processing (16 steps) - Lens shading - DWDR (Digital wide dynamic range expansion) - F-DNR (Fog Digital Noise Reduction) - 3D/2D noise reduction - DIS (Digital Image Stabilizer) - Digital zoom (x1 ~ x32) - Motion detector - Privacy mask 8 zone (polygon) - Vertical/horizontal mirror - OSD (256 user fonts) - Support line lock external synchronization - RS-485, Coaxial communication (PELCO-C) - Serial interface for AFE (AD9943/AD9949) - Serial peripheral interface (3-wire) - Embedded MCU (96KB program RAM/4K RAM) - On-chip NTSC/PAL video encoder - On-chip 2-CH DAC x 2 (S-video or CVBS or IRIS) - On-chip 1-CH ADC (4-CH MUX) - 3.3V/1.8V/1.2V power

Ordering information

Device Package Temperature Range

REFIA-D(NVP2190) 144 FBGA -25℃ ~ 85℃

Applications - CCD camera - Zoom lens box camera - Video phone camera - Rear-view monitoring camera

Related products

- CCD : Sony/Sharp 760H/960H CCD Sensor

- AFE : AD9943, AD9949 - V-Driver : NVD2014A

Functional block diagram

3D

NR

ZO

OM

FR

EE

ZE

V M

IRR

OR

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TABLE OF CONTENTS

REVISION HISTORY ............................................................................................................................................................... 2

TABLE OF CONTENTS ........................................................................................................................................................... 4

LIST OF TABLES ...................................................................................................................................................................... 5

LIST OF FIGURES ................................................................................................................................................................... 5

CHAPTER 1 BALL INFORMATION ......................................................................................................................................7

1.1 BALL ASSIGNMENT ................................................................................................................................................................................................ 8

1.2 BALL DESCRIPTION ................................................................................................................................................................................................ 9

CHAPTER 2 ELECTRICAL CHARACTERISTICS ................................................................................................................ 12

2.1 RECOMMENDED OPERATING CONDITIONS .................................................................................................................................................... 13

2.2 DC CHARACTERISTICS ....................................................................................................................................................................................... 13

2.3 ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................................................... 13

2.4 POWER CONSUMPTION .................................................................................................................................................................................... 13

CHAPTER 3 PACKAGE INFORMAION ............................................................................................................................. 14

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List of Tables

Table 1 Ball description ............................................................................................................................................... 11

List of Figures

Figure 1 Ball map.......................................................................................................................................................... 8

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Page 7: REFIA-D(NVP2190)REFIA-D(NVP2190) Data Sheet 3 High end CCD image signal processor REFIA-D is a high end and high performance image signal processor (ISP) to upgrade your CCTV camera

REFIA-D(NVP2190) Data Sheet

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Chapter 1

Ball information

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1.1 Ball assignment

Figure 1 Ball map

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1.2 Ball description

Name Ball

number Type Descriptions

System

XTALI L12 I Crystal input

XTALO M12 O Crystal output

RSTB L3 I System reset

CCD interface

XSG1 A1 O CCD read out pulse 1

XSG2 B1 O CCD read out pulse 2

XSUB A2 O CCD shutter speed control pulse

XRG E1 O CCD reset gate pulse

V1 B5 O CCD vertical driving pulse phase 1

V2 B4 O CCD vertical driving pulse phase 2

V3 B3 O CCD vertical driving pulse phase 3

V4 B2 O CCD vertical driving pulse phase 4

H1 D1 O CCD horizontal driving pulse phase 1

H2 C1 O CCD horizontal driving pulse phase 2

SHP A3 O CDS sample & hold pulse for pre-charge

SHD A4 O CDS sample & hold pulse for data

CLPOB A6 O Optical black signal

AFE_CLK A5 O AFE sampling clock

CFA interface

CFAIN_00 B12 I CCD CFA pattern input 0

CFAIN_01 A12 I CCD CFA pattern input 1

CFAIN_02 B11 I CCD CFA pattern input 2

CFAIN_03 A11 I CCD CFA pattern input 3

CFAIN_04 B10 I CCD CFA pattern input 4

CFAIN_05 A10 I CCD CFA pattern input 5

CFAIN_06 B9 I CCD CFA pattern input 6

CFAIN_07 A9 I CCD CFA pattern input 7

CFAIN_08 B8 I CCD CFA pattern input 8

CFAIN_09 A8 I CCD CFA pattern input 9

GPIO

EXP_00(EXT_INT0) D2 B GPIO 0.0 / External interrupt 0

EXP_01(EXT_INT1) E2 B GPIO 0.1 / External interrupt 1

EXP_02(SPI_SCK) F2 B GPIO 0.2 / SPI clock

EXP_03(SPI_MISO) F1 B GPIO 0.3 / SPI MISO

EXP_04(SPI_MOSI) G2 B GPIO 0.4 / SPI MOSI

EXP_05(SPI_CSN) G1 B GPIO 0.5 / SPI chip select

EXP_06(AFE_SCL) B7 B GPIO 0.6 / Serial interface clock (AFE interface)

EXP_07(P_BLK) C12 B GPIO 0.7 / Pixel blanking

EXP_10(AFE_SDA) A7 B GPIO 1.0 / Serial interface data (AFE interface)

EXP_11(AFE_SLD) B6 B GPIO 1.1 / Serial interface enable (AFE interface)

EXP_12(SF_CLK) J11 B GPIO 1.2 / Serial FLASH clock

EXP_13(SF_CSB) K11 B GPIO 1.3 / Serial FLASH chip select

EXP_14(SF_DQ0) K12 B GPIO 1.4 / Serial FLASH DQ0(DI)

EXP_15(SF_DQ1) H11 B GPIO 1.5 / Serial FLASH DQ1(DO)

EXP_16(SF_DQ2) H12 B GPIO 1.6 / Serial FLASH DQ2(WP#)

N.C J12 - Not connect

EXP_20(DIGT0) M5 B GPIO 2.0 / Digital data output 0

EXP_21(DIGT1) L6 B GPIO 2.1 / Digital data output 1

EXP_22(I_RMT_IN/H_BLK)

L5 B GPIO 2.2 / Remote controller input

EXP_23(PWR_ID/H_BLK)

G10 B GPIO 2.3 / Power generation pulse

EXP_24(UART_TX0) G11 B GPIO 2.4 / UART Tx 0

EXP_25(UART_RX0) G12 B GPIO 2.5 / UART Rx 0

EXP_26 (I_COAX/UART_TX1)

F11 B GPIO 2.6 / Coaxial input

EXP_27 (COAX_AREA/UART_RX1

F12 B GPIO 2.7 / Coaxial area

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Name Ball

number Type Descriptions

EXP_30 (EXT_VSYNC/H_BLK)

E11 B GPIO 3.0 / Line lock external sync

EXP_31(V_BLK) E12 B GPIO 3.1 / Vertical blank

EXP_32(FLD) D11 B GPIO 3.2 / Field

EXP_33 D12 B GPIO 3.3

EXP_34(DIGT2) M6 B GPIO 3.4 / Digital data output 2

EXP_35 C11 B GPIO 3.5

EXP_36(DIGT3) L7 B GPIO 3.6 / Digital data output 3

EXP_37 (CLPDM/EXT_HSYNC)

L10 B GPIO 3.7 / Dummy cell clamping pulse

EXP_40(DIGT4) M7 B GPIO 4.0 / Digital data output 4

EXP_41(DIGT5) L8 B GPIO 4.1 / Digital data output 5

EXP_42(DIGT6) M8 B GPIO 4.2 / Digital data output 6

EXP_43(DIGT7) L9 B GPIO 4.3 / Digital data output 7

EXP_44(PWM) L11 B GPIO 4.4 / PWM

EXP_45(PWM_REF) M11 B GPIO 4.5 / PWM reference

DAC

DAC1 dacDAC2

K1 O DAC 1 output

DAC2 L1 O DAC 2 output

DAC3 M1 O DAC 3 output

DAC4 M2 O DAC 4 output

DAC12_VREF K2 I DAC12 voltage reference

DAC12_COMP

K3 O DAC12 comparator reference

DAC12_REXT L2 I DAC12 external resistor

DAC34_VREF M4 I DAC34 voltage reference

DAC34_COMP M3 O DAC34 comparator reference

DAC34_REXT L4 I DAC34 external resistor

AVDD_DAC1 H4 P Analog power (3.3V) for DAC 1

AVDD_DAC2 J4 P Analog power (3.3V) for DAC 2

AVDD3A_DAC12 G6 P Analog power (3.3V)

AVDD_DAC3 K5 P Analog power (3.3V) for DAC 3

AVDD_DAC4 K6 P Analog power (3.3V) for DAC 4

AVDD3A_DAC34 K4 P Analog power (3.3V)

AVSS_DAC1 G5 P Analog ground for DAC 1

AVSS_DAC2 H5 P Analog ground for DAC 2

AVSS3A_DAC12 G4 P Analog ground

AVSS_DAC3 J6 P Analog ground for DAC 3

AVSS_DAC4 J7 P Analog ground for DAC 4

AVSS3A_DAC34 J5 P Analog ground

ADC

ADC_CH0 H2 I ADC 0 input

ADC_CH1 H1 I ADC 1 input

ADC_CH2 J2 I ADC 2 input

ADC_CH3 J1 I ADC 3 input

ADC_VREF H3 I ADC voltage reference

ADC_REXT100K J3 I ADC external resistor

AVDD_ADC F3 P Analog power (3.3V) for ADC

AVSS_ADC G3 P Analog ground

Etc.

DIGT_CLK M9 O Digital data output clock

LL_CLK M10 I Line lock clcok

Power

VDD12

C5, C8, C9, D5, D8, G8, H8, H9,

H10

P 1.2V Power

VDD3 C6, C7, G7, H6

P 3.3V Power

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Name Ball

number Type Descriptions

VDD18 C10, D9, D10, F9, F10, G9

P 1.8V Power

VDD_FLASH H7 P 3.3V Power for FLASH

VDD3_SHPD C3 P 3.3V Power for SHP/D

VDD3_H12 D3 P 3.3V Power for H1/2

VDD3_XRG E3 P 3.3V Power for XRG

AVDD12_PLL1 K7 P 1.2V Power for PLL

AVDD33_PLL1 K8 P 3.3V Power for PLL

Ground

VSS

E5, E6, E7, F5, F6, F7, F8, J10

P Ground for 1.2V

VSS_IO D6, D7, F4, K9

P Ground for 3.3V

VSS18 E8, E9,

E10 P Ground for 1.8V

VSS_FLASH K10 P Ground for FLASH

VSS_SHPD C4 P Ground for SHP/D

VSS_H12 D4 P Ground for H1/2

VSS_XRG E4 P Ground for XRG

AVSS_PLL1 J8, J9 P Ground for PLL

TEST C2 Ground

Table 1 Ball description

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Chapter 2

Electrical characteristics

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2.1 Recommended operating conditions

Parameter Symbol Min. Typ. Max. Unit

DC supply voltage 1 VPOWER1 1.08 1.20 1.32 V

DC supply voltage 2 VPOWER2 2.97 3.30 3.63 V

DC supply voltage 3 VPOWER3 1.65 1.80 1.95 V

Ambient operating temperature VA -20 - 85 ℃

2.2 DC characteristics

Parameter Symbol Min. Typ. Max. Unit

Input low voltage VIL -0.3 0.8 V

Input high voltage VIH 2.0 VPOWER2 + 0.3 V

Input leakage current IL ±1 uA

Threshold point VT 1.30 1.41 1.53 V

Schmitt trig. low to high threshold point

VT+ 1.54 1.65 1.74 V

Schmitt trig. high to low threshold point

VT- 0.95 1.02 1.09 V

Output low voltage VOL 0.4 V

Output high voltage VOH 2.4 V

2.3 Absolute maximum ratings

Parameter Symbol Min. Typ. Max. Unit

DC supply voltage 1 VP1 -0.5 1.80 V

DC supply voltage 2 VP2 -0.5 4.60 V

DC supply voltage 3 VP3 -0.5 2.60 V

Input voltage Vi -0.5 4.60 V

Output voltage VO -0.5 4.60 V

Storage temperature VS -65 - 150 ℃

2.4 Power consumption (To be done)

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Chapter 3

Package informaion

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Package Type Ball pitch Size (WxD)

144 FBGA 0.8mm 10mm x 10mm