Erik Jonsson School of Engineering & Computer Science

Redundant SAR ADC Architecture

and Circuit Techniques for ATLAS

LAr Phase-II Upgrade

Ling Du1, Hongda Xu1, Yun Chiu1

Datao Gong2, Jingbo Ye2

1University of Texas at Dallas, Richardson, TX, USA

2Southern Methodist University, Dallas, TX, USA

TWEPP 2015 - 2 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single-Event-Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 3 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single-Event-Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 4 - 2015-10-01

ADC Specs for Phase-II LAr Readout

• High resolution: 12-14 bits

• High speed: 40-80 MS/s

• Low power, low area

• Radiation-tolerant

Detector

Output Signal

Phase-II Upgrade FEB (On detector)

MUX

&

Serializer Optical Links

To Back-end

-1000 200400600800100012001400

0

0.5

1

Time [ns]

Norm

alize

d A

mp

litu

de

Analog

Shaper

ADC

Preamp

ADC

16-bit DR 10 Gbps???

TWEPP 2015 - 5 - 2015-10-01

Previous TID Results (TWEPP’14)

• 12-bit, 160-MS/s ADC on 40-nm CMOS

• Total radiation dose up to 1 Mrad

• No significant degradation on SNDR, SFDR

100

102

66

66.5

67

67.5

68

68.5

69

SN

DR

[dB

]

100

101

102

10310.67

10.75

10.84

10.92

11.00

11.09

11.17

EN

OB

[bit]

Radiation dose [krad]

fin=10MHz

fin=25MHz

fin=40MHz

fin=70MHz

100

102

80

82

84

86

88

90

92

SFD

R [

dB

]

100

101

102

10313.00

13.33

13.66

14.00

14.33

14.66

15.00

EN

OB

[b

it]

Radiation dose [krad]

TWEPP 2015 - 6 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single Event Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 7 - 2015-10-01

A A,i A,i

i

d = w D

B B,i B,i

i

d = w D

• LMS update: A,i A,i A,iw (n+1) = w (n) - μ ε D

B,i B,i B,iw (n+1) = w (n) + μ ε D

Vin

ε

dA

dB

dout

ADCA

ADCB

Radix

Cal.

Radix

Cal.

DA

DB

Architecture – Split ADC

• Split-ADC enables digital background calibration

TWEPP 2015 - 8 - 2015-10-01

• Fewer number of bits in first stage

• Amplifier removed from SAR LoopFast Conversion

Vin

Cap

DAC

SAR

logic

Cap

DAC

SAR

logic

First stage Second stage

Amp

Architecture – Pipelined SAR

9 bits 7 bits

TWEPP 2015 - 9 - 2015-10-01

Architectural Redundancies

C9

+VR

VR

Vin

C8. . .

C0

Sub-binary DAC

Stage1

+Vref

Vref

Stage2

Vout512X

Stage1

+Vref

Vref

Stage2

Vout16X

+0.125Vref

0.125Vref

RA gain reduction and

inter-stage redundancy

Intra-stage and inter-stage redundancies for dynamic error tolerance

• DAC incomplete settling, reference voltage bouncing, etc.

• Comparator hysteresis, noise crosstalk, etc.

TWEPP 2015 - 10 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single-Event-Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 11 - 2015-10-01

Split ADC for SEE Protection

Vi

DoA

Do

ΔDo

DoB

ADCA

SEE Det.

SEE Det.

ADCB

Logic /2

Mu

x

• If ΔDo is large, chose the output of the ADC that is not hit

• A 3-dB SNR gain with normal operation (i.e., no hit)

TWEPP 2015 - 12 - 2015-10-01

Modeling SEE Current

100

Time

[ps]

Current

[mA]

10

0 200

Drain

175 nm

90 nm

13

5 n

m

Impact

point

2 1-t / -t /tot

2 1

QI = e - et

-

Ref. Bonacini, “Redundancy

methods in ASICs,” 2013

Ref. Mavis and Eaton, “SEU and SET Modeling

and Mitigation in Deep Submicron Technologies,”

2007

TWEPP 2015 - 13 - 2015-10-01

Summing-Node Hit Detection

VX+

Φ=0

Φ=0

VX-

M1

M2

Req

Req

VT

VH

VL

VDD

0

VX+hit

VX- hit

Ionizing

current pulse

No hit

LVT NMOS clamp

to prevent latch up

• For QSEE = 100 fC and CTOT = 2 pF, Verr = 50 mV !

• SEE detector is formed by a pair of resistors, a “substrate-

current amplifier”, and some digital logic

C C 2N-1C

VX+

C C 2N-1CΦ=0

Φ=0

VX-

Summing node(high impedance)

SAR DAC (N-bit)

SAR DAC (N-bit)

M1

M2

TWEPP 2015 - 14 - 2015-10-01

Summing-Node Hit Detection

ISEE

CLK_samp

SEE_Amp

SEE_Out

• The total charge collected due to SEE is ~5.5 fC, causing a 2.75-mV

voltage error on a 2-pF DAC (~20 LSBs)

• The detector is reset at the beginning of each sample period

0.6V0.97V

TWEPP 2015 - 15 - 2015-10-01

1st-Stage SAR Error Detection

VAMP

t

VFS/2

VFS/2

0

VFS

error within redundancy

error out of redundancy

(11...11)

Stage2

(00...00) VFS

Out-of-range error can be detected by observing the code of the 2nd stage:

11…11 (overshoot) or 00…00 (undershoot)

TWEPP 2015 - 16 - 2015-10-01

. . .

2C 1C 6C

extra cap in

2nd-stage DAC

2nd-Stage SAR Error Detection

VX+-VX

-

normal condition

extra

cycle

normal condition w/ noise SEE

1 1 1 1

large

error

1 0 1 0 1 0 0 1

extra

cycle

extra

cycle

VX+-VX

- VX+-VX

-

LSB LSB LSB

TWEPP 2015 - 17 - 2015-10-01

Data-Latch Error Detection

C9

+VR

VR

Vin

C8. . .

C0

Data

Latch

Data

Latch. . . Data

Latch

Data latch not TMR-protected to

reduce the comparator loading

Comp

Amp

TWEPP 2015 - 18 - 2015-10-01

Data-Latch Error Detection

VAMP

t

-VFS/2

VFS/2

0

VFS residue stillwithin

redundancy

Stage2

one data latch hit here

Data latches hit during residue amplification may cause error

TWEPP 2015 - 19 - 2015-10-01

Data-Latch Error Detection

VSUMP

VSUMND Q

Clk

Q

parity

bit

CLK

Master

CLK

Sampling 1st SAR Conversion Amplification

parity bit

stored

data

output

one data latch

may be hit

TWEPP 2015 - 20 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single-Event-Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 21 - 2015-10-01

Layout Screenshot

Stage1Stage2

CLK GenReference

buffer

Stage1Stage2

65-nm

CMOS

TWEPP 2015 - 22 - 2015-10-01

Preliminary Simulation Results

Corner Max. Fs [MS/s] SNDR [dB] SFDR [dB]

TT (w/o noise) 100 86.5 99.9

SS (w/o noise) 80 86.4 99.2

FF (w/o noise) 100 86.9 101.8

TT (w/ noise) 10076.4, single

79.1, avg

93.3, single

95.3, avg

TT

w/o circuit

noise

0 10 20 30 40 50

-120

-100

-80

-60

-40

-20

0

Freq [MHz]

[dB

]

SNDR=86.5dB

SFDR=99.9dB

TWEPP 2015 - 23 - 2015-10-01

Outline

• Introduction

• ADC Architecture and Redundancy

• Single-Event-Effect (SEE) Protection

• Layout and Simulation Results

• Summary

TWEPP 2015 - 24 - 2015-10-01

Summary

• Redundant pipelined SAR ADC is a strong candidate to meet the

stringent requirements for ATLAS LAr upgrade

• Split-ADC architecture with SEE detection techniques provides a

potential (architecture + analog) solution to SEE

• Various SEE-protection techniques and proven TID-tolerance will

result in a fully radiation-tolerant ADC in CMOS in the near future

• Stay tuned…

Thank you for your attendance!

TWEPP 2015 - 25 - 2015-10-01

Backup Slides

TWEPP 2015 - 26 - 2015-10-01

Split-ADC Bit-Weight Calibration

. . .

CDAC

C0 C1 CN

CCAL

PN•Vref (PN=±1)

Vout

Vin

Injection

< 0

Injection

> 0

Offset injection to the SAR conversion

curve to split the decision trajectory

TWEPP 2015 - 27 - 2015-10-01

Behavioral Simulation Results

0 0.5 1 1.550

60

70

80

90

100

dB

SFDR/SNDR Learning Curve

Number of Samples (millions)

SFDR

SNDR

Calibration converges within 1 million samples

[MSamples]

[dB

]

TWEPP 2015 - 28 - 2015-10-01

Comparator-RA Offset

Vout

Vin

2nd

stage

w/o offset

w/ offset

VFS

VFS/4

-VFS/4

-VFS

3VFS

4

VFS/2

-VFS/2

resid

ue

co

nfin

ed

he

re

• 150-mV 2nd-stage full scale

• 2-bit inter-stage redundancy

• 16× inter-stage gain

Maximum tolerable offset:

OS,MAX

3×150mV

4V = =7mV16

Too small !Observing the digital code of the 2nd

stage enables residue confinement

TWEPP 2015 - 29 - 2015-10-01

Comparator-RA Offset Calibration

. . .

CDAC

C0 C1 C9

. . .

CAUX

Ca0 Ca1 Ca7

Master

CLK

CDAC Sampling 1st SAR conversion Amplification

CAUX offset injection

Auxiliary DAC used to compensate the comparator-RA offset

TWEPP 2015 - 30 - 2015-10-01

TMR Protection for Logic Gates

D Q

Clk

Q

...

D Q

Clk

Q

...

D Q

Clk

Q

...

Voter

Voter

Voter

D Q

Clk

Q

D Q

Clk

Q

D Q

Clk

Q

Voter

Voter

Voter

...

...

...

CLK<0>

CLK<1>

CLK<2>

TMR-protected shift registers are used in other parts, i.e., clock generation,

parallel-to-serial conversion, etc.