reduced order codesignanalysis for design space evaluation ... reduced... · unclassified...

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UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesUNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

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Reduced Order CoDesign Analysis for Design Space Evaluation of Power Electronic Modules

Dr. Lauren Boteler (ARL)3D PEIM – June 2018

Dr. Steve Minor (USNA), Dr. Miguel Hinojosa, Michael Deckard (TAMU), Mike Fish, Mike Rego

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UNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

ArmyPower Electronics Applications

Power device packaging plays a critical role in enabling these

capabilities

Aerospace

Platforms

Medical

Survivability & Lethality

Army electrical power needs are increasing across the multi-

domain battlefield

↑ Power + ↓ Size = ↑ Temperature

àà Need improved packaging AND cooling

Opportunity Space• Packaging is now limiting the

performance of power electronics.• >99% of size and weight is

packaging• Little packaging improvement in

power packaging in >20 years

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• Wirebonds- 10-12 mil Al (Au or Cu)

• Power Device- Switches (IGBT/MOSFET) and Diodes- Silicon and/or Silicon Carbide

• Solder- AuSn, SAC, sintered silver

• DBC (Direct Bonded Copper)- Thick ceramic (25mils) sandwiched by

Cu (12 mils)- Ceramic: Alumina or AlN- Alternatives: DBA, AMB

• Heat Spreader- CuMo, CuW, AlSiC, Copper

• Thermal Interface Material (TIM)• Heat Sink/Cold Plate

- Copper, aluminum- Air or liquid cooled

Power Electronics: Standard Package

Heat Sink / Cold Plate

Heat Spreader

DBC

TIM

Power Device

SolderWirebonds

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Challenge Current Solution(s)Packaging limits performance Derate devicesOperating temperature (> 200°C) High temperature materials

Thermal (1 kW/cm2) – drives the size

Integrated cooling, reduce thermal resistance, PCMs, higher thermal conductivity materials, improved heat sinks

Break-down voltage (up to 25 kV) Increase package size, thicker/improved dielectrics

Inductance Snubbers, eliminate wirebonds, intelligent placement of chips on board

Reliability: DBC Dimple edges, DBAReliability: Wirebonds Eliminate wirebondsReliability: Large area contacts DBC, CTE matched materials (TiW, CuMo),

multiple DBC boards, stress-relieving TIMS

dtdiLV =

Power Electronics: Packaging Challenges

All of these challenges are exacerbated by increased temperature and/or temperature non-uniformity.

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• Because heat is what makes these things fail

• Thermal management can be a significant system cost even when things don’t fail–Poor choices, overdesign, reliance on ‘how things have

always been done’ can impact the bottom line• Rule of thumb: failure rate doubles for every 10°C rise

in temperature

Why do we care about thermal management?

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1. Co-Design/Co-Engineering– Consider the electrical, thermal and mechanical domains during design

2. Transient Thermal Mitigation– Designing for transient thermal loads instead of steady state to reduce

overdesign3. High Voltage Design and Packaging

– New high voltage devices (>15kV) create the need for advanced packaging4. Additive Manufacturing

– Custom power modules

Key Enabling Capabilities for Future Power Modules

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Sequential• Not optimized,

overdesigned• Integration is difficult• Minimal

understanding of tradeoffs

Current & New Design Methods

Electrical Mechanical Thermal

Parametric Analysis Methodology

16X Reduction in Size & Weight

Army Design Goal: Improve SWaP-C & Reliability

Co-Design/Co-Eng

Multiphysics Module Design

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Co-Engineered Design

Mechanical Electrical Thermal

stacked devices reduce parasitic inductance

fewer wirebonds

small area bonds reduce CTE mismatch fluid ports

for active cooling

internal heat sinks

thermal fins also electrical contacts

Positive Bus

Negative Bus

Midpoint

no DBCincreased power density

Co-Design Objective: Eliminate single

function components (ex. wirebonds, heat

sinks, solid dielectrics)

KEY enabling feature: Multi-functional components (MFC)• MFC acts as electrical, thermal and mechanical attachment consecutively

>40X improvement in power density

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Codesign – Parametric Analysis (ParaPower)

• Problem Statement: It is critical that the time required to understand a complete multi-disciplinary parametric space is reduced, this will eliminate overdesign in power modules and improve SWaP-C.

• Objective: Develop a tool that can support the military and the industry to quickly develop optimized power packages.

• ARLs ParaPower tool − Compact 3D thermal

resistance and stress network model

− Quickly analyze large multi-disciplinary parameter space

− >100X faster solution time with reasonable accuracy

− Simple node temperature and stress output

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Thermal Ohm’s Law

l Method: Use a 3D resistor network to perform a thermal analysis

l Ohm’s Law:

l Thermal Analogy to Ohm’s Law:

l Conduction:

l Convection:

elecIRV =

thermqRT =D

kAxRconduction

D=

hARconvection

1=

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Approach: Nodal Network

TeTa

Tb

Td

Tc

Ra

RbRc

Rd Re

Rf

Tf

To

Low fidelity network solution using MATLAB

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Approach

Combine Thermal Analysis & Stress Analysis

Single Node Resistance Network

Matrix Equation for Temperatures

• Stress driven by difference in CTE(α) and the change in temperature from initial (zero) stress (processing temp) and operating temperature

• Based on work by Hsueh, C. H., “Thermal Stress in Elastic Multilayer Systems,” Thin Solid Films, vol 418, pp 182 – 188, 2002.

E – Modulus of elasticityα –CTEc – Uniform component of straintb – Bending axis locationz – Vertical location in the substrate/film stackr – Radius of curvature

Bending StrainTotal Strain

!" = $" % − '"∆)!* = $* % − '*∆)

Stress in the substrate:

Stress in individual film layers:

% = c + - − ./0

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Model Verification

Grid / Network Density

Model Geometry

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Device Temp. (oC) Comparison

Network FEA FEA

Device Stress (MPa) Comparison

Network

Network Model Validation

Mesh Nodes Tmax (C) (MPa) Time (sec) Mesh Nodes Tmax (C) (MPa) Time

(sec)Network Solution FEA Solution

Coarse 343 80.4 489.1 0.25 Coarse 17994 71.4 461.7 21Medium 1008 78.7 502.7 0.34 Medium 53142 74.5 437.2 49

Fine 3328 77.6 506.9 0.95 Fine 145771 76.9 432.2 128

(half module shown, symmetric about dotted line)

<2C Difference <20% Difference

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Network Model Validation: Backside Cooling

• Parametric study of backside cooling (5,000-100,000 W/m2K)

• FEA solution time = 92 seconds

• Network solution time = 0.82 seconds (112X faster)

<2 °C

<20%

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Network Model Validation: Chip Spacing

Sample Geometry ParametersChip Spacing Study Results

• 3x3 device layout with boundary conditions of Q=64 W/cm2, h=1000 W/m2K• Square device spacing ranged from 1mm to 20 mm • Device spacing beyond 12 mm provided minimal decrease in maximum chip

temperature

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Parametric Analysis

1.

1.

2.

2.

3.

3.

4.

4.

5.5.

6.

6.7.

7.

8.8.

9.

9.

von

Mis

es S

tress

(Pa)

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Study Total Iterations Time (sec)Encapsulant 25 4.7

Encapsulant Parametric Analysis

Maximum

(C)

Thickness (mm) Conductivity (W

/m K)

VonMisesStress(MPa)

Thickness (mm

)

Conductivity (W/m K)

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Network Model Validation

Parametric Analysis 112X faster

• Benefits:- Eliminate CAD/meshing- Quick parametric analysis- Answer design questions- Determine the cooling method

- Flexible for any rectilinear geometries - Easy to learn interface- Simple node temperature and stress

output

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ParaPower Tool

Random Geometry Test:• 9 minute setup time• 5.8 second solution time with visuals

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IGBTs for High Voltage Applications

§ Army Relevant Applications:• Survivability & Lethality systems• Radar systems• Materials processing• Air/Water purification• Electro-photography• Power transmission

§ Historically: Gaseous electronic switches and relays operate in vacuum, SF6, hydrogen, or transformer oil but have low durability, large size, high cost

§ Silicon IGBTs improve reliability but requires many devices to be stacked

§ ARLs HVPT program: single die SiCswitches. Epitaxial growth >100µm → blocking voltages >10 kV.

21

50 kV Modulator designed as a power supply for a microwave magnetron.

Equivalent modules. Top: Si, Bottom SiC

Portable x-ray imaging(Minxray)

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High Voltage Packaging Projects

Previous Stacked DiodesGoal: Design and develop stacked-diode package capable of operating at 30 kV.

15 kV Stacked diodes

Fins for voltage

Stress relief

ABS 3D printed housing

Low stress Kovar high dielectric strength encapsulant

AnodeCathode

Rounded mitigate voltage crowding

Eliminate wirebonds, DBC, large area attaches

High VoltageReliabilityCost

Col

lect

or C

urre

ntD

iode

Cur

rent

(I d

iode

)

Discrete Diodes Stacked Diodes

Turn on Energy = 6.7 mJTurn on Energy = 8.6 mJ

Lower parasitic

capacitance

Faster reverse

recovery time

17A 9A

Stacked Diodes with Integrated CoolingGoal: Design and develop a high voltage

stacked-diode package with integrated cooling.

Tested to 21kV continuousDielectric fluid: Novak 7500

10X reduction in size!

ITherm2017IMAPS2015

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Parametric Analysis

• Want a module that can handle 30kV and dissipate heat: Co-designed High Voltage Module

• First module fully designed using ParaPower tool• Parameters varied:

• Number of fins• Fin spacing• Fin thickness• Exterior fin dimensions• Fin width• Fin material• Solder material• TIM material • Pillar thickness• Pillar material

15kV SiC diodes

anod

e

cath

ode

Fins

Pillars

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Geometric Comparison

• ParaPower results for number of fins and width of fins → 4 fins 3mm thick

• All results normalized to C/W metric

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Material Comparison

• Effect of fin material was also modeled comparing alumina (Al2O3), aluminum nitride (AlN), and machinable AlN

• These trade-offs/comparison studies can be performed in seconds

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Fabrication

Step 1: Machine and assemble thermal/electrical/ mechanical connections

MFC: Machinableceramic acts as both electric isolation and thermal fins

MFC: Copper pillars act as electric, thermal and mechanical contacts

Parametric model indicated thicker pillars were desired from a thermal perspective but needed a taper to connect to diode

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Fabrication

Step 2: Vertically align and attach stack

Bond created using silver epoxy

15kV SiC diodes

anod

e

cath

ode

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Fabrication

Step 3: Attach housing and fill with dielectric gel

MFC: Copper acts as heat sink and module housing

Dielectric gel inserted into cavities

AM end caps

Ceramic based thermal grease used for low stress connection, models showed thermal conductivity didn’t effect device temperature

30kV wire soldered to ends

Completed 30kV high voltage power module

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• Forward-conduction tests show the diodes perform as expected

• Pulsed dielectric breakdown tests showed it can withstand 30kV without breakdown (20uA compliance limit).

Testing

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• Objective: Investigate high-density packaging concepts to improve SWaP for high-voltage EM and DE vehicle survivability & lethality to leverage the 20kV class semiconductor devices that were developed under our SiC High-Voltage Power Technology (HVPT) program.

• Challenge: 15-30kV devices are a new area of research and packaging doesn’t exist• Goal: Compact high-performance integrated package capable of >25 kV

High Voltage (HV) Packaging Program

Device: Continuous(kV)

Failure @ 20 µA (kV)

Failure mode:

DiscreteDiodes

20 21.25Package

UncooledStacked

25 29.25Avalanche

CooledStacked

20 20.36 Package /Fluid

Co-designModule

25 30 No Failure

First fully co-designed power module

MFCs

Parametric Analysis

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• A method for quick single and parametric analysis of power modules has been developed and validated

• A ParaPower tool has been designed• Benefits:

- Eliminate CAD/meshing- Quick parametric analysis- Answer design questions- Determine the cooling method - Flexible for any rectilinear geometries - Easy to learn interface- Simple node temperature and stress output

- Designed as initial design tool, subsequent FEA/CFD required- Tool also includes:

- Transient thermal analysis- Currently implementing PCM in collaboration with TAMU

Conclusion

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1. Co-Design/Co-Engineering– Consider the electrical, thermal and

mechanical domains during design2. Transient Thermal Mitigation

– Designing for transient thermal loads instead of steady state to reduce overdesign

3. High Voltage Design and Packaging – New high voltage devices (>15kV) create

the need for advanced packaging4. Additive Manufacturing

– Custom power modules

Conclusions/Future Work

Holistic approaches to electronic design to enable significant SWaP improvement in various electronics systems

[email protected]

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