Reconfigurable Architecture based on FPGA forOFDM Transmitter

L. Orozco-Galvan, R. Parra-Michel

Dept. of Electrical Engineering

CINVESTAV-GDL

Zapopan, Jalisco, Mexico

{lorozco, rparra}@gdl.cinvestav.mx

E. Romero-Aguirre

Dept. of Electric and Electronic Eng.

Instituto Tecnologico de Sonora

Ciudad Obregon, Sonora, Mexico

eduardo.romero@itson.edu.mx

Abstract—Future communication systems such as 5G will re-quire high interoperability between standards, obligating currentdesigns to contemplate the inclusion of multiple standards intoa single device. Therefore, the main communication blocks mustbe designed with high capability in terms of reconfigurability.This paper presents the architecture and implementation ofa reconfigurable Orthogonal Frequency Division Multiplexing(OFDM) transmitter with such capabilities. The proposed ar-chitecture is capable of generating frames for the Long TermEvolution (LTE) standard and with minimal modifications canalso generate frames for IEEE 802.11a and 802.11g standards.The configuration parameters can be adjusted on-the-fly viaconfiguration registers, such as: frame size, cyclic prefix (CP) size,data modulation type, and pilot values. Additionally, it is possibleto operate in the five bandwidths required for LTE, allowingits inclusion in multi-standard design and software design radioplatforms. Results have shown a moderate FPGA (Field Pro-grammable Gate Array) consumption and good SQNR (signal-to-quantization-noise ratio) performance of 50 dB average.

I. INTRODUCTION

Nowadays, wireless mobile communications have expanded

dramatically all over the world, leading to a need to increase

their bandwidth capacity. One way to increase the capacity

of a wireless mobile communication system, is to improve

the communication technology [1]. In particular, Orthogonal

Frequency Division Multiplexing (OFDM) is considered the

technology for the next-generation broadband wireless sys-

tems. As a matter of fact, it has been adopted for many

standards, such as 3rd Generation Partnership Project-Long

Term Evolution (3GPP-LTE), Digital Audio Broadcasting

(DAB), Digital Video Broadcasting–Terrestrial (DVB-T), Dig-

ital Video Broadcasting-Handheld (DVB-H), and IEEE 802.11

[2].Nevertheless, OFDM systems requires intensive comput-

ing algorithms, so it is necessary to implement them using

contemporary high performance devices. Field Programmable

Gate Array (FPGA) is a very cost-effective and highly flexible

solution, which allows fast prototyping, and re-usability of

functional modules and also provides system performance

superior to traditional solutions based on Digital Signal Pro-

cessors (DSP). Additionally, FPGA designs can be easily

migrated to Application-Specific Integrated Circuits (ASICs).The following previous works have dealt with OFDM based

on FPGA: In [3] a configurable transmitter architecture for

explicit and implicit training (IT) communications systems is

proposed. This transmitter supports 4/16/64-QAM (Quadrature

Amplitude Modulation) modulation in superimposed train-

ing (ST) and data-dependent superimposed training (DDST).

However, the data rate is fixed, and the transmitter did not con-

sider a pulse-shaping filter. In [4] a Multi-standard Transmitter

is introduced. Its architecture incorporates both implicit and

explicit training modes into a reconfigurable transmitter for

Software Defined Radio (SDR) applications. It also considers

a pulse-shaping filter and is able to perform several modulation

schemes, such as: 4/16/64 QAM, Binary Phase Shift Keying

(BPSK), Offset Phase Shift Keying (OQPSK), Differential

Binary Phase Shift Keying (DBPSK), and Differential Phase

Shift Keying (DQPSK). Nevertheless, both, [3] and [4] are

only for single carrier systems.

A reconfigurable architecture for an OFDM modulator is

described in [5]. Such transmitter was tested for Chinese

Mobile Multimedia Broadcasting (CMMB) and DAB systems,

but not for LTE applications. Furthermore, an Intellectual

Property (IP) core was used for the Inverse Fast Fourier

Transform (IFFT) processing.

In [6], a modulator for IEEE 802.11a is discussed. Its engine

is based on a fixed-length 64-point Xilinx IP core, suitable

for IEEE 802.11a. Hence, it is not capable of supporting

other standards. In contrast to previous works, a fast OFDM

transmitter based on FPGA is presented in this work. No

IP cores nor pre-designed components were used in order

to assurance portability. Our study case was the 3GPP-LTE

standard for downlink frame, that is, Orthogonal Frequency

Division Multiple Access (OFDMA). However, it is reconfig-

urable enough to support OFDM applications.

The rest of the paper is organized as follows: section

II presents the basis for the OFDM transmitter and LTE

frame assembling. Section III describes in detail the FPGA-

design transmitter architecture. In this section, signal names

are written in bold face and module names are written with

typewriter font. Furthermore, modules which use clock

signal are represented graphically by adding an asterisk (*)

next to the module name. Section IV shows the implementa-

tion results and the performance evaluation of the proposed

architecture. Finally, section V presents our conclusions.

978-1-4673-8451-3/15/$31.00 ©2015 IEEE

II. TRANSMITTER BACKGROUND

A. Generic OFDM Transmitter

The block diagram of the generic OFDM transmitter is

shown in Fig. 1. The transmitter accepts a bit-stream from

higher layer protocols and converts them to symbols using

the chosen modulation scheme. The serial-to-parallel converter

then takes a block of Nc symbols a0, a1....,aNc−1 padding

with zeros to length N and translates them onto N parallel

sub-streams. The transmitter uses an Inverse Discrete Fourier

Transform (IDFT) in order to apply OFDM modulation to

the N parallel sub-streams. Then a parallel-to-serial module

converts the N parallel result from IDFT, to a serial stream

followed by digital-to-analog conversion [7]. In particular, by

selecting the IDFT size N equal to 2n, for some integer n,

the OFDM modulation can be implemented by the efficient

radix-2 IFFT algorithm [7].

B. LTE frame

The LTE signal in time-domain is based on frames, which

are 10 ms long and consist of 10 sub-frames each of 1 ms

duration. The sub-frames are divided further into two slots

each 0.5 ms long. Each slot consists of a number of OFDM

symbols, either six or seven, depending on whether a normal

or an extended cyclic prefix (CP) is used [9].

LTE uses a three dimensional scheme to manage the re-

source time, frequency, and space (antennas). The smallest

unit is the so-called Resource Element (RE), which consists

of a time interval of one OFDM symbol and one sub-carrier.

The area consisting of 12 sub-carriers and one time slot is

called Resource Block (RB) and contains 12 × 7 REs in the

case of normal CP. In each RB, four reference symbols (pilots)

are transmitted. The pilots position can be seen in Fig. 2.

III. FPGA-BASED TRANSMITTER ARCHITECTURE

The proposed architecture for the OFDM transmitteris depicted in Fig. 3. It is composed of 4 main mod-

ules: Frame Conformer (FC), FFT/IFFT processor,

Transmission Rate Controller (TRC), and OutBuffer (OB). All of them operate together as explained

below.

There are essentially three types of information to store in

Bank Register (BR): data configuration, pilots, and data

(both user and control data). All of them arrive as a bit-

stream from higher layer protocols and are introduced into

the transmitter word input. Data configuration is used to write

all internal registers from BR, which is composed of Pilot,

N null carriers, CP size, Slot Configuration

Figure 1: Generic OFDM Transmitter block diagram [7]

Figure 2: Signal content of LTE downlink sub-frame [9]

(SCR), and Frame Configuration (FCR) registers, as

well as a Data FIFO.

When wr input is asserted, the configuration parameter,

introduced in word input, is stored in its corresponding

register, selected by bank sel input. To configure frame size,

the number of slots in the frame and the number of symbols

per slot should be stored in FCR. Moreover, the configuration

for every OFDM symbol in the slot should be stored in SCR.

In the case of N null carriers and size CP registers,

the BW input is used to write the parameter in a specific

region of the selected register. Finally, data and pilots should

be stored in their respective registers.

The processing begins when the start input is asserted.

First, Main Control Unit (MCU) reads FCR in order to

determine the number of slots in the frame and the number

of OFDM symbols per slot. Secondly, MCU activates OFDMSlot Conformer (OSltC) to generate every OFDM sym-

bol in the slot. In order to generate an OFDM symbol, OSltCreads the current OFDM symbol configuration and sends it

to OFDM Symbol Conformer (OSyC). This module con-

trols the order in which data and pilots are processed by

the BPSK-QAM modulator. Thus, the modulated symbol

passes through the symbol multiplexer towards the symbol

output port. Additionally, when the OFDM symbol requires

null carrier insertion, OSyC pauses data and pilot modulation.

Consequently, the symbol multiplexer begins to feed zeros into

the symbols output port.

Once all modulated-symbols have been stored, MCU enables

IFFT processing, and OSyC pauses itself. The writing process

in the OB starts during the last stage of the IFFT processing.

When both processes finish, an OFDM symbol has already

been stored in ABCD FIFO. Then, the CP AGU module is

activated in order to generate addresses, which are used to

transfer the CP samples from the IFFT processor to the

X FIFO.

After that, transmission occurs, enabling the TRC module,

which remains active until the entire frame has been trans-

mitted. This module coordinates reading process in the OBin order to achieve the transmission rate required in LTE.

Simultaneously, FC repeats the process to write symbols in the

IFFT processor. However, the IFFT processing is paused

until the OB status indicates that there is enough space to store

Figure 3: Architecture of the proposed OFDM Transmitter

one more OFDM symbol. The entire process is repeated to

generate the rest of the OFDM symbols which comprise the

frame. An explanation of the main modules of the OFDM

transmitter is detailed below.

A. Frame Conformer

This converts the data bit-stream (user and control data) to

a sequence of modulated data, which is accepted by IFFTprocessor. Its internal modules are described below.

1) Bank Register: This was designed to configure dif-

ferent transmitter operation modes. All of its internal registers

are presented below.

• Data FIFO. This is used to store data, whether user or

control, which are introduced through word input. The

first introduced word represents data set 1, the second

introduced word represents data set 2, and so on. The first

data of each set is located in the Most Significant Bits

(MSB). The amount of data in each set is determined by

DM (Data modulation scheme) input and Data FIFOword length.

• Pilot Register. This is similar to Data FIFO.

The difference is that the amount of pilots in each set is

determined by Pilot Register word length divided

by 2.

• N null Carriers and CP size registers.

Both registers have as many locations as available

bandwidths for the transmitter. The first word introduced

is the parameter for the bandwidth 1, the second wordintroduced is the parameter for the bandwidth 2, and so

on.

• Slot configuration register. This has as

many locations as the amount of OFDM symbols per

slot. The information introduced through word input is

a set used to configure each OFDM symbol. The set

is defined as: {pilot distance, pilot offset, ena pilots}.

The first parameter determines how many sub-carriers

separate a pair of pilots in the OFDM symbol. The

second determines the initial sub-carrier, where pilots

are included. Finally, ena pilots parameter indicates the

presence of pilots in the OFDM symbol.

• Frame Configuration Register. This is em-

ployed in order to configure frame size. It has two

locations, the first is used to configure the number of slot

in the frame and the second for the number of OFDM

symbols per slot.

2) Deco BW: This module decodes BW input to maxFF-Taddr parameter —which determines the IFFT length—

according to Table I.

3) BPSK-QAM Modulator: Its main feature is that it can

perform BPSK, and 4, 16, and 64-QAM modulations using

only a mapper for all schemes and applying its corresponding

normalization factors.

4) OFDM Symbol Conformer: In order to generate a

sequence to assemble an OFDM symbol, OSyC should take

into account pilot distance, pilot offset, ena pilots, maxFF-Taddr, and N null carriers (Nnc) parameters. The sequence

length is determined by maxFFTaddr. This sequence is

conformed as follows. First, OSyC generates Nnc/2 zero

symbols. Next, OSyC generates a sequence of modulated

symbols including a zero symbol in the middle of the se-

quence. If ena pilots is asserted, then, data and pilots are

included in the sequence. Otherwise, only data are included.

Finally, Nnc/2 − 1 zero symbols are included at the end of

the sequence. For each symbol, OSyC generates an address

ranging from 0 to maxFFTaddr.

Table I: Parameters associated with Bandwidth decoder

BW Bandwidth [MHz] maxFFTaddr m

000 1.4 127 32001 3 255 16010 5 511 8011 10 1023 4100 20 2047 2

B. IFFT processor

A multi-core Variable Length (VL) FFT/IFFTprocessor based on Decimation-in-Time (DIT) Fast

Fourier Transform (FFT) radix-2 algorithm is proposed for

OFDM-engine. The N -point Discrete Fourier Transform

(DFT) of an input sequence x(n) is defined as follows:

X(k) =

N−1∑

n=0

x(n)WnkN , k = 0, 1, ..., N − 1 (1)

where WN = e−j 2πN are the twiddle factors, n is the discrete

time-domain index, and k is the normalized frequency-domain

index. In the same context, the Inverse Discrete Fourier

Transform (IDFT) can be expressed as:

x(n) =1

N

N−1∑

k=0

X(k)W−nkN , n = 0, 1, ..., N − 1 (2)

From the point of view of decimation, there are two

basic types of FFT algorithms: decimation in time (DIT)

and decimation in frequency (DIF). There is no difference

in computational complexity between them and the number

of samples must be a power of two. The DIT radix-2 FFT

algorithm divides the original sequence into two N/2-point

data sequences f1(n) and f2(n), corresponding to the even-

indexed and odd-indexed points of x(n), respectively. Then

N -point DFT can be computed as:

X(k) = F1(k) +W kNF2(k),

X(k +N/2) = F1(k)−W kNF2(k),

(3)

where, k = 0, 1, ..., N/2 − 1, F1(k) and F2(k) are the N/2-

point DFT of f1(n) and f2(n), respectively.

The subsequences F1(k) and F2(k) are recursively solved

applying the above formula. Thus, the elementary operation

is obtained, known as DIT butterfly (BF). Its pictorial repre-

sentation is shown in Fig. 4. In DIT radix-2 FFT algorithm,

log2(N) butterfly stages are necessary to calculate an N -point

FFT. During each stage, N/2 butterflies should be calculated.

For example, in the 8-point FFT signal flow diagram, shown

in figure 5, there are 3 butterfly stages and 4 butterflies are

calculated during each stage. The multi-core architecture can

be also interpreted from the example depicted in Fig. 5, where

a level 1 FFT processor can be assembled combining two

N/4-point FFTs to obtain an N/2-point FFT. The combining

process consists of applying the corresponding last butterfly

stage (LBFS). If the architecture is applied again so that two

level 1 N/2-point FFT processors are combined to obtain an

N -point FFT, then a level 2 FFT processor is obtained. By

assembling Lv levels, an FFT processor with Lv+1 available

Figure 4: Butterfly DIT radix-2

lengths can be obtained. The corresponding FFT length for

level l is determined as:

FFT length(l) =N

2Lv−l(4)

where N is a power of 2 and represents the maximum FFT

length, Lv is the amount of levels, and l is the current level,

which is an integer number ranged from 0 to Lv.

The proposed FFT/IFFT processor architecture is shown

in Fig. 6. It is a level Lv processor mainly composed of

two level Lv − 1 FFT/IFFT processors (C1 and C2),

a control unit (CU), an address manager (AM), a

size decoder, two external BFs (BF), and two ROMs

(ROM_Wn_e and ROM_Wn_o) used to store twiddle factors.

A general description of its functionality is as follows.

First, size FFT input is decoded into u size FFT and

N Nb2 signals. The first signal is used to indicate the FFT

size for C1 and C2 processors; and the second signal is used

to determinate if the two level Lv − 1 processors will

be combined or not. After that, a sequence of samples and

addresses are introduced in sec e and addr e inputs, respec-

tively. The AM processes the address to select the processor,

C1 or C2, where the corresponding sample will be stored.

When start FFT input is asserted, the level Lv − 1 FFT

processing begins in one or both processors, depending

on N Nb2 signal. Once it finishes, CU declares the process

complete if N Nb2 is asserted. If it is not asserted, then CUactives LBFS of level Lv. During this process, sets of four

samples are read from C1 and C2, as well as two twiddle

factors from ROM_Wn_e and ROM_Wn_o. Such samples are

processed by a pair of BFs, then a write back operation is

applied to the four resulting samples of each set. When the

LBFS has finished, CU declares the process complete using

busy done signal.

An important setting of the FFT/IFFT processor is

that it is able to feed the result during the LBFS of the

corresponding level. This result is fed through A e, B e, A oand B o outputs. Depending on the N Nb2 signal, the result

could be fed from level Lv − 1 LBFS, which is executed in

C1, or from level Lv.

Our FFT/IFFT processor was designed ad-hoc for

the aforementioned transmitter, considering four hierarchical

levels and a maximum length of N = 2048 samples. There-

fore, it is capable of performing five different FFT lengths

(N , N/2, N/4, N/8 and N/16) with the same data-path.

Figure 5: Example of an 8-point DIT radix-2 FFT [8].

Figure 6: Proposed architecture for level Lv Variable Length FFT/IFFT processor

The only constraint is that transformation cannot begin until

the entire input sequence has been introduced. However, the

processor is able to feed the result during LBFS. This

feature compensates the time used for the input sequence

loading.

C. Transmission Rate Controller

This module manages the transmission rate required for

each bandwidth (BW) specified in LTE standard. Since a clock

rate of 61.44 MHz was used for the transmitter, TRC enables

reading in OB every m clock cycles. The value for m is

a multiple of two and depends on maxFFTaddr, which is

related to the BW chosen. Table I shows all possible values

for m. TRC carries out two steps during OB reading process.

During the first, it coordinates rd control signals to read

the CP samples. In the last step, it coordinates rd controlsignals to read all the samples of the corresponding OFDM

symbol. Both steps are repeated until the entire frame has been

transmitted.

D. Out buffer

This module is composed of two FIFO memories: ABCDFIFO, used to store the OFDM symbols samples, which are

fed during the LBFS; and X FIFO, used to store the CP

samples of the corresponding OFDM symbol. OB uses statussignals to indicate if there is enough space to store one more

OFDM symbol.

IV. IMPLEMENTATION RESULTS

The proposed transmitter architecture was implemented in

RTL level using Verilog hardware description language. This

transmitter was synthesized using EDA tool Xilinx ISE v14.7

and targeted to a kintex7 XC7K70T FPGA. All signals are

complex-valued and were represented using signed fixed-point

two’s complement. Its synthesis results are summarized in

Table II and compared with the OFDM transmitters mentioned

in Section I. Since our FFT/IFFT processor uses 43 butterfly

Table II: Synthesis comparison of the proposed OFDM Tx

[6] [5] ProposedStandard 802.11a CMMB/DAB LTE

Xilinx ALTERA XilinxTarget XC2V3000 EP4CE115F29C7 Kintex7

4FG676 XC7K70TIFFT lengths 64 4096, 2048, 2048, 1024,

512 512, 256,128

Block RAM 12 54/38 (M9Ks) 24Slice Registers 2353 - 6233

Slice LUTs 2814 - 22240LEs - 11078/10853 -

DSPs - 26/26 184Frequency [MHz] 80 - 61.44Max. freq.[MHz] 91.948 - 69

Table III: Execution time for several FFT lengths

FFT length Total exe. Time Partial exe. Time[samples] [clock cycles]

128 904 -256 1033 904512 1290 10331024 1803 12902048 2828 1803

modules and each uses 4 DSP blocks, so it is composed of 172

DSPs. Nevertheless, [5] uses many more Block RAMs than

the proposed transmitter. Although Block RAM consumption

in [6] is less than ours, FFT length should be considered. It

is much smaller than our proposed FFT/IFFT processor. None

of them have the high-reconfigurability degree feature of the

our designed architecture.

Although the proposed FFT/IFFT processor uses 46

BF modules, its advantage is memory consumption, which

is equal to N -samples to be processed. This represents an

advantage, because in our design, all memories were inferred

and translated to a dedicated block-RAM (BRAM). Hence,

for a FFT length of 2048 samples and 32-bit word length

(16 bits for real and imaginary parts), the resulting memory

consumption is 8 KB. For the performance of the FFT/IFFTprocessor, we considered two execution times; the first

one is the total execution time, which is the time used to

process the FFT/IFFT, since start input is activated until

busy done output declares process done. The second is the

partial execution time, which is shorter than the first, because

in this case, time used to carry out the LBFS is not considered

as processing time, but rather as time used to feed the result.

The total execution time (Tt) in the level 0 FFT/IFFTprocessor is determined as:

Tt(0) = s · b · c+ log2(FFT length(0)) + 1 (5)

where s is the number of butterfly stages used to process a

level 0 FFT, b is the number of butterflies per stage in level

0, c is the number of clock cycles to calculate a butterfly

operation, which has a value of 2 in this implementation, and

FFT length was defined in eq. (4).

Similarly, the total execution time (Tt) for the higher levels

is defined as:

Tt(l) = Tt(l − 1) + 2l−1 · b · c+ 1 (6)

In this case, l ranges from 1 to Lv.

The partial execution time (Tp) for level 0 is not consid-

ered, because it is not a variable length IFFT/FFT processor;

therefore, it does not execute LBFS using two external BFs.

In the case of level 1, (Tp) equals Tt(0). Moreover, for the

higher levels, Tp is defined as:

Tp(l) = Tp(l − 1) + 2l−2 · b · c+ 1 (7)

In this case, l ranges from 2 to Lv. Table III shows both, total

and partial, execution time results for the proposed FFT/IFFTprocessor.

The functionality of our OFDM transmitter was tested using

hw/sw co-simulation environment. A spectrum analyzer tool

was connected to the transmitters output. Fig. 7 shows the

OFDM symbol obtained for 3 MHz bandwidth and 16-QAM

as modulation scheme. Since spectrum analyzer averages

the OFDM symbols, it is not possible to distinguish pilots

clearly, because some OFDM symbols do not include them.

Finally, the SQNR (signal-to-quantization-noise ratio) perfor-

mance of the transmitter is conditioned by the FFT/IFFTprocessor SQNR, thereby it can be used as an indirect

Figure 7: Transmitter output spectrum for 3 MHz/16-QAM

OFDM symbol.

Figure 8: SQNR performance of the FFT/IFFT proc.

measure of this metric. Thus, Fig. 8 depicts the SQNR his-

togram from 100 2048-point length transformations performed

by the FFT/IFFT processor, obtaining an SQNR average

of 50.13 dB. Hence, the transmitter’s SQNR performance is

close to this value.

V. CONCLUSIONS

In this paper, a reconfigurable OFDM transmitter architec-

ture for 4G-LTE applications was presented. It has the capa-

bility of selecting on-the-fly from five different transmission

modes: 1.4, 3, 5, 10, and 20 MHz; three modulations: 4/16/64

QAM, frame size, OFDM symbols/slot, and the assembly

configuration parameters of each OFDM symbol, such as the

number of null carriers, the CP size, the pilot inclusion, etc.

Although the transmitter presents moderate hardware resource

consumption, this is compensated by its high reconfigurability

and good SQNR, which allow its inclusion in the multi-

standard designs for future communication systems.

ACKNOWLEDGMENT

This work was supported by CONACyT scholarship

300943, CONACyT-240813 research project, and PROFAPI-

1545 grant.

REFERENCES

[1] Cox, C.I. An Introduction to LTE LTE, LTE-advanced, SAE, VoLTE and4G Mobile Communications. 2014

[2] Revanna, D. and Anjum, O. and Cucchi, M. and Airoldi, R. and Nurmi, J.A scalable FFT processor architecture for OFDM based communicationsystems. Embedded Computer Systems: Architectures, Modeling, andSimulation (SAMOS XIII), 2013 International Conference on, 2013.

[3] Romero-Aguirre, E. and Parra-Michel, R. and Carrasco-ALvarez, Robertoand Orozco-Lugo, A. G. Configurable transmitter and systolic channelestimator architectures for DDST communications systems Int. J. Recon-fig. Comput., January 2012, issn = 1687-7195

[4] Bautista-Contreras, B. and Parra-Michel, R. and Carrasco-Alvarez, R.and Romero-Aguirre, E. A SDR architecture based on FPGA for multi-standard transmitter. Global Conference on Signal and InformationProcessing (GlobalSIP), 2013 IEEE, 2013.

[5] Zhang, B. and Guo, X. A Novel Reconfigurable Architecture for GenericOFDM Modulator Based on FPGA. In Advanced Communication Tech-nology (ICACT), 2014 16th International Conference on, pages 851-854.IEEE, 2014.

[6] Garcia, J. and Cumplido, R. On the design of an FPGA-Based OFDMmodulator for IEEE 802.11a. Electrical and Electronics Engineering,2005 2nd International Conference on, 2005.

[7] Dahlman, E. and Parkvall, S. and Skold, J. LTE/LTE-Advanced for MobileBroadband. Elsevier Science, 2011.

[8] Proakis J.G. and Manolakis D.G. Digital Signal Processing. Prentice HallInternational editions, Pearson Prentice Hall, 2007.

[9] Zarrinkoub, H. Understanding LTE with MATLAB: From MathematicalModeling to Simulation and Prototyping. Wiley Desktop Editions, 2014.