reconfigurable radar waveform and timing generation module ... archive/irsi-15/15-fp-001.pdf ·...

Reconfigurable Radar waveform and Timinggeneration Module with target simulation

functionality for Exciter applications

Prashant kumar Letha, Sarala Balaraman, Renulakshmi Ramesh, Hari Krishnan ICentral D&E, Radar signal processing group, BEL Bangalore

Bangalore-560013.Email: [email protected]

AbstractThis paper presents an FPGA based design of

radar waveform and timing generation with BITEfunctionality for target simulation. These three functionsof waveform, timing and BITE generation are integralpart of Radar exciter and are very crucial for Radaroperation. The hardware is primarily designed forgeneration of LFM/NLFM waveform, timing and BITEon-the-fly based on the parameters received from Radarcontroller over gigabit Ethernet link. This designapproach is fully reconfigurable for porting other Radarwaveforms without any hardware re-spin. The presentdesign is evaluated for existing Radar platform andavailable as single module with conduction cooledmechanical housing.

Keywords: Field programmable gate array (FPGA),Built in test equipment (BITE), linear frequencymodulation (LFM), peak side lobe level (PSL), Radarcontroller (RC)

I. INTRODUCTIONPulsed Doppler Radars determine the range

of a target using pulse-timing techniques and usesDoppler Effect of the returned signal to determinetarget object velocity. Different waveforms areemployed to enhance the radar performance, in termsof side lobe reduction, pulse compression ratio andoverall system SNR.

Pulsed radar waveforms can be completelycharacterized by carrier frequency, pulse width, PulseRepetition Frequency (PRF), pulse modulation andmodulation bandwidth. Radar design enables thechoice of carrier frequency, while pulse width andbandwidth are decided by processing gain and rangeresolution.

In modern radars the waveform generationand, modulation is performed digitally usingFPGA’s. This approach provides extreme flexibilityof implementation including portability of multipletypes of waveforms, fully pipelined digital signalprocessing and in-system programmability for futuresystem upgrades.

Digital generation methods of frequencymodulated continuous wave signals include directwaveform synthesis and frequency synthesis. Thesignal can be generated directly at Intermediatefrequency (IF) or from its baseband components and

I/Q modulation done to form the analog IF signal.Subsequently the IF signal is up-converted to Radaroperating frequency in analog domain.

In the digital up-conversion (I/Qmodulation) the digital samples of LFM waveform atthe desired frequency, pulse width and bandwidth aregenerated offline in MATLAB and stored in FPGABRAM or external memory. Based on the commandsfrom RC, these waveform coefficients are read, upsampled and multiplied by 60 MHz reference signalgenerated by FPGA based DDS. Further thesesamples are band pass filtered and interfaced to DACfor generating LFM chirp at 60 MHz IF.This waveform is further up-converted to the radar’soperating frequency and transmitted.

II. DESIGN APPROACHThe design presented in this paper is part of

Radar Exciter receiver which performs the threebasic functions of Exciter i.e., Waveform(LFM/NLFM), Timing control and, BITE generation.The other modules include power supply, DDS basedsynthesizer, up converter, four channel receiver. Thesystem level block diagram is shown in theFigure1

Figure1. Exciter-Receiver System block diagram

10th International Radar Symposium India - 2015 (IRSI - 15)

NIMHANS Convention Centre, Bangalore INDIA 1 of 5 15-19 December 2015

The hardware for this module is based on Xilinxkintex7 series FPGA. Provision is made for twogigabit Ethernet links for connectivity to RC withexternal memories DDR2 and Flash for storing thewaveform coefficients. High speed 1.2Gsps DAC isprovided for generating LFM chirp waveform at 60MHz IF. Other components include on boardtemperature sensor for temperature monitoring andtransceivers (RS422/TTL) for status monitoring andcontrol signal generation for other Radar subsystems. The board level block diagram is shown inthe Figure 2. The entire module is designed forconduction cooled chassis and, for adaptability toharsh operating environments, environmental stressscreening (ESS) tests are done.

1. Waveform generation:

Linear frequency modulation (LFM/NLFM)waveform has been chosen for the presentapplication. A long pulse can have spectralbandwidth as a short pulse if the long pulse ismodulated in frequency or phase. If the frequencyincreases linearly from f1 to f2 over the duration ofpulse (up chirp) and, if the frequency decrease withtime then it is down chirp.

The LFM up-chirp instantaneous phase canbe expressed by,Ψ (t) = 2*π*(f0 * t + µ * t2 /2), -t/2 <τ<t/2 ………(1)

Where, f is the radar centre frequency,µ=2πB/τ is the LFM coefficient

Thus the instantaneous frequency is given by:f(t) = (1/2*π)*d/dt …………………. (2)

(Ψ(t))= f0+µ*t,-t/2 < τ < t/2 ………………... (3)Similarly, the down-chirp instantaneous frequency isgiven by,f (t) = (1/2*π)* d/dt(Ψ(t))=f0-µ* t, -t/2< τ < t/2…(4)

The linear frequency modulationcoefficients are computed as per above equations.The sampling frequency is chosen corresponding tothe bandwidth of the waveform to be generated.Figure3 and 4 shows plots of LFM waveform at baseband level. Main advantages of LFM waveform areinsensitivity to Doppler shifts, high range resolution.

Figure3. I-Q samples generated at Base band level

Figure4. Pulse width 18uS Band width 5MHz Baseband spectrum view

2. UP-conversion to IF stage

The basic band pass signal representation isgiven byX (t) =XI (t) cos2πf0t- XQ (t) sin2πf0t ……………… (5)Where XI (t) and XQ (t) represents I and Qcoefficients respectively, f0 is the radar centrefrequency at IF level. Cosine and sine components off0 are generated by FPGA based DDS. Modulation isperformed using Xilinx system generator designflow. After modulation output samples are band passfiltered in FPGA and fed to Digital to analogconverter.

Figure2. Board level block diagram

3. NLFM waveform significance

LFM matched filtering results in range sidelobes. These side lobes are often undesirable becausethey mask small targets or may they be mistaken fortargets themselves. NLFM matched filtering hasbetter detection and estimation characteristics thanLFM with side lobe control. The phase modulationfunction for NLFM is designed using Taylor seriescorrection. It is given by

N

Ψ NLFM (t) = πβt2/τ- πβτ Σ Kn/πn cos (2π nt/τ) … (6)n=1

Coefficients are calculated using aboveequations and up conversion is performed. So at thereceiver no weighting function (windowing) isrequired. This results in peak side lobe level isdecreased to -40db. NLFM waveform is alsovalidated using MATLAB. Similarly otherwaveforms can also be ported without anymodification in the present hardware.

4. Timing generation:

In the present design, FPGA receives50MHz master clock from synthesizer which is usedas reference for timing generation for various radarsub systems. Radar controller sends the dwellparameters scheduled on a dwell to dwell basis to theFPGA over Ethernet link. Dwell parameters includetype of waveform (LFM/NFLM), pulse width, PRF,



bandwidth (5/10 MHz), number of pulses withindwell along with information to SP and othermodules.

Complete custom UDP/IP hardware stack inVHDL is developed and used in FPGA to receive thedwell and bite parameters. Waveform parameters arepassed onto the waveform generation module and,timing information is used to generate Dwell, PRTand other control signals. A tight hand shakingmechanism is employed between RC and FPGA tomaintain synchronization. These timings generatedby the FPGA are used to synchronize the waveformtransmission with all the subsystems of the radar.

5. BITE generation:

Modern radars provide target simulationmode to validate various sub systems of Radarwhenever it is offline. BITE targets generated act asecho returns from real targets. There is provision ofgenerating targets with or without Doppler henceboth stationary as well as fixed targets can beemulated.

The provision of BITE mode of operation ismade in the present hardware by including separatededicated Ethernet link to the RC. BITE parametersinclude number of targets with target range, spacingbetween targets, approaching or receding targets withDoppler and attenuation values for sum, azimuth, andelevation channels. These parameters are received bythe FPGA, targets generated during pulse off time.

In addition to target BITE generation thisEthernet link is also used to send status informationto RC. All other subsystems send status informationover dedicated RS422/TTL lines to this module, andthe status information is consolidated and sent to RCon regular basis.

III. IMPLEMENTATION ARCHITECTURE

The entire design is based on single XilinxKintex7 series FPGA which is manufactured usinglow power 28-nm process technology. It provideslow cost, low power 1.0V core supply, 900 pinFBGA package, with around 350 high range (HR)I/O’s supporting(3.3V to 1.2V) and high performance(HP) I/O’s (1.8V to 1.2V). It has Block RAMmemory of around 25Mbit with 1540 DSP48E1slices and 406720 logic cells. Based on 6-input LUTarchitecture provides implementation of wide inputcombinational logic functions.

The functional block diagram is shown inthe Figure5. The front end interface to RC is gigabitEthernet link where all the parameters arecommunicated over UDP/IP link. FPGA interfaces toexternal PHY chip in GMII mode, implements theMAC layer functionality as well as custom UDP/IPstack in VHDL. The dwell and BITE parameters arewritten into dedicated BRAM memories. Based onthe handshaking mechanism employed,acknowledgement is sent to RC for every dwell andBITE packet. Timing generation is initiated by RCby sending dwell start packet and the corresponding

dwell parameters are read from BRAM memory andloaded to Timing generation module. The waveformcoefficients are generated in MATLAB for therequired pulse width, bandwidth and stored inBRAM memory. Presently only LFM/NLFMwaveforms are implemented. These coefficients areread from BRAM and up-sampled, and multiplied bysine and cosine signals at 60 MHz in digital I/Qmodulation module. FPGA based DDS is used togenerate the sine and cosine signals.

Figure5. Functional block diagram

The output samples are band pass filtered and fed toDAC for analog LFM chirp generation. This LFMchirp signal is given to external up converter modulefor conversion to Radar frequency and transmitted.

Provision of storing multiple Radarwaveform coefficients in hardware is done by writingthese coefficients in external 32MB flash memory.On power-on these coefficients can be copied intoexternal DDR2 memory for faster memory access.From DDR2 coefficients can be buffered in FIFOand the same process of I/Q modulation can be done.Separate FSM’s are implemented for both Timingand, BITE generation. The process of updating thewaveform coefficients into external Flash memory isdone in software using embedded Micro blazemicrocontroller. PC based GUI used to interface toRC for receiving dwell and BITE parameters onEthernet link. The output LFM waveform at 60MhzIF is observed in spectrum analyzer and timing onCRO.

Additional glue logic implemented tointerface to other modules of the exciter receiver.These modules include (i) DDS based synthesizer for50 MHz timing reference clock and, 400 MHzsampling clock for DAC and LO1 for up conversion,(ii) Up converter module takes the 60 MHz LFM,LO1 and generates LO2 and further converts it to Cband signal for transmission.



IV. TEST RESULTS

Figure6.SFDR measurement using spectrum analyzer (400MHz-clk input, 60MHz output) 60MHz level=-2.17dBm and

next highest peak within Nyquist zone is @ 180MHz= -76.17dBm.SFDR=74dBc

Figure7. IF spectrum for 18uS Pulse width 5MHz Band width

Figure8. Multiple targets generated for 10km range 300m spacing

Figure9. Real time spectrum view of IF output (LFM)

Figure10. Real time spectrum view of IF output (NLFM)

Figure11. 18uS Pulse width LFM scope output



V. CONCLUSION

The design presented in this paperimplements all three basic functions of Radar exciterwaveform, timing and, BITE generation in a singleFPGA based module. This module is a good form fitreplacement for other OEM vendor solutions offeredas three separate modules for the same functionality.It addition to this it can be easily re-configured toport different Radar waveforms with IF frequencysupport upto 120Mhz.The entire module is housedinside a conduction cooled enclosure and it isdesigned to meet rugged operating conditions ofMilitary Radars.

ACKNOWLEDGEMENT

We would like to acknowledge the supportof Mr. Philip Jacob Executive Director, C-D&E,BEL, Mr.Udayshankar, Manager, D&E (MR) BEL.We would also thank Mrs. Rose Abraham Sc.E, Mr.Subhasis Marndi Sc.D, Mr.O.C Vishnu Sc.D ofLRDE for their technical guidance, suggestions andconstant encouragement.

REFERENCES

[1]. Merrill Skolinik, “Introduction to Radar Systems,” 2nd ed.,McGraw-Hill[2] Lav R Varshney and Daniel Thomas, “Side lobe reduction formatched filter range processing”, IEEE, Radar Conference, 2003.[3] George W Stimson “Introduction to Air-borne radar”, 2nd ed.,Scitech Publishing Inc.[4] Bassem R Mahafza, “Radar Signal Analysis and processingusing Matlab”, CRC press, Taylor and Francis group.[5] Xilinx IP Cores and System generator User guides.

BIO-DATA OF AUTHORS

PRASHANT KUMAR LETHA received B.Ein electronics engineering degree from OsmaniaUniversity; Hyderabad. He received theM.TECH degree in Micro ElectronicsEngineering from Institute of Technology (IT),Banaras Hindu University (BHU), Varanasi. Hejoined Central Research Laboratory, BEL as aresearch staff in the year 2000. Presently he is

working in C-D&E, RSP group. His research activities includeVLSI and embedded processing, radar array signal processing andradio communication.

SARALA BALARAMAN received her B.E inelectronics engineering degree from College ofEngineering, Guindy, Chennai. She joinedBEL Bangalore in the year 1988 as designengineer. After working in D&E Navalsystems for long time, she joined C-D&E, RSP

group in BEL 2007 and presently heading the division. Herresearch activities include radar signal processing, adaptive beamforming for active phased array Radars.

RENULAKSHMI RAMESH received herM.E degree from P.S.G College ofTechnology, Coimbatore. She joined CentralResearch Laboratory, BEL as a research staffin the year 2001. Presently she is working inC-D&E, RSP group in BEL. Her fields ofinterest include Radar Signal Processing,

Image Processing and FPGA based designs.

HARIKRISHNAN I received B.Tech degreein Electronics and Communication Engineeringfrom College of Engineering Trivandrum. Hejoined BEL in May 2013. Currently he isworking as a Deputy engineer in C-D&E RSP.Presently he is working on FPGA Based

designs for RADAR signal processing.



reconfigurable radar waveform and timing generation module ... archive/irsi-15/15-fp-001.pdf ·...

Documents