recent development of finfet technology for cmos logic...
TRANSCRIPT
Recent Development of Recent Development of FinFET Technology for CMOS FinFET Technology for CMOS
Logic and MemoryLogic and Memory
ChungChung--Hsun LinHsun Lin
EECS DepartmentEECS DepartmentUniversity of California at BerkeleyUniversity of California at Berkeley
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 2
OutlineOutlineWhy FinFETWhy FinFET
FinFET processFinFET processUnique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, QM, , QM, volume inversionvolume inversion
IssuesIssues
Recent Recent FinFETFinFET DevelopDevelopTripleTriple--gate FinFET, Omega FET, gate FinFET, Omega FET, NanowireNanowire FinFETFinFET, , Independent gate, MultiIndependent gate, Multi--channel FinFET, Metalchannel FinFET, Metal--gate/highgate/high--K K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemoryDRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
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MOSFET ScalingMOSFET Scaling
Same transistordesign concept
2000 2005 2010 2015 20201
10
100
GAT
E LE
NG
TH (n
m)
YEAR
LOW POWER HIGH PERFORMANCE
ITRS 2001 Projection
Technology Scaling
Investment
Market Growth
Better Performance/Cost
The first transistor 1947
The Power5 microprocessor
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Scaling : MooreScaling : Moore’’s laws law
•Source: Intel
Technology Drivers
• Reduced cost / function
• Improved performance
• Greater circuit functionality
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BulkBulk--SiSi MOSFET Scaling IssuesMOSFET Scaling Issues
Leakage current is the primary barrier to scalingTo suppress leakage, we need to employ:
Higher body doping lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric higher gate leakageUltra-shallow S/D junctions higher Rseries
Substrate
Gate
Source DrainLeff Nsub
Xj
LgTox
Desired characteristics:
- High ON current (Idsat)- Low OFF current
G
S
Dcourtesy of Prof. Kuroda
Keio University
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Issues for Scaling Issues for Scaling LLgg to <25 nmto <25 nm
VT variation (statistical dopant fluctuations)
Leakage
Incommensurate gains in Idsat with scaling
— limited carrier mobilities
— parasitic resistance
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Advanced MOSFET StructuresAdvanced MOSFET Structures
Leakage can be suppressed by using a thin body
Ultra-Thin Body
GateGate
Silicon Substrate
Source DrainTBOX
TSiSiO2
SOI
Double Gate
Source Drain
Gate 1Gate 1 Vg
Tox
TSiSOI
Gate 2Gate 2
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ThinThin--Body MOSFETsBody MOSFETs
Control short-channel effects with Tbody
No channel doping needed!Relax gate oxide (Tox) scaling
Double-Gate is even more effectiveScalable to 10nm gate lengths
TbodyUltra-Thin Body Double-Gate
Gate
Source Drain
Gate
Buried Oxide
Substrate
Source Drain
Gate
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Electric Field ReductionElectric Field Reduction
Reduced vertical field in DG and UTB
No doping =No Qdepl!
Expected to benefit:MobilityGate Leakage
Si
deplinveff ε
QQηE
+=
Gate
Buried Oxide
Substrate
Qinv
Thin-Body
Gate Qinv
QdeplBulk
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ThinThin--Body MOSFETsBody MOSFETs
Control short-channel effects with Tbody
No channel doping needed!Relax gate oxide (Tox) scaling
No channel doping needed!
↑ Ion
↓ Cload
Double-Gate is even more effectiveScalable to 10nm gate lengthsPotentially less Vt scatter (dopant fluctuation)
— Improved mobility• Lower vertical electric field• No impurity scattering
— Improved swing• Better control of SCE• Lower VT
— No depletion or junction capacitance
Bulk
Idra
in
Vgate
DG
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Circuit level benefitsCircuit level benefits
Thin body devices
Good control of SCE
Steep Sub-threshold swing
Higher Idsat
Lower Capacitance - No Cjunc and Cdepl
Better CV/I delay at lower power 2
468
10
20 Bulk UTB DG
Technology Lgate [nm]FO
4 In
vert
er D
elay
[ps]
50 35 25 18
Tbody,UTB= 5nm
Tbody,UTB< 5nm
Source: Leland Chang
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DoubleDouble--Gate MOSFETsGate MOSFETs
Gate 1
Gate 2Current flow
S
Planar DG MOSFET
D
Vertical DG MOSFET
S
D
Current flow
Gate 1Gate 2
FinFET
S
D
Current flow
Gate 1Gate 2
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MultiMulti--Gate FinFETGate FinFET
Rotation allows for self-aligned gatesLayout similar to standard SOI FET
Gate
Drain Drain
Gate
Drain
Gate
Source
Gate
Source
Source
Drain
Gate
PlanarDG-FET
90°Rotation FinFET
Gate
Source Drain
Gate
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Poly Gate Deposition/Litho
Gate EtchSpacer Formation
S/D Implant + RTASilicidation
FinFET Process FlowFinFET Process FlowSiO2
SOI SubstrateFin Patterning
Si Fin
BOX
Poly
Resist
Si3N4Spacer
NiSi
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FinFET Device StructureFinFET Device Structure
• All features defined by optical lithography and aggressive trimming
Gate
Source
Drain
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10nm FinFET TEM10nm FinFET TEM
220ÅSiO2 cap
Lg=10nm
BOX
NiSi
Poly-Si
Si Fin
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10nm FinFET I10nm FinFET I--VV
Dual N+/P+ poly gates:- Need VT control
Low DIBLNMOS: 120 mV/V PMOS: 71 mV/V
Good SCE despite thick Tox (27Å EOT) & Wfin(26nm)- Due to large S/D
doping gradient &spacer thickness
-1 0 110-9
10-7
10-5
10-3
10-9
10-7
10-5
10-3
NMOS PMOSS=101
mV/decS=125
mV/dec
Vd=1.2V
0.1V
Vd=-1.2V
Dra
in C
urre
nt [A
/μm
]Gate Voltage [V]
-0.1V
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ShortShort--Channel EffectsChannel Effects
Acceptable DIBL and subthreshold slope down to below 20nm Lgate
Nearly ideal (60mV/dec) subthreshold slope at long Lgate
NMOS better than PMOS due to slower As diffusion 0 20 40 60 80 100
0
40
80
120
160
0
40
80
120
160
NMOS PMOS
Wfin=26nm
DIB
L (m
V/V)
Subt
hres
hold
Slo
pe (m
V/de
c)Gate Length (nm)
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OrientationOrientation
Rotation by 45º changes orientation from (110) to (100)Intermediate rotation similar to (111)
<100>
<110>
(110)Surface
Gate
Sour
ceDr
ain
(110) (100)
~(111) (110)
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0.2 0.4 0.6 0.8 1.00
100
200
300
400
500Oxynitride
(111)
(110)
(100)
Elec
tron
Mob
ility
[cm
2 /Vs]
Effective Field [MV/cm]0.2 0.4 0.6 0.8 1.0
0
100
200
300
400
500Oxynitride
(111)
(110)
(100)
Hol
e M
obili
ty [c
m2 /V
s]
Effective Field [MV/cm]
How Mobility ChangesHow Mobility Changes
By shifting away from (100):μe is degraded, μh is enhanced
Can we benefit from changing the N/P ratio?
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0
5
10
15
20
Oxynitride
Fanout=4
% D
elay
Spe
edup
vs.
(100
)
Orientation(100) (111) (110) (100) NMOS
(110) PMOS
↑μh, ↓μe
NAND
Inv
NOR
Gate DelayGate Delay
PMOS enhancement (20%) is larger than NMOS degradation (8%)
Net delay improvement
Trade off μh and μe
NOR: PMOS stackμh very importantMost improvement
NAND: NMOS stackμh less importantLeast improvement
Lgate=35nm
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Optimized FinFETOptimized FinFET
Trade off layout area for performance
Gate
Source
Drain
Source
Drain
Gate
Source
Drain
SourceDrain
(100) NMOS(110) PMOS
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FinFET Layout AreaFinFET Layout Area
Non-(100) orientation saves areaHigher PMOS Idsat reduces drawn W
45º orientation is less area efficient for smaller WThese devices are small anyway…does it matter?Use only in critical path?
0.0
0.2
0.4
0.6
0.8
(100) (110) (111) 45oN / 90oP 90oN / 45oP
Idsatn,p=1.1mALa
yout
Are
a [μ
m2 ]
0
10
20
30
40
50
Idsatn,p=110mA
Layo
ut A
rea
[μm
2 ]
Inverter
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Hybrid-Orientation-Technology (HOT)
Super HOT: SOI versionDSB: bulk version
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VVTT: What CMOS Needs: What CMOS Needs……
Need symmetrical VT’s for proper CMOS operation
Need low VT’s for speed
Input
Ou
tpu
t
Inverter Response
VDD
VDD0
VIN=VTN
VIN=VDD-VTP
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Single gate materialVTn = -VTp = 0.4V
N+/P+ PolyVTn = -VTp = -0.2V
• For low body doping, desired ΦM values are:
~ 4.5 eV for NMOS~ 5.0 eV for PMOS
Need two separate work functions for NMOS and PMOS!
Gate Work FunctionGate Work Function
4.2 4.4 4.6 4.8 5.0 5.2-0.2
0.0
0.2
0.4
0.6
0.8
1.0
4.95eV
VT=0.2V
4.52eV
P+ Pol
y
N+ Pol
y
VT=0.4V
VTn -VTp
Thre
shol
d Vo
ltage
[V]
Gate Workfunction [eV]
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Molybdenum Molybdenum ΦΦMM EngineeringEngineeringby Ion Implantationby Ion Implantation
ΦM can be lowered by N+ implantation and thermal annealΔΦM increases with
doseenergy
(N segregates to SiO2interface & forms Mo2N)
Anneal time = 15m except for 900oC (15s)TMo = 15nm
P. Ranade et al., IEDM 2002
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MoMo--Gated FinFETs (PMOS)Gated FinFETs (PMOS)
Y.-K. Choi et al., IEDM 2002
-0.8 -0.6 -0.4 -0.2 0.0 0.210-13
10-11
10-9
10-7
10-5
10-3
Dra
in C
urre
nt, I
d [A
/um
]
Gate Voltage, Vg[V]
Mo MoN(N2=5x1015cm-2)
Vt shift
Lg=80nm, TSi=10nmVds=0.05V
• Alternative technique:Full silicidication (NiSi) of n+/p+ Si gates(J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002)
• |Vt|=0.2V for lightly doped body, and is adjustableby N+ implantation
Potential issues include: - dopant penetration- thermal stability - stress/adhesion- gate dielectric reliability
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Corner Effect in Triple or More GatesCorner Effect in Triple or More Gates
Corner EffectCorner EffectDifferent VDifferent Vthth at corner regionat corner regionSignificant subthreshold leakage currentSignificant subthreshold leakage currentStrong corner radius, body doping dependenceStrong corner radius, body doping dependence
B. Doyle et al., VLSI Tech., p. 133, 2003
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Corner Effect [1]Corner Effect [1]
0 5 10 15 20 25 300
1
2
3
Cur
rent
Den
sity
(A/c
m2 )
Position (nm)
z direction y direction
0 5 10 15 20 25 300
1x106
2x106
3x106
4x106
Cur
rent
Den
sity
(A/c
m2 )
Position (nm)
z direction y direction
DESSIS 3DESSIS 3--D device D device simulatorsimulatorIdeal rectangular fin Ideal rectangular fin shapeshapeNNsubsub=1e15cm=1e15cm--33
Vg=1 V
y
z Vg=0.2 V
y
z
2D current density distribution 2D current density distribution S
D
G
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Corner Effect [2]Corner Effect [2]
Nsub=5e18cm-3
Vg=0.2 V
Vg=1 V
2D current density distribution
y
z
y
z
2D current density distribution
-0.015-0.010
-0.0050.000
0.0050.010
0.015
0
1x1020
2x1020
3x1020
4x1020
0.000
0.0050.010
0.0150.020
0.0250.030
Ele
ctro
n D
ensi
ty (c
m-3)
Y Axis
X Axis
flat
corner
-0.015-0.010
-0.0050.000
0.0050.010
0.015
0.0
5.0x106
1.0x107
1.5x107
2.0x107
0.000
0.0050.010
0.0150.020
0.0250.030
Cur
rent
Den
sity
(A/c
m2 )
Y Axis
X Axis
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3D Simulation w/ Various Shape of Corner3D Simulation w/ Various Shape of Corner
Lg=1μm, Wsi=30nm, Hsi=30nm, Tox=1nmR=0, 5, 10, 15m
0.0 0.5 1.0 1.5 2.01E-13
1E-11
1E-9
1E-7
1E-5
Nor
mal
ized
Dra
in C
urre
nt (A
/μm
)
Gate Voltage (V)
R=15nm R=10nm R=5nm R=0nm
0.0 0.5 1.0 1.5 2.00.0
2.0x10-5
4.0x10-5
6.0x10-5
8.0x10-5
Nor
mal
ized
Dra
in C
urre
nt (A
/μm
)
Gate Voltage (V)
R=15nm R=10nm R=5nm R=0nm
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Short Channel BehaviorShort Channel Behavior
MG device with sharp corner shows better short channel behavior than the rounded corner
0 200 400 600 800 10000
20
40
60
80
100
D
IBL
(mV
/V)
Gate Length (nm)
R=0nm R=15nm
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DoubleDouble--humps induced by cap transistorhumps induced by cap transistor
30x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3
Cap transistor induced lower Vt is very significant.It may attribute to thicker Tox, and more partial depleted.
0.3 0.6 0.9 1.2 1.5 1.80.0
1.0x10-6
2.0x10-6
3.0x10-6
4.0x10-6
dGm
/dV
g
Gate Voltage (V)
30x30nmLg=1μm, Tox=3nmNsub=5e18cm-3
0.0 0.5 1.0 1.5 2.01E-17
1E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Dra
in C
urre
nt (A
)
Gate Voltage (V)
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Volume Inversion [1]Volume Inversion [1]
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
Gate Gate Gate Gate
Oxide Oxide
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
N sub =10 15 cm -3 N sub =10 18 cm -3
T si T si
The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left).
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Volume Inversion [2]Volume Inversion [2]
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6 Nsub = 1015 cm-3
ϕs0, 10nm ϕs, 10nm ϕs0, 20nm ϕs, 20nm
Elec
tric
Pot
entia
l (V)
Gate Voltage (V)
For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region. The inversion charge (current) in the subthreshold region is proportional to Tsi.
0.0 0.2 0.4 0.6 0.8 1.01E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Tsi
Nsub = 1015 cm-3
Tsi = 10 nm Tsi = 20 nm
Inve
rsio
n ch
arge
she
et d
ensi
ty (C
/cm
2 )
Gate Voltage (V)
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QM Surface Potential CorrectionQM Surface Potential Correction
Undoped case
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II--V VerificationV Verification
Model can predict both subthreshold and strong inversion region well.
0.0 0.5 1.0 1.5 2.00.0
1.0x10-5
2.0x10-5
3.0x10-5
4.0x10-5
5.0x10-5
6.0x10-5
Dra
in C
urre
nt (A
/μm
)
Gate Voltage (V)
Symbols: 2D simulationLines: Model
Classic QM
0.5 1.0 1.5 2.01E-14
1E-12
1E-10
1E-8
1E-6
1E-4
Dra
in C
urre
nt (A
/μm
)
Gate Voltage (V)
Symbols: 2D simulationLines: Model
Classic QM
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S/D Series Resistance IssueS/D Series Resistance Issue
S/D series resistance will degrade the performance of thin body deviceCan be improved by the selective Si epitaxy raised S/D
J. Kedzierski et al., IEDM 2001
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 40
OutlineOutlineWhy FinFETWhy FinFET
FinFET processFinFET processUnique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, QM, , QM, volume inversionvolume inversion
IssuesIssues
Recent Recent FinFETFinFET DevelopDevelopTripleTriple--gate FinFET, Omega FET, gate FinFET, Omega FET, NanowireNanowire FinFETFinFET, , Independent gate, MultiIndependent gate, Multi--channel FinFET, Metalchannel FinFET, Metal--gate/highgate/high--K K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemoryDRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
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TripleTriple--Gate TransistorGate Transistor
B. Doyle et al., VLSI Tech. 2003
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OmegaOmega--Gate TransistorGate Transistor
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5nm 5nm NanowireNanowire FinFETFinFET
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Independent Gate FinFETIndependent Gate FinFET
Control the threshold voltageIdeal rectangular shape of Si fin
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Independent Gate FinFETIndependent Gate FinFET
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MultiMulti--Channel FinFETChannel FinFET
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Metal Gate FinFETMetal Gate FinFET
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MetalMetal--Gate FinFETGate FinFET
Vth adjustmentImprovement of IonK.G. Anil et al., VLSI Tech. 2005
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TiN/HfO2 FinFETTiN/HfO2 FinFET
Vth adjustmentReduce Gate leakage
N. Collaert et al., VLSI Tech. 2005
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Inverted T Channel (ITFET)Inverted T Channel (ITFET)
UTB + FinFETContinuous effective width
L. Mathew et al., IEDM 2005
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Strained FinFETStrained FinFET
25% drain current enhancement of PFET by introducing recessed Si0.8Ge0.2 S/DCompressive stress and raised S/D P. Verheyen et al., VLSI 2005
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Impact of GateImpact of Gate--Induced StrainInduced Strain
MuGFETs with TiSiN gate (+3GPa stress as deposited)
10-1594-1900-290-540Inverse PR Model
108594Experiment
(110) PMOS
(100) PMOS
(110) NMOS
(100) NMOSσzzσyyσxx
Mobility Enhancement [%]Stress [MPa]Eeff=0.4MV/cm
0
100
200
300
400
500
0 0.2 0.4 0.6 0.8
(100) metal(110) metal(100) poly ref(110) poly ref4%
59%
NMOS0
100
200
300
400
0 0.2 0.4 0.6 0.8
(100) metal(110) metal(100) poly ref(110) poly ref10%
8%PMOS
xy
z
xy
z
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Issue of Fin FormationIssue of Fin Formation
Neutral beam etching can accomplish damage (defect) free fabrication of high aspect ratio fin.Higher mobility is obtained in NB device due to atomically-flat surface
K. Endo et al., IEDM 2005
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Sidewall Spacer Transfer (SWT) ProcessSidewall Spacer Transfer (SWT) Process
Both gate and fin are formed by SWTSiN is selected as hard mask material for Si RIE on top of fin
Can be used as the CMP stopper during poly gate planarization (important for gate SWT)Suppress the agglomeration of Si fin during selective Si epiPrevent the leakage of the top cornerUsed as RIE stopper in the gate RIE process
A. Kaneko et al., IEDM 2005
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SWT ProcessSWT Process
The threshold voltage uniformities for SWT FinFETs of 15nm fin and 15nm gate length over the wafer is better than ArF and EB lithography
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Selective Gate Sidewall Spacer Formation Selective Gate Sidewall Spacer Formation
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FinFET on Bulk FinFET on Bulk SiSi SubstrateSubstrate
Bulk FinFET has the advantages of cheaper wafer cost, ease of combination with conventional bulk CMOS.
K. Okano et al., IEDM 2005
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Characteristics of Bulk FinFETCharacteristics of Bulk FinFET
Better subthreshold swingBetter short channel controlNegligible body effect
T. Park et al., VLSI 2003
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OutlineOutlineWhy FinFETWhy FinFET
FinFET processFinFET processUnique features of FinFETUnique features of FinFET
Mobility, workfunction engineering, corneMobility, workfunction engineering, corner effectr effect, QM, , QM, volume inversionvolume inversion
IssuesIssues
Recent Recent FinFETFinFET DevelopDevelopTripleTriple--gate FinFET, Omega FET, gate FinFET, Omega FET, NanowireNanowire FinFETFinFET, , Independent gate, MultiIndependent gate, Multi--channel FinFET, Metalchannel FinFET, Metal--gate/highgate/high--K K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
MemoryMemoryDRAM, SONOS, SRAMDRAM, SONOS, SRAM
ConclusionConclusion
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT
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NWL SchemeNWL Scheme
Lower VT (doping concentration) FinFET combined with NWL scheme can provide lower leakage and higher performanceNWL bias is critical to refresh fail bit
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SONOS Application of FinFETSONOS Application of FinFET
High Performance FinFET SONOS flash cells with gate length of 20nm is demonstrated.Program/erase window of 2V with high P/E speed (Tp=10ms, TE=1ms)
J. Hwang et al., TSMC 2005
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SONOS Application of FinFETSONOS Application of FinFET
Excellent endurance: up to 10K P/E cyclesGood retention: 1.5V after 10years retention time
J. Hwang et al., TSMC 2005
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FinFETs based 6FinFETs based 6--T SRAMsT SRAMs
Large fraction of the total chip area will be memory1
Leakage problem
Limited by impact of variations
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
VRVL
pulldown
access
load
FinFETs offer good control of short channel effects
1Source : Ranganathan, 2000
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Static Noise MarginStatic Noise Margin
• The minimum noise voltage at the storage node needed to flip the state
• Large SNM is desirable
Make pulldown device stronger relative to access transistor
Source: Bhavnagarwala, 2001
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SNM spread with variationsSNM spread with variationsThicker Si body better
Higher performance due to Rs limitations
Greater noise immunity (SNM)
Lesser spread in SNM
0
0.05
0.1
0.15
0.2
0.25
0.3
0.1 0.15 0.2 0.25SNM (V)
Prob
abili
ty
Tsi = 11nmTsi = 15nm
Taurus Device Simulation
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SNM spread with variationsSNM spread with variations
To improve SNMa) Wpulldown ↑ - 2 fins
b) Laccess ↑
c) μeff, pulldown>μeff, access
(100)pulldown device
(110) access device
0
0.1
0.2
0.3
0.1 0.15 0.2 0.25SNM (V)
Prob
abili
ty
(100)/1fin
(100 )/ 2 fins
(110) / 1finTSi = 15nm
Taurus Device Simulation
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FinFET Circuit design tradeoffsFinFET Circuit design tradeoffs
AdvantagesExcellent SCE control
Scalability
Double-gates are self-aligned
Insensitivity to channel doping
LimitationsGate materialContact/Series resistanceArea efficiency (fin pitch)Back gate routing
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ConclusionConclusion
Unique FinFET physics are introduced.Unique FinFET physics are introduced.
Recent developing effort on FinFET Recent developing effort on FinFET technology are discussedtechnology are discussed
TripleTriple--gate FinFET, Omega FET, gate FinFET, Omega FET, NanowireNanowire FinFETFinFET, , Independent gate, MultiIndependent gate, Multi--channel FinFET, Metalchannel FinFET, Metal--gate/highgate/high--K K FinFET, FinFET, SStrained FinFETtrained FinFET, Bulk FinFET, Bulk FinFET
FinFET based CMOS and memory cells are FinFET based CMOS and memory cells are very promising for subvery promising for sub--32 technology 32 technology node.node.
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Thank you very much Thank you very much for your attentionfor your attention