real intent, inc. 2008 (1) copyright © 2005 - real intent real intent, inc. envision suite of eda...
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Real Intent, Inc. 2008 (1)Copyright © 2005 - Real Intent
Real Intent, Inc.
EnVision EnVision
Suite of EDA SolutionsSuite of EDA Solutions
Real Intent, Inc. 2008 (2)Copyright © 2005 - Real Intent
Real Intent Corporate
Company founded 1999
World Wide Offices• Worldwide headquarters and R&D - Sunnyvale, CA• Development Centers - Austin,TX; Portland, OR; Boston, MA• CTC - Japanese Distributor• Black Forest - European Distributor• Maojet – Taiwanese Distributor
Real Intent, Inc. 2008 (4)Copyright © 2005 - Real Intent
What is EnVision?
A suite of advanced verification toolsA suite of advanced verification tools Designed to enhance existing verification flowsDesigned to enhance existing verification flows Easy to deploy through support of standardsEasy to deploy through support of standards Interoperate with major simulatorsInteroperate with major simulators
Based on proven formal technologyBased on proven formal technology Newly architected for performanceNewly architected for performance Patented formal algorithmsPatented formal algorithms
Increase design quality at lowest costIncrease design quality at lowest cost
Real Intent, Inc. 2008 (5)Copyright © 2005 - Real Intent
EnVision in your flowEnVision in your flow
Ascent™AutomaticFormal
Conquest™AdvancedVerification
Meridian CDC™Verification
PureTime™ExceptionVerification
Early Functional VerificationEarly Functional Verification Timing Closure VerificationTiming Closure Verification
EnVision TCVEnVision EFV
Real Intent, Inc. 2008 (6)Copyright © 2005 - Real Intent
Ascent Improving Early Design Quality
Ascent is a unique automatic Ascent is a unique automatic formal verification solutionformal verification solution
Quickly finds design errors without Quickly finds design errors without testbenchestestbenches
Completely automaticCompletely automatic Comprehensive formal checkingComprehensive formal checking Unique hierarchical reporting – low Unique hierarchical reporting – low
noisenoise Supports PSL / SVA constraintsSupports PSL / SVA constraints System Verilog SupportSystem Verilog Support
AUTOMATICAUTOMATICASSERTIONSASSERTIONS
Dead codeDead code
Uninitialized MemoryUninitialized Memory
Constant RTL expressionsConstant RTL expressions
Constant netsConstant nets
Constant state vector bitsConstant state vector bits
Unreachable FSM statesUnreachable FSM states
Single FSM deadlockSingle FSM deadlock
Pairwise FSM deadlockPairwise FSM deadlock
Bus contentionBus contention
Floating busesFloating buses
Full-case pragma violationsFull-case pragma violations
Parallel-case pragma Parallel-case pragma violationsviolations
X value propagationX value propagation
Array bounds violationsArray bounds violations
Real Intent, Inc. 2008 (7)Copyright © 2005 - Real Intent
ConquestStatic Formal ABV
Industry’s easiest formal solutionIndustry’s easiest formal solution Static formal ABV toolStatic formal ABV tool Replace and run from simulation Replace and run from simulation
scriptscript
Comprehensive language support Comprehensive language support Mixed Verilog, VHDL, SVMixed Verilog, VHDL, SV
Powerful debugPowerful debug Precise diagnosis info for failuresPrecise diagnosis info for failures Assertion trace visualizationAssertion trace visualization
RTL SourceRTL Source& Assertions& AssertionsRTL SourceRTL Source& Assertions& Assertions
Convergence Convergence Formal EngineFormal EngineConvergence Convergence Formal EngineFormal Engine
Extend Extend ProcessingProcessingExtend Extend
ProcessingProcessingResultResultResultResult
VerifiedVerifiedVerifiedVerified
ProofProof
IncompletIncompletee
ProofProof
CounterexampleCounterexample(Bug)(Bug)
Real Intent, Inc. 2008 (8)Copyright © 2005 - Real Intent
MeridianMulti-Strategy CDC Verification
Verifies clock domain crossing Verifies clock domain crossing behaviorbehavior
Fastest time to first resultFastest time to first result Ease and automation of setupEase and automation of setup
Completeness of analysis / templatesCompleteness of analysis / templates All synchronizer types & FIFOsAll synchronizer types & FIFOs Gray code analysisGray code analysis Both function and structureBoth function and structure
Best debug and reporting Best debug and reporting Quick isolation of root cause errorQuick isolation of root cause error Minimization of signoff burdenMinimization of signoff burden
Real Intent, Inc. 2008 (9)Copyright © 2005 - Real Intent
PureTimeTiming Exception Verification
Fast exception consistency analysis Fast exception consistency analysis Report important exception errorsReport important exception errors
Full sequential verificationFull sequential verification False & Multicycle path verificationFalse & Multicycle path verification Glitch and interaction awareGlitch and interaction aware
Easy setup, easy to runEasy setup, easy to run Design + SDC file + environment fileDesign + SDC file + environment file
Smart reportingSmart reporting VCD traces help debug failed VCD traces help debug failed
exceptionsexceptions