rcw@dei - reconf comp
TRANSCRIPT
POLITECNICO DI MILANO
Reconfigurable Reconfigurable Computing:Computing:
Systems historical Systems historical contextualizationcontextualization
Reasons behind FPGA(s)-based Reasons behind FPGA(s)-based solutionsolution
DRESD Team
PPartialartial DDynamic ynamic RReconfiguration econfiguration WWorkshoporkshop
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OutlineOutline
Basic Idea
A bird’s eye view on the Reconfigurable Computing
The roadmap
Reasons behind Xilinx
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What’s nextWhat’s next
Basic Idea
A bird’s eye view on the Reconfigurable Computing
The roadmap
Reasons behind Xilinx
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ReconfigurationReconfiguration
The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation.
Gerald Estrin, 1960
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Reconfigurable ComputingReconfigurable Computing
Reconfigurable computing is defined as the study of computation using reconfigurable devices
Christophe Bobda, 2007
ProcessorProcessor
FPGAFPGA
Full CustomFull Custom
Compilation time
Performance
low
high
low high
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What’s nextWhat’s next
Basic Idea
A bird’s eye view on the Reconfigurable Computing
The RC dawn and the FPGA revolutionSome !FPGA architectureThe accademic effortsChoose the optimal hardware platform for a given application
The roadmap
Reasons behind Xilinx
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The RC DawnThe RC Dawn
The Estrin Fix-Plus Machine, 1959The Ramming Machine, 1977Hartenstein’s XPuter, 1980
mid-1980s: the FPGA revolution/eraThe PAM Machine, SPLASH II, PRISM, Garp, DISC, DPGA
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Data Flow Machine (!FPGA)Data Flow Machine (!FPGA)
The Pact XPP DeviceThe NEC-DRP ArchitectureThe picoChip Reconfigurable Device
PicoChip solution:Array of heterogeneous processorsCommunication flexibility between processors achieved through reconfigurable technology
Array Processing Element
Switch Matrix
Inter-picoArray Interface
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The Academic EffortsThe Academic Efforts
The Reconfigurable Architecture Workstation (RAW) - MITThe Matrix Architecture - MITThe Reconfigurable Multimedia Array Coprocessor (REMARC) - StanfordMorphoSys - University of California, Irvine Chimaera – NorthwesternPipeRench - CMURaPiD - University of WashingtonGarp – UC BerkeleyBee2- UC Berkeley
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What are the drivers for this What are the drivers for this choice?choice?
Time: How long does it take to compute the answer?Area: How much silicon space is required to determined the answer?Costs: How much does it costs (performance, $)?Power: How much does it consume?
Processor generally fixes computing area. Problem evaluated over time through instructions.
FPGA can create flexible amount of computing area. Effectively, the configuration memory is the computing instruction.
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What’s nextWhat’s next
Basic Idea
A bird’s eye view on the Reconfigurable Computing
The roadmapThe 90% – 10% RuleProgrammable System on a ChipMulti-FPGA
Reasons behind Xilinx
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The 90% – 10% RuleThe 90% – 10% Rule
90% of the execution is spent in 10% of the codeInner loops in algorithmsComputational intense code
10% of the execution is spent in 90% of the codeExceptionsUser interaction
The 10% computational intense code has to be executed as hardware on reconfigurable devicesThe 90% exception code is run as executable files on processors
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Programmable System on a Programmable System on a ChipChip
No longer just a bunch of reconfigurable elements
DSPs, GPP, reconfigurable elements, etc. etc...
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Multi-FPGAMulti-FPGA
Heterogeneous Multi-FPGA system
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What’s nextWhat’s next
Basic Idea
A bird’s eye view on the Reconfigurable Computing
The roadmap
Reasons behind Xilinx
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Commercial FPGA CompaniesCommercial FPGA Companies
Lattice official webiste
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Reconfigurable Multi-FPGA Reconfigurable Multi-FPGA (taxonomy) (taxonomy)
and FPGA vendorsand FPGA vendors
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Reconfigurable SoC (taxonomy) Reconfigurable SoC (taxonomy) and FPGA vendorsand FPGA vendors
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Xilinx FPGA and Configuration Xilinx FPGA and Configuration MemoryMemory
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QuestionsQuestions