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Integrated Circuit Design 813 Stellenbosch University – Dept. E&E Engineering

2013

Course contents Lecture 1: GHz digital electronics: RSFQ logic family Introduction to fast digital logic families, superconductive (Josephson) logic circuits, the RSFQ logic family, JSIM simulations. Lecture 2: RSFQ basic cell libraries and simulation Effective simulation of digital circuits at electrical level: functionality, yield, noise, BER. RSFQ cells with Spice (JSIM) and including noise (JSIM_n), introduction to cell libraries of Stony Brook / Stellenbosch and FLUXONICS (IPHT Jena). Lecture 3: Circuit performance and optimisation Modelling circuits to calculate post-manufacture performance: margins and yield; as well as optimisation methods to improve circuit performance. Lecture 4: VLSI design flow and wafer manufacture Very Large Scale Integration circuit manufacturing. Lecture 5: IC layout: software, design rules, floor plans, methods and tricks Integrated circuit layout of RSFQ circuits for the Hypres and FLUXONICS processes, LASI as a free layout tool, design rule adherence (and where to “bend” the rules), layout tricks and the conversion of lumped-parameter circuit schematics into layouts. Quick rules for determining parameter values during layout. Lecture 6: Layout verification Reliable parameter calculation from layouts (resistance, capacitance, inductance, impedance) and extraction, InductEx as an extraction utility, identification of parasitics and layout-versus-schematic checking. Lecture 7: Packaging and testing: cryogenics included Die packaging, “design-for-test”, interface electronics, liquid helium testing, cryocoolers, thermal design, magnetic shielding. Note: The course notes are not exhaustive, as these are only used as a guideline during lectures.

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Lecture 1: GHz digital electronics: RSFQ logic family

1. Introduction The integrated circuit (IC) was first developed in 1958 by Jack Kilby at Texas Instruments to solve a growing problem: how to simplify the wiring between the increasing numbers of transistors in electronic circuits. The revolution in circuit manufacture this brought about continues to this day, and integrated circuits are now manufactured for digital logic circuits, memory, analogue (radio) circuits, mixed-signal circuits (for example GPS receivers with decoding logic integrated on the same die). In 1971, Intel unveiled the 4004 microprocessor with 2 300 transistors. Today, just more than 4 decades later, the microprocessors in Intel’s Core processors each have about 560 000 000 transistors. And yet the size of a die (the silicon chip in which transistors and interconnects are made) has remained roughly the same. This is made possible by ever-shrinking feature sizes. In 1971, the smallest features on the 4004 were around 10 microns, or 10 000 nanometres. Today, features for semiconductor circuits are down to 22 nanometres (and shrinking).

(a) (b)

Figure 1 (a) The Intel 4004 microchip and (b) a microphotograph of the 4004 die.

How do IC design engineers manage to keep track of 560 000 000 transistors? And make sure that interconnects are correctly wired, or that the circuit functionality is correct? The answer, of course, is structured design and the use of powerful software. Most integrated circuit design today (microprocessors, FPGAs, etc.) are done for CMOS (Complementary MOS) processes, but there are also bipolar transistor logic and other processes. Semiconductor integrated circuit design is a fascinating field, but specialised training is required to master circuit design and layout in any specific modern process.

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Figure 2: Intel quad-core Nehalem processor

In this course, we will study circuit design and layout in for a superconductive logic family. Although this is also highly specialised, the pace of development is much slower than in semiconductor IC design, feature size is still larger than 1 micron, and circuit complexity is typically below 1 000 gates. It is therefore not too difficult to get acquainted with the basic concepts of circuit design, layout and verification. Once this process is mastered, it is much easier to understand any other IC design process.

2. Superconductor electronics Over the last 20 years, superconducting digital electronics have made a big contribution to the field of applied superconductivity. Although there is currently more application for analogue or microwave superconducting electronics, especially in industry, the digital electronics hold sufficient promise to even feature in the International Semiconductor Technology Roadmap, where the contenders to CMOS electronics are evaluated on a regular basis. With respect to both power dissipation and speed, superconducting electronics outperform semiconductors. Superconducting digital circuits have been demonstrated to work at clock frequencies in excess of 40 GHz, and with improved technology this can be boosted to approximately 300 GHz for low-TC circuits [1]. Theoretically, high-TC circuits made with YBCO could operate even faster – at about 1 THz! A single-gate (T-flip-flop) superconductive circuit has already been demonstrated to operate at 770 GHz [2]! Superconducting digital electronics can be implemented using only inductive coupling and the critical magnetic field of superconductors to induce normal state switching. The

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device used for such electronics is the cryotron, but its switching speed is limited to the 100 Megahertz range, and it has been abandoned a long time ago. Today, all superconducting digital electronic circuits use Josephson junctions as the switching elements. There are two distinct approaches to superconducting digital electronics, namely voltage-state logic (such as COSL [3]), and flux-state (or single-flux-quantum) logic (such as RSFQ [1]). The former represents binary information in the same way that semiconductor electronics do (with two voltage levels), while in the latter binary information is represented by single-flux-quantum pulses. Currently most superconducting digital electronics are manufactured in LTS Nb-based circuits (4 Kelvin), but some HTS circuits (40 Kelvin) have been demonstrated to work too – although never as complex systems, but rather on gate level [4], [5], [6]. In the short term, LTS Nb-circuits will continue to dominate the field, but the added speed advantage of HTS circuits, as well as the reduced demands on cryogenic cooling, keeps interest in HTS RSFQ alive. (There is, however, the problem that HTS circuits suffer from thermal noise degradation). The ultimate goal with superconducting digital electronics has long been suggested as supercomputing. However, massively parallel semiconductor computers can still match anything that experimental superconductor systems can achieve, with the exception that superconductive supercomputers would use much less switching energy (and thus much less power from the grid [7]). Recently, energy efficiency improvements to the RSFQ logic family have been proposed and demonstrated [8], [9], [10], [11], up to the point where SFQ circuits are biased with zero static power dissipation [12], and dissipate only dynamic power (at less than 1 aJ/bit) [13]. In the long run, this efficiency might mean the difference between powering a supercomputer with a nuclear power plant or a wind turbine… In the short term, however, superconductor systems will most likely break into the areas where extreme speed is the primary advantage, such as special-purpose signal processors, analogue-to-digital converters, digital filters, counters, switching arrays, software-defined radio systems, random number generators and spread-spectrum systems, and specialised codebreaking.

3. Brief theory of superconductor electronics from an engineering point of view

Although the Josephson junction is a macroscopic quantum device, we can consider it (the same as for the transistor) as circuit element governed by simplified equations. The Josephson junction is a two-terminal device, and the circuit symbol is shown in Fig. 3.

Figure 3: Josephson junction circuit symbol.

You will be shown the Josephson junction’s I-V characteristics in class. For a basic start, consider the junction as a nonlinear device with one parameter: Critical current

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(IC). Starting from zero current, with the junction in the superconductive state, if a current is applied through the junction it will flow without any voltage developing across the junction. When current through the junction exceeds IC, the junction switches to the normal state, and acts (mostly) as a resistor. The current through the junction now produces an average voltage that is not zero. So how do we use this 2-terminal device to make digital circuits? There are several ways, but the most popular and successful is RSFQ (Rapid Single Flux Quantum). The following concepts will be discussed during the lecture:

• Junction damping (with resistors) • Junction hysteresis • Junction biasing • Junction switching • Fluxons and the relation to currents in RSFQ. • Pulse logic vs voltage level logic

4. Rapid Single-Flux Quantum Logic The RSFQ logic family is constructed with damped Josephson junctions, inductors (superconducting) and current sources. Almost all standard logic cells, and a few RSFQ-specific cells can be constructed, and with these we can build almost any combinational or sequential logic circuits. In this section, we present a quick overview to help you with understanding RSFQ. The graphics in this section, and most of the text, were published by the RSFQ Design Group at Ilmenau University of Technology (Germany) (http://www.tu-ilmenau.de/en/department-of-advanced-electromagnetics/research/superconductive-high-speed-electronics/rsfq-cell/).

Fig. 4: RSFQ circuit components

RSFQ logic relies on the representation of data through the absence or presence of single flux quanta (a flux quantum Φ0 = h/2e) generated by Josephson junctions and inductances. In Fig. 4, single flux quanta (SFQ) are represented by crosses in circles (showing flux penetration into the plane of the figure). RSFQ circuits are composed of

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three elements: inductance L of interconnects, critical current of Josephson junctions, and bias current Ib. These elements allow us to form three basic building blocks:

1. Transfer. These blocks allow bidirectional transfer of SFQ pulses. Pulse / data propagation can either be viewed as a switching current and accompanying voltage propagating from one junction to the next, or as a flux quantum threading one transfer loop and then the next as Josephson junctions switch. Transfer blocks have small inductances.

2. Storage. With larger loop inductances, the circulating current in a loop that encloses the inductance is too small to switch the second junction. Thus, the circulating current remains in the loop and information is stored. This is used to build bistable cells.

3. The decision element. A decision element uses two Josephson junctions to form a two-junction comparator. Typically, with sufficient input current, one of the two junctions in a decision element will switch, with the bias current through the two junctions determining which junction switches.

The operation of the following basic cells will be demonstrated in the lecture: • The JTL • The DFF • The DCSFQ

5. The Likharev paper In 1991, Konstantin K. Likharev and Vasili K. Semenov published their paper [1] on RSFQ electronics in the first issue of the IEEE Transactions on Applied Superconductivity. Although it has aged over the last 2 decades, and much work has been done to expand the family and change some of the fundamental circuits or ideas, this article remains the basis for almost all further RSFQ research. You are required to read the paper before the next lecture, as it introduces the basic logic cells and concepts such as the clocking of pulse logic circuits.

6. Simulation software Integrated circuit design for superconductive circuits follows much the same approach as that of semiconductor circuits. Before we can proceed to physical circuit implementation (layout and verification of actual cells as they will appear on masks and eventually wafers), we need to set up tools (software) with which to capture circuit schematics and simulate circuit behaviour (electrical and functional). There are many expensive but powerful software suites for semiconductor circuit design (from Cadence, Synopsys, Mentor Graphics and others), and some freeware utilities that allow you to do basic simulations and designs. In superconductive electronics design there are toolsets for Cadence (but Cadence requires a very expensive license), and the powerful but sometimes limited software XIC (including the simulation engine WRSpice) from Whiteley Research. Mostly, however, superconductive circuit designers use free software. For this course, assemble your own free software suite to include at least the following modules:

• Jsim_n (a phase-based simulation engine that is much faster than Spice for superconductive circuits, and has Josephson junction support built in)

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• gEDA (a free schematic capture tool that does not look very smart, but works very well.)

7. Weekly task It is essential that you get a basic grasp on RSFQ circuit operation (gate level only) as soon as possible. The rest of this course will be structured along the design flow process, starting with electrical simulations in the next lecture. This determines the focus of this week’s task. For your first task, you will learn to model Josephson junctions in Spice, and observe junction switching during simulation.

1. Install gEDA with from our in-house repository (we made some changes to allow it junction and JSIM support).

2. In gEDA, build the JTL using the built-in model for a Josephson junction, convert it to a netlist, and simulate with JSIM_n. Feed the JTL with some simulated SFQ pulses, and terminate the output in a 2 Ohm resistor.

3. Plot the results of the simulation. Matlab works well for this (Stellenbosch University has licenses).

Run transient simulations with 0.5 ps data storage resolution and 0.25 ps maximum simulation step size. Keep total simulated time spans under 1 ns. Also collect all the papers referenced in these notes from the Unversity’s electronic library. Read the Likharev paper [1] in detail, and browse through the rest before the next lecture. Finally, compile a research report on the design flow for semiconductor circuits (from schematic capture to final tape-out) with the toolsets of Cadence, Synopsys or Mentor Graphics. You may use the internet extensively, but should pick out only hard facts. This task is to be done as a group (only submit one well-polished report). Hand in your circuit files and simulation results at the start of the next lecture. For the report, you have two weeks.

8. References [1] K. K. Likharev and V. K. Semenov, “RSFQ logic/memory family: A new

Josepshon-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Transactions on Applied Superconductivity, vol. 1, pp. 3-28, Mar. 1991.

[2] W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens and K. K. Likharev, “Rapid single flux quantum T-flip flop operating up to 770 GHz,” IEEE Transactions on Applied Superconductivity, vol. 9, pp. 3212-3215, Jun. 1999.

[3] W. J. Perold, M. Jeffery, Z. Wang and T. Van Duzer, “Complementary output switching logic – a new superconducting voltage-state logic family,” IEEE Transactions on Applied Superconductivity, vol. 6, no. 3, pp. 125-131, Sep. 1996.

[4] D. Cassel, R. Dittmann, B. Kuhlmann, M. Siegel, T. Ortlepp, H. Toepfer and F. H. Uhlmann, “HTS basic RSFQ cells for an optimal bit-error rate,” Superconductor Science and Technology, vol. 15, pp. 483-487, 2002.

[5] H. Toepfer, T. Ortlepp, H. F. Uhlmann, D. Cassel and M. Siegel, “Design of HTS RSFQ circuits,” Physica C, vol. 392-396, pp. 1420-1425, Oct. 2003.

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[6] T. Wolf, N. Bergeal, J. Lesueur, C. J. Fourie, G. Faini, C. Ulysse and P. Febvre, “YBCO Josephson junctions and strip-lines for RSFQ circuits made by ion irradiation,” IEEE Transactions on Applied Superconductivity, vol. 23, 2013.

[7] D. S. Holmes, A. L. Ripple and M. A. Manheimer, “Energy-efficient superconducting computing – power budgets and requirements,” IEEE Transactions on Applied Superconductivity, vol. 23, 2013.

[8] N. Yoshikawa and Y. Kato, “Reduction of power consumption of RSFQ circuits by inductance-load biasing,” Superconductor Science and Technology, vol. 12, pp. 918-920, 1999.

[9] Y. Yamanashi, T. Nishigai and N. Yoshikawa, “Study of LR-loading technique for low-power Single Flux Quantum circuits,” IEEE Transactions on Applied Superconductivity, vol. 17, no. 2, pp. 150-153, 2007.

[10] T. Ortlepp, O. Wetzstein, S. Engert, J. Kunert and H. Toepfer, “Reduced power consumption in superconducting electronics,” IEEE Transactions on Applied Superconductivity, vol. 21, pp. 770-775, 2011.

[11] O. A. Mukhanov, “Energy-efficient Single Flux Quantum technology,” IEEE Transactions on Applied Superconductivity, vol. 21, no. 3, pp. 760-769, June 2011.

[12] D. E. Kirichenko, S. Sarwana and A. F. Kirichenko, “Zero static power dissipation biasing of RSFQ circuits,” IEEE Transactions on Applied Superconductivity, vol. 21, no. 3, pp. 776-779, June 2011.

[13] M. H. Volkmann, A. Sahu, C. J. Fourie and O. A. Mukhanov, “Implementation of energy efficient Single Flux Quantum digital circuits with sub-aJ/bit operation,” Superconductor Science and Technology, vol. 26, 015002, 2013.

C. J. Fourie – February 2013