quadratic i-v and rc delay...
TRANSCRIPT
2EE 215B
Overview
• Reading– Rabaey 5.4, 5.5– W&H 4.2, 4.4, 5.4 (Calibrating Models)
• Overview– This lecture will review the RC model, and explain why it
works, and were it fails. We start with the classical i-V derivation as a foundation for the discussion on the effective resistance. Luckily for us, the simple first moment model of delay works for most CMOS circuits as long as you are interested in the delay at the end of the RC network.
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Review: Classical Quadratic Model
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MOS i-V Curves
• To understand the transistor’s effective resistance and how it is sensitive to various parameters and inputs, we need to have a more detailed model of the relation between current and terminal voltages.
• This is usually done by making a few assumptions:– Main assumption is the current is controlled by the mobile charge in
the channel. This is a very good approximation– Next is the gradual channel assumption – the vertical field sets
channel charge, so we can approximate the charge by the voltage difference between the gate and the channel
– There are non-mobile charge present when the mobile charge channel forms. The gate voltage needed to image this charge is called the threshold voltage, Vth
– Using these approximations means that the mobile charge, Qn = Cox (Vg -Vc -Vth)
– The last assumption, and the worst (we will fix it up soon) is that the carrier velocity, ν = µE – velocity is proportional to lateral field
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Review: MOS I-V Curves
• How to find the current?– Know Vg, Vs, Vd, Vth, Cox
– Need to find Vc(y) the channel voltage as a function of y– d/dy (Vc(y)) is E; the field in the channel is due to change in
voltage
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Review: Equations
• It is difficult to directly find out Vc(y)
• But we do know at any position ‘y’– Qn(y) = Cox(Vg-Vc(y)-Vth)– i = Qn(y)∗ν = Cox(Vg-Vc(y)-Vth)∗µE– E =dVc/dy
• Further we know that the current through each segment of the channel must be the same.– Otherwise charge would be building up in the channel, and
means voltages would need to change• Since current is constant, we can relate dVc/dt to Vc, and form
an equation we can easily integrate.
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Review: MOS i-V Curves
• Qn(y) = mobile charge/surface area induced in channel• Vc(y) = channel voltage at y
• Using our assumptions( )
( )
( )( )
dsds
thsgoxds
cthcgoxds
cthcgoxds
cthcgoxds
thcgoxn
V2
VVVVCLW i
dVVVVCWdyidy
dVVVVC Wi
dydVE but E;VVVWCWQi
VVVCQ
⎟⎠⎞⎜
⎝⎛ −−−=
−−=
−−=
=−−==
−−−=
∫ ∫µ
µ
µ
µν
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Review: Plot of i-V Curves
• This is wrong!!
• Current does not decrease with increasing voltage
• 0.35um
Now the simple model for drain current is to write the drain current as a function of the channel charge and solve the resulting set of equations which gives:
i ds Vg Vd, Vs, WL
µ e C ox. Vg VthVs Vd
2. Vd Vs. Vd 0 Vdd
N, Vdd..
0 0.5 1 1.5 2 2.5 3 3.50
2 .10 4
4 .10 4
6 .10 4
8 .10 4
0.001
i ds Vdd V d, 0,
i ds 2.5 V d, 0,
i ds 1.5 V d, 0,
V d
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Review: Why Does the Current Bend Down?
• When Vg-Vth-Vd is negative, the sign of the carriers change?!– Because the equation has negative carriers– This implies negative resistance (this is wrong)
• What really happens when channel charge gets small– Gradual channel approximation breaks down– Carrier density is not set by gate– That is when our equations breakdown
• Assume voltage across channel is just until this point occurs– Assume that the maximum voltage at end of the channel
min(Vd, Vg-Vth)
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Review: Equation w/ Saturation
• If we clamp the equation we get:
Vc Vg Vd, min Vd Vg Vth
0 0.5 1 1.5 2 2.5 3 3.50
2 .10 4
4 .10 4
6 .10 4
8 .10 4
0.001
i ds Vdd V c Vdd V d,, 0,
i ds 2.5 V c 2.5 V d,, 0,
i ds 1.5 V c 1.5 V d,, 0,
V d
( )
**ds
ds ox g s th ds
*ds ds g s th
VWi µC V V V VL 2
V min V ,V V V
⎛ ⎞= − − −⎜ ⎟
⎝ ⎠= − −
11
RC Delay Model
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Delay In Transistor Networks
• As we have seen transistors are not linear devices– So an interesting question is why does the RC model work– Answer: quadratic transistors are ‘nice’ non-linear devices
• First let’s look at delay in a single transistor capacitor circuit– For all non-linear differential equations, it is useful to put the
equation into what is called normalized form. • This is where you make all the variable dimensionless, and pull
all the dimensions and other constant factors into some normalization constants.
– These normalization constants often give you most of the information you need, and are often simpler than solving the actual differential equation
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Synopsis of RC Delay Models
• Circuit delay– Is approximately the normalization
constant for time in the differential equation• Effective resistance, Reff
– Is proportional to ΔVsw / ids_eff
– Determined normally from simulation data• Its value depends on the operating conditions
– Lower supply voltage – larger Reff
– Higher temperature -- lower mobility –larger Reff
idsV
ds
ds_eff
dVi (V)=Cdt
C VtiΔΔ ≈
14
Review: Transistor as a Switched Resistor
VGS ≥ VT
S DRon
( )
( )
eff mid 0
DD DD DDeff
2DSATN DSATNeff ox DD th
1R = R +R2
V V 2 V1R = +W2 I I u C V -V2L
⎛ ⎞∝⎜ ⎟
⎝ ⎠
ID
VDS
VDDVDD /2
VGS = VDD
Rmid
R0
15
Aside: Reff Depends on Operating Condition
0 0.5 1 1.5 2 2.50
1
2
4
5
6x 10-4
VGS (V)
I D(A)
3
( ) ( )DD DD
effDS GS DD DS GS DD
V V 21R = × +2 I V =V I V =V 2
⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠
16
Transistor as a Switched Current
( ) ( )( )
eff
eff max mid ds gs dd ds dd
2dd dd th eff eff ox dd th dsat
delay=C V/I1 3I I I I V V ;V V42
W3 V >V -V ; I =u C V -V I4 2L
Δ
≈ + ≈ = =
=
• Charging of the capacitance
• Approximate average current as Ids at Vds=(3/4)Vdd
ID
VDS
VDDVDD /2
VGS = VDDImax
Imid
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Normalized Form
• Circuit
• Equation
• V* ranges from 0 to 1, ids*() ranges from 0 to 1
– MOS transistors are ‘nice’ since ids* for any series/parallel combination is the same function. They combine like linear resistors – normalization constants combine like they would with linear resistors
* ** * dsmax
ds dd dsmax ds * *ddds
idV dV dVC i (V); CV i i (V ); dtdt dt CVi (V )
= = =
idsV
i dsmaxW2 L.
µ e Cox. Vdd Vth2.
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Aside: Quadratic Transistors
• The transistors combine this way because you can represent– ids
* = (f(Vd) - f(Vs))
• Now think about using a transformed voltage U=f(V)– System is linear in U– Match moments of U
• Result is exactly the same formulation as for linear resistors• This is the rational behind RC models for transistors
– Actually the model came first, then we figured out why it worked
⎥⎦
⎤⎢⎣
⎡−
=−−=thdd
X*X
2*XX VV
V ,1minV ;)V1(1)f(V
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Aside: Shape of Waveform
• We don’t need to do this, but in case you are interested– The waveform is a ramp when current is constant
• In linear region:
• Note that the difference with a linear resistor is small
**
*
2)tanh(1V ;dt)V(11
dV **D
*2*
D
*D
tt
t
eeet
−+
−
+=−==
−−
0
0.2
0.4
0.6
0.8
1
0 1 2 3
ResistorMOS
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Application of RC Model
• Logic gates and networks can be modeled as a linear RC network to estimate delay
• In general these models have distributed resistor, capacitor networks– Often only the parasitic capacitors are distributed– Sometimes need to solve the full problem
• An interesting example is the pass-transistor logic– Multiple Rs and Cs.
M2
M1
M3 C2
C1
M3M1
C1 C3C2
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Measuring Delay in RC Circuits
• If circuit has a dominant R or C– Estimate delay by measuring delay of RC network
• For an RC circuit– With a step input
• Output V(t) = Vdd (1- e-t/τ)– τ = RC; Delay to 50% is RC ln(2) = .7 RC– (From now on, voltage is normalized to be in range 0-1)
R
C
sRC11H(s)
+=
[ ]t/RCe1VddV(t) −−=
Vout
00.10.20.30.40.50.60.70.80.91
0 0.5 1 1.5 2 2.5
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Delays in More General RC Networks
• For a more complex network– Answer gets more complex
• Can factor:
• There must be a simpler model
R1
C1 C2
R2
22112
22111 CRCRs))CR(RCs(R11H(s)
++++=
212
2
121
1
s11
s11H(s)
ττττ
ττττ
+−+
+−=
( )[ ] 1
2*
1
2*2**
**22111
1,2 CCC ;
RRR ;
CR11
C4R112
)CR(RCRτ ==⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
++−±++=
This doesn’t seem right. After all, this is a simplified model of the real circuit. It must be easy to calculate to be useful
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Single Pole Model
• For most RC networks– Output is dominated by
a single pole• Look at the previous
example. Even if the RC sections are the same, the two poles are separated -- one time constant is much lower than the other
• τ1 =5.2RC; τ2=.8RCτ1 >> τ2
– Exponential is not a bad model (single pole). Even when τ1 = τ2 less than 15% t error 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.5 1 1.5 2 2.5
Modeltau2 = 0.1 tau1tau2 = 0.25 tau1Worst-case
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Elmore Delay Model
• Elmore 1948 uses a first-moment model.– First moment of the impulse response, vout’(t) (rising transition)
– Works well with symmetric impulse response.• Transition of a gate.• Non-linearity of the transistors.• Multi-pole systems.
– Works for monotonic waveforms.
∫∞
=0
' )( dtttvt outelmore
Vout’(t)
ttelm
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Slight Variation of Elmore Delay
• A reformulation of Elmore Delay is
– V(t) is a normalized output voltage– Taylor approximates to the same as Elmore formula.– Used to formulate delay of RC chains.– Aside: has been extended to accommodate non-monotonic
waveforms.• RC (Elmore delay) is then the equivalent area or time constant.
– Reasonable approximation for a long chain of RC.
∫∞
−=0
)(1 dttvtdelay
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First-Order Moment Model
• To approximate the output delay– Need to find the exponential that ‘best’ matches output– Match the area under the two waveforms (first moment)
• The area under an exponential is simple– It is the time-constant - τ
ττ =∫∞
−
0
t/ dte
00.10.20.30.40.50.60.70.80.91
0 0.5 1 1.5 2 2.5 3 3.5
00.10.20.30.40.50.60.70.80.91
0 0.5 1 1.5 2 2.5 3 3.5
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RC Network Output
• For a general RC network finding the area is easy!– Add the voltage drop caused from each capacitor current
– Rki = voltage induced on output i, by the current injected at location k divided by that current. R32 = R1, R22 = R1+R2
– Don’t know what dVk/dt is, but know its integral is ΔV
∑=k
kkkii dtdVCRV
∑∑∫ =Δ=∞
kkki
kkkki
0i CRVCRV
DC
R1
R3
R2C3
C2C1
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RC Delay in Series Transistor Stacks
Lambda = 0.2µ
Rstage = 2/W 13K Cstage = (0.4fF + 0.4fF)W = 0.8WfF (middle)Ctop = 0.4WfF
• So delay is:
RCstage + 2RCstage + 3RCstage + 4R(Ctop+Cload)
• In general for n stages:
n(n-1)/2 RCstage+ nR(Cload+Ctop)=0.02ns * n(n-1)/2 + 0.01ns *n/W +26K *Cload
10
6
W
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Delay Estimate
• In summary, the estimate is easy to find:1. Find every capacitor in the circuit that changes value.2. Find the voltage that a current injected from this capacitor will
produce at the output, and define the effective resistance, Rki, equal to this voltage/current.
3. Sum Ck*Rki, over all nodes k that change value. This sum is an estimate of the time constant
• Can apply this to distributed elements like wires too– Look at a small segment of the wire of length dL– As dL gets smaller, the sum over all caps becomes an integral.
• Equals Rtotal Ctotal /2• Π model accounts for the C/2
0 1 2 3 4 50
0.2
0.4
0.6
0.8
1
V t( )
V e t( )
t
0
L totalL
Rmm
L.Cmm. d
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Response of Distributed RC Wire
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
vo
lta
ge
(V
)
x= L /10
x = L/4
x = L/2
x= L
RCtDLY 38.0=Very similar to Elmore Delay of Π model, except for 0.38 (instead of 0.5)
Step response
Step input
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Error in RC Delay Estimation
– For a lump RC circuit• Step inputs: the approximation has positive skew.• Tdelay = ln(2)RC (Elmore overestimates by 1.4x)
– For a distributed RC circuit• Step input: Tdelay = 0.38RC
– Can potentially compensate for the error by normalizing• Rw-effective = ln(2)*Rw-actual
RDRVP
out
V’(t)
ttelm
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Analysis of Error in Wire RC Delay
• The problem is that the Rw-effective is a function of the input slope.
• Elmore approximation is more accurate if the input rise time is long compared to the RC delay.– Ratio approaches 1.
• What value to use?– Rw-effective = Rw-actual
overestimates long wires.– Rw-effective = ln(2)*Rw-actual
underestimates shorter wires.
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Error in Wire RC Delay
• Data from a 0.35µm microprocessor using Rw-effective=Rw-actual(Pileggi)
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Moment Analysis
• Works reasonably well in most cases (even with the ln(2) error)– Output at the end of a long line is almost always single pole– Even when have two poles closely spaced, it is decent.
• Works poorly where there is a pole-zero pair– Output is the sum of two exponentials
• One is slow with low amplitude• One is fast with full amplitude
– In example shown on right• Decays with R1C1 to R1/(R1+Rlarge)• Then decays with time constant Clarge(Rlarge +R1)
• This rarely happens at the output of a network– More common in the middle of network– Can do bounds, and 2nd order model,
• But you don’t really need to hear about it.
DC
R1 Rlarge
ClargeC1
Vout
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0 1 2 3 4 50
0.2
0.4
0.6
0.8
1
V t( )
V e t( )
t
A Bad Output – A Pole-Zero Pair
• This plot show a ‘bad’ output– Tail is 10 times slower– And 0.3 full swing
• Circuit is shown below• Moments are not the best
model for this circuit
1 2
0.1 0.3
36
Model Calibration
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Transistor RC Models
• While simple, these models are very powerful– Mostly it derives delay relations of the correct form
• Shows the critical parameter for speed is– Cin * Rdrive of a gate– The smaller this product the faster the gate
• But you need to calibrate the models before you use them– Need to find the correspondence between transistor size and
resistance, and gate and junction capacitance
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Calibrating Transistor RC Models
• MOS devices are not linear resistors• MOS capacitances are not linear either• So what value should you use?
– Critical question is you want your model to be useful
• Calibration simulations– Someone does a bunch of simulations– First have inverters/gates driving linear capacitor
• Match delay to RC model, use delay to find R• This accounts for the ln(2) problem for Gates.
– Next have inverters driving other inverters, diffusion, etc• Since know R, find the effective C that matches the delay
• Use these calibrated values in your models
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Model Calibration
• For capacitance – Adjust CLOAD to match delay– Make the fanout of the inverters 4, since quite typical for
well-optimized circuits.
• For resistance– Set the CLOAD the same as FO4 case and adjust R
Cload
R CloadCload
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Calibrating Diffusion Capacitance
• For self-loading, match delay to A and B.– Introduce extra S/D parasitic.– Specify AD/PD for the area and perimeter area.
• What is the capacitance actually measured?– Overlap + Area + Perimeter– Isolate each one (set AD/PD/W to 0)– Useful for general number by using realistic number for all 3
• To get a fF/µm number.
A
B
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Calibration Issues
• Resistance depends on gate overdrive, so need the correct VDD
– This might not be VDD nominal, since you might want some margins. Generally measure delay at worst-case operating voltage, which is VDD – 10 (or 15)%
• Capacitance depends on the voltage swing• Resistance depends on input rise-time.
– Need to measure resistance with the correct input slope• First inverter in the calibration setups is to make the input slope
correct• Resistance depends on velocity saturation.
– Cannot compose the Rdrive from series summation– Need to measure the resistance for different logic gates
• Different inputs, rising/falling etc.
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Logical Effort Calibration
• The values for g and p can be extracted from simulation.– Because, d = g*h+p– Simulating the delay of the gate for different loads.
• Drive itself with different multiplication factor.– Extract τo using inverter with no self-loading.
• Need to vary the inputs (and rise/fall) for different g and p.
Delay/τo
Cload/Cin
GateSlope is g
Intercept is p Inverter
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Summary and Limitations of RC Transistor Models
• Arbitrary RC networks has some limitations– ln(2) problem– Tapping an output from the middle of a network
• You have to use models calibrated for your operating conditions– You need to operate over some range of Temp and Voltages– A set of RC parameters
• Effective R’s is a function of i-V characteristics.– “Reff” networks does not actually have benign function.– Hence LE simulation differs from RC calculation.
• Input-slope dependence