Application Note 195

PULSE GENERATOR

TECHNIQUES INCMOS APPLICATIONS

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INTRODUCTION

CMOS TEST REQUIREMENTS

FUNCTIONALTESTING

PARAMETRIC TESTING

PARAMETRIC TEST SET

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PULSE GENERATORTECHNIQUES IN

CMOS APPLICATIONS

INTRODUCTIONSince ils introduction at thé end of thé 1960's, MOSintegrated circuit technology has penetrated a widevariety of application areas. One variant of MOStechnology, called CMOS (or COS/MOS) logic, is rapidlygaining in popularity and has created a need for testequipment with new capabilitîes. A spécifie need is forstimulus instrumentation with which CMOS devices canbe exercised in order to evaluate their performance. Thisapplication note will describe new puise generatortechniques for making thé necessary measurements, aswell as provide an explanation of thé tests themselvesand a brief introduction to CMOS technology.

WhatisMOS?The initiais MOS (Métal Oxide Semiconductor) todaydescribe any enhancement mode (a device which isnormally off with no bias and has to be turned on orenhanced to cause current flow through it), insulatedgâte, field effect transiter. Because of its features (someunique) such as low power dissipation and low packingdensity, MOS is one of thé major technologies for LargeScale Intégration (LSI) along with ECL and TTL. Thedifférent types of MOS devices are described as follows.

PMOS and NMOS devicesAs mentioned above, thé basis for ail MOS devices is théenhancement mode Field Effect Transistor. FET deviceswere originally fabricated using an N-type substrate withtwo diffused régions of P-type material, thé source anddrain. A metallized layer separated from thé substrate by

a diffused layer of silicon dioxide formed thé gâte orcontrol élément. Figure 1 shows a cross-section of théP-channel device structure and its schematic symbol.

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Figure 1. P-Channel Transistor (PMOS)

A voltage applied to thé gâte establishes a path, théchannel, for hole conduction between thé source anddrain. Similarly, using a P-type substrate with N-typesource and drain results in an NMOS transistor utilizingélectron conduction after gâte turn-on. Figure 2 is across-section of an N-channel élément and thé schematicsymbol. Either of thèse FET devices can be integrated toform logic circuitry.

Figure 2. N-Channel Transistor (NMOS)

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CMOSdevices

With thé development of CMOS (or ComplementaryMOS), a new and very advantageous form of MOSbecame available to thé system designer. The benef its ofCMOS logic are many: low power dissipation at médiumspeeds, wide range of power supply voltages (3—16V),high noise immunity, high packing density, and highfan-out capability. Thèse advantages are today offered inIC's encompassing a wide variety of basic and complexlogic functions. They offer thé designer complète Systemdesign freedom.

state current is drawn. Power dissipation in thé CMOScircuit occurs only during thé brief transition periodbetween logic states.

Careful device design for rapid turn-on and turn-offresults in a power dissipation as low as 2 nW per gâte.The high noise immunity inhérent in CMOS logic isalsoa direct resuit of thé complementary configurationbecause two separate thresholds must be crossed. Thethreshold région also varies directly with thé powersupply voltage and has its center located at typically45% of thé supply voltage.

This third type of MOS intégrâtes both N-channel andP-channel transistors in thé same logic circuits. As shownin Figure 3 a complementary inverter may be formed byapplying thé input signal to thé gâtes of two oppositepolarity transistors.

The operating speed of CMOS circuits is at présentlimited to about 15 MHz. This is due to thé relativelyhigh parasitic capacitance of thé silicon substrate. CMOScircuits using a sapphire substrate (called SOS/CMOSlogic) are now in development which hâve substantiallyhigher operating speeds because of reduced parasiticcapacitances.

In this circuit a low input signal means thé N-channeltransistor (Q1) is OFF and thé P-channel device is ON.The output is shorted to thé positive supply, butvirtually no load current is drawn if a similar highimpédance MOS gâte input is used as thé load. When théinput signal goes high, Q1 is turned ON and Q2 is turnedOFF. The output is pulled to ground, but no steady-

The three major advantages made available by CMOStechnology can be summarized as follows:

very low power dissipation

wide power supply voltage operating range

- high noise immunity.

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CMOS TEST REQUIREMENTS

Test requirements for CMOS digital devices are of twodifférent types: functional tests and parametric tests.

Functional testing is performed to détermine if théCMOS device or circuit is working on a digital (i.e., Vsand 0/s) basis. Does thé device correctly process digital in-put signais to produce ils expected output signais? Does itperform according to its truthtable? Functional testingis, for example, a design engineer's first concern whenturning-on and troubleshooting a new circuit design.

Parametric testing is concerned with measuring deviceperformance in terms of nanoseconds, volts, andmilliamperes. Data sheet specified parameters such aspropagation delays, setup times, leakage current, andoutput voltages are typical examples of device attributesthat must be measured and compared against standardvalues. Such testing is typically performed by IC design-ers and manufacturer and is often also required inincoming inspection of purchased devices.

CMOS adds an additional level of complexity toparametric testing. As thé power supply voltage is variedthrough its allowable 3 - 16 volt range, device parame-ters also vary considerably. Figure 4 shows two représen-tative characteristic curves which indicate thé variationsin device performance which can typically be expected.The resuit is that it is often necessary to performparametric tests at several différent power supplysettings or even over a range of voltages.

CMOS device parametersThe following are a sélection of thé most importantparameters that need to be measured when performingparametric tests on CMOS devices.

Input VoltageThe CMOS input structure requires that thé signal inputvoltage (V } be limited to values between thé upper andlower power supply voltages, respectively VDD and Vss

{or system common}. If thé signal is ever greatcr thanVQQ, thé device input protection diodes become forwardbiased and thé resulting high input current destroysthé IC.

Operating SpeedThe operating speed of a logic System dépends uponsignal propagation delays and output rise and fall times.In thé CMOS logic family thèse parameters are functionsof output load capacitance, operating voltage, and thédevice température.

Propagation DelaysPropagation delay pairs, tp,H and tpHL are usuallyspecified on ail data sheets. tp ,H is thé time required fora signal to propagate through thé device and raise théoutput node with its associated capacitance from a lowto high level. tpH| is thé delay through thé same pathbut for an output change of logic high to low. Fornon-synchronous circuits, thé delay is measured fromthé input signal edge to thé resulting output signal edge(50% points}. For synchronous circuits, which hâve aclock signal, thé delay is measured from thé active clockedge to thé resulting edge on thé output signal (again,50% points).

An increase in load capacitance lengthens thé transitiontime which increase thé propagation delay. Propagationdelay also increases with température. An increase in thésupply voltage reduces propagation delay.

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Minimum Clock Puise Width

Minimum clock puise widths, PW, and PW,, , asLmm Hmin

with propagation delays, can be specified in pairsalthough one or thé other is often omitted. PW, andLmmPW,. refer respectîvely to thé minimum widths of

Hminthé low and hîgh portions of thé clock puise. Thespécification is primarily a measure of how fastinformation can be shifted in a synchronous circuitwithout circuit malfunction. Puise widths may also bespecified for non-synchronous circuits such as non-clocked RS flip-flops and latches.

Maximum Clock Frequency

The maximum clock frequency is thé maximum rate atwhich information can toggle or transfer through asynchronous circuit without thé circuit malfunctioning.Above this frequency, thé circuit propagation delaysbecome comparable to thé reciprocal of thé clock rate sothat information may be improperly entered into thévarious clocked devices. The reciprocal of thé sum of thélow and high minimum puise widths equals thisfrequency: PRF max = 1/(PW, + PWU . ). Thus

Lmm Hminonly two of thé three parameters are usually specified.

Minimum Setup Time

Maximum Input Rise and Fall Times

Input rise and fall time spécifications describe thémaximum, or slowest, input signal transition times atwhich an integrated circuit will properly function. Thèseare most often given for thé clock input of edgetriggered devices, such as flip-flops, shift registers, andcounters. Above maximum limits, transitions become soslow that data in thé synchronous circuit may react withdata in thé previous stage rather than properly toggle tothé next state.

Minimum setup time is thé length of time whichinformation must be présent on thé data inputs ofsynchronous devices before thé clock (or strobej signaloccurs. If thé setup time is too short, data may beincorrectiy entered into thé device. The time is measuredbetween thé 50% points of thé data and clock inputsignal edges.

Minimum Hold Time

Minimum hold time is normally specified in conjunctionwith setup time. It is thé length of time which datainputs must remain steady after occurrence of thé clockedge. Again, it assures correct data entry into synchro-nous devices.

NOTE: This application note is concerned withpuise generaîor testing techniques. Discussion isthus focused mainly on dynamic parameters, orthose having to do with timing and frequencyconsidérations. Measurement of static voltages andcurrents is a separate problem and is not discussed.

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FUNCTIONAL ING

As mentioned prevîously, test requirements for CMOSdevices are of two différent types:

1. Functional Tests

2. Parametric Tests

Functional testing is described in thé paragraphs below.Parametric testing will be covered in thé followingsection.

During functional testing, proper digital performance ofthé device-under-test is checked under a given, fîxed setof operating conditions. Power supply voltage, inputsignal transition times, clock puise width, and set-uptimes, for example, are ail held constant during thé test.The device or circuit is checked to see if it does workunder thé given conditions as opposed to finding outhow it works and thé effect of varying thé conditions.

A puise generator, for example, which fulfils thé above

requirements is thé Hewlett-Packard model 8011A (seefigure 6). It also includes other capabilities valuable inCMOS functional testing and two of thèse are discussedbelow.

InterfaceKroper interface to thé test device requires a generatorwith a selectable, 50 H or high impédance, sourceimpédance. Minimum reflections are achieved by back

terminating with 50Î2 in thé generator when drivinghigh capacitance loads. When thé load capacitance is small,thé generator should be operated as a current source(high output impédance) and a 50H termination shouldbe used at thé load.

A typical example of functional testing is thé work of acircuit design engîneer to put together circuits compris-ing 30 - 50 IC's to perform a particular logic function.Mis concern is troubleshooting his design to removemistakes he may hâve unintentionally designed in. Mostoften his requirement is for a basic puise generator withvariable amplitude and répétition rate to use as a clocksource for his logic System. In addition a simple countedburst capability is also very useful to him. With it he cancheck blocks of logic by clocking to a spécifie point inthé logic séquence and checking to see if thé proper statehas been reached.

Other areas concerned with functional testing includeprinted circuit (PC) board testing and incoming inspec-tion testing of integrated circuits. Hère thé need is oftenfor multichannel word génération to supply patterns tothé multiple inputs of thé devices under test. Still,however, thé puise response requirements of théstimulus signal are simple when a functional test is to beperformed.

A listing of thé requirements for a puise generatorcapable of supplying signais for functional testing is asfollows.

1. Répétition rate to 10 or 20 MHz

2. Single Channel

3. Variable output amplitude to 16 volts

4. Fixed puise transition time < 10 nS

5. 50 Si Source impédance.

Puise Burst TestingFunctionally testing counters, shift registers, memoriesor circuits built from thèse devices often requires thécapability to supply a burst of an exact number of puisesto thé test circuit. Model 8011A includes this capabilityin its option 001. The number of puises desired, from 1to 9999, is set into thumbwheel switches and upontriggering is delivered to thé test circuit.

The burst can be started in one of two ways: by externalelectrical trigger or by pressing a pushbutton. At thé endof a burst, extra puises can be generated individually bypressing another pushbutton. Circuits can thus beclocked to a desired state at their operational clock rateand then analyzed under static conditions.

Figure 7 illustrâtes such an application. The circuit is afrequency divider and could represent a portion of somelarger, more complex circuit. The circuit is comprised of4 décade counter/decoders and should produce onehigh going puise at thé AND gâte output for each 6752input clock puises. The circuit is checked as follows.

A burst of exactly 6751 puises is supplied to thé clockUne of thé'circuit. The AND gâte output is then logicprobed and an additional clock puise delivered bypressing thé 8011A's SINGLEPULSE button. The ANDoutput should puise high briefly and return low as thé6752nd clock puise is delivered. Répétition rate or otherpuise parameters can be varied and thé test repeated.The puise burst length is independent of other puisegenerator settings and thus remains constant.

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PARAMETRIC TESTING

Parametric testing, in contrast to functional testing, isperformed to détermine how a device or circuit opérâtesunder given conditions and how it reacts if théconditions are changed. This requires, naturally, moredetailed control of thé test puise shape and, therefore, amore complex test setup. Typical environments forparametric testing are manufacturing tests or componentévaluations performed on integrated circuits.

The first step in expanding a functional test to aparametric test could be to investigate thé dependenceof thé device opération on ils clock input risetime. Inpractice when thé IC is part of a larger circuit, actualinput risetimes are limited by stray capacitance on signalnodes. Longer effective delays through thé device resuit,and System maximum operating speed is reduced {seeFigure 8). In testing to détermine thé magnitude of thisvariation, thé effect of stray capacitance is bestsimulated by varying thé rise and faillîmes of thégenerator driving thé clock (or other) input of thédevice.

Level Tracking

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Figure 8. Influence of Transition Time on Puise Period

An instrument particularly well suited to thé needs ofCMOS parametric testing is thé Hewlett-Packard model801 5A puise generator. It includes two variable rise andfalltime outputs in addition to a number of other CMOSorientée! capabilities and will be used as thé examplestimulus source in thé applications which follow.

CMOS integrated circuits are specified to work properlyover a power supply voltage range of 3 — 16 volts.Parameters, however, such as propagation delay andsetup times are directly dépendent on thé power supplyvoltage. Thus for a true représentation of deviceparametric behavior, parameters must be measured overa range of power supply voltages. Input signal ampli-tudes, which should equal thé supply voltage and mustnever exceed it*, must also be varied concurrently withthé power supply.

Level tracking capability (option 006 for model 8015A)simplifies this testing requirement and éliminâtes thédanger of destroying thé IC. Level tracking permitscontrolling thé puise generator output levels with anexternal control voltage, which is normally thé devicepower supply. Signal levels automatically track thépower supply voltage and device safety and proper inputlevels are ensured.

Figure 9 shows thé connections between puise generator,device-under-test, and power supply. The level trackinginputs are connected directly to thé puise generator'soutput amplifiers. The DUT {device-under-test) is pro-tected even if thé power supply is switched off.

Direct Output Amplifier AccessDirect access to thé puise generator's linear outputamplifiers (option 004) permits thé puise generator to beused as a level converter. TTL signais or low level wordgenerator outputs may be amplified to CMOS com-patible levels.

• As briefly descn'bed earlier, CMOS integrated circuits arerapidly destroyed if thé input signal level is ever greater thanthé power supply voltage. Device manufacturer go so far asto recommend disconnecting ail low impédance test eguip-ment from thé device under test before switching off thépower supply in order to avoid this danger.

Figure 9. Level Tracking with thé Device Power Supply

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Figure 10. Direct Output Amplifier Access

As shown in Figure 10, a major advantage of usïng directamplifier access is that two signais with a defined timerelattonship to each other are provided. One channel canbe used as a clock signal and thé other as datainformation.Thisconfiguration (figure 10) allowsextrem-ely convenient measurements of setup time, hold timeand propagation delay.

Delay between thé two channels is inserted using thénormal puise generator delay controls. Minimum setuptime of thé DUT can be measured by decreasing thédelay between thé clock puise active edge and data puiseleading edge until a point just before thé Q outputdisappears. The delay then présent equals thé minimum

setup time and can be determined from thé scopedisplay.

Propagation delay is measured between thé clock puiseactive edge and thé Q output leading edge. Minimumhold time is measured by decreasing thé width of théword generator puise (or increasing clock delay) until apoint just before thé Q output of thé device disappears.

The word generator provides thé advantage that théclock puise parameters, particularly its width, can beadjusted independently of thé data puise. Deviceminimum clock puise width sensitivity can thus besimply measured by decreasing thé clock width until théoutput disappears.

Two-Phase ClockingA requirement of some CMOS circuits (and many PMOSdevices) is multiple input clock signais. Figure 11, forexample, shows 2-phase non-overlapping clock signaisrequired by a CMOS shift register and other dynamicMOS devices.

Two-phase signais for IC driving or testing purposes areeasîly generated using model 8015A's capability forinterchannel delay. Puises with thé proper amplitude,répétition rate, puise width, and transition times are firstset up in each of thé generator's channels. SelectingB DELAY mode of opération, interchannel delay isinserted between thé two outputs using thé generator'sdelay controls. The proper phase relationship is easilyachieved.

Figure 11. Two-phase clock signais required by dynamicshift registers. For proper shifting opérationthé puises must be non-overlapping.

A further facilîty allows thé A and delayed B channelsignais to be added. Three level signais are thusgenerated, as shown in figure 12. Thèse signais are oftenuseful in other applications such as charge coupleddevice (CCD) testing or for sîmulating spécial codes. Thesignais may be generated in any of four formats byselectîng différent combinations of thé NORMAL/COM-PLEMENT switches. In addition thé A and B puise levelscan be independently defined by thé separate puiseamplitude controls.

Figure 12. Three-level Signais

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PARAMETRICTESTSE1

Ail of thé capabilities introduced above can be combinedinto a single test set. This configuration can perform testsof ail dynamic CMOS parameters over thé full range ofoperating voltages. The typical IC testing example shownbelow is intended to illustrate thé application of thé testset as well as summarize and conclude this applicationnote. The device chosen is a CMOS 64 bit static shiftregister.

The following parameters will be measured:

• Minimum Setup and Hold Times• Propagation Delay• Minimum Clock Width• Maximum Clock Rate• Effect of Power Supply Variations• Parameter Dependence on Clock Puise

Transition Time• Correct Shifting Opération

Word Generator: HP 8006A

DC Power Supply: 0-1 5 volts

Oscilloscope: 4 channel

Figure 13 shows thé complète parametric test set. Thepuise generator is thé master instrument. Its triggeroutput clocks thé word generator thereby synchronizingthé two instruments. The word generator output isamplified in one of thé pulser's channels to thé samelevels as thé second channel. Channel delay enablesspécifie time relationships between thé two channels,and level tracking keeps thé signal amplitude alwaysequal to thé power supply voltage.

Measurement of minimum setup and hold times,propagation delay, and minimum clock puise width hasbeen described earlier.

The test set is comprised of thé following instruments:

Puise Generator: HP Model 8015A with

- Counted Puise Burst (Option 002}- Direct Output Amplifier Access

(Option 004)- Upper Output Level Tracking

(Option 006)

To measure maximum clock rate ail parameters are firstset to minimum or worst case values. Puise répétitionrate is then increased until just before thé output puisedisappears.

Device parameters on IC data sheets are typically givenfor a particular power supply voltage and not specifiedat other voltages. Still, testing over a range of voltages isoften quite useful. If thé CMOS IC is, for example, to bepart of a battery-powered instrument, it enables thé

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Figure 13. Block Diagram of Complète Parametric Test Set

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design engineer to assess circuit performance at différentbattery voltages. This check can be carried out verysimply. The power supply voltage is adjusted up anddown and thé parametric tests repeated.

Varying thé puise generator rise and faillîmes allowsinvestigation of thé dependence of parametric perfor-mance on stray circuit capacitance. The designer thusgains an understanding of how his device will behave inthé less than idéal environment of a real circuit.

A final test is of thé dynamic length and opération ofthé shift register. It is performed with a puise burst. Thetest could be a simple functional test to find out if théregister is working properly. Alternatively it could formpart of a parametric test in which thé puise burst is

carried out with worst case parameters to check théregister at ils operating limits.

The word generator is set to produce a single 32 bitword (64, 16 or 8 bit words will also work). The worddata is set to a one in thé first bit and zeroes in ailremaining bits. The puise generator is set to deliver aburst of 64 puises, and thé burst is triggered eitherelectrically or manually. If thé shift register is workingproperly, thé logic low level at thé Q output shouldchange to a one at thé end of thé burst. If an additionalclock puise is then delivered, thé Q output should returnto thé low state.

Figure 14 shows thé timing relationship between clock,data, and register output puises. The first registeroutputs do not appear unttl 64 puises after thé start ofthé test.

Figure 15. Photograph of Complète Parametric Test Set

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