© PSU

Variation Aware Placement in FPGAs

Suresh Srinivasan and Vijaykrishnan Narayanan

Pennsylvania State University, University Park

© PSU Introduction Field Programmable Arrays(FPGA) are becoming popular due

to their short-design times and cost-effectiveness. Increasing popularity and demands compelling to move to

sub-100nm domain.

Interconnect Switch Matrix

Logic Slice

Logic Slice

Logic Slice

Logic Slice

Loca

l Fee

dbac

k

CLB Cin

Cout

CLB Multiplier

Clock I0

© PSU Problems in sub-100nm domain Unpredictability in the process parameters, “PROCESS

VARIATIONS” Variations in devices’ gate length, threshold voltages, oxide

thickness etc. Thereby variations in the power and performance of devices.

Drastic impacts of such variations demonstrated on FPGAs*: Leakage Power increase by 2X. 3X increase in the delay of the LUTs. Manufacturing yield affected cost for industry

Solutions for such problems in FPGAs NONE YET – THIS IS THE START!!!

*P. Wong, L. Cheng, Y. Lin and L. He, "FPGA Device and Architecture Evaluation Considering Process Variation," Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2005.

© PSU Observing the impact The impact on different components

Configuration Bits (SRAM cells) POWER – SRAM cells used are high Vt

– Leakage power: Not significant in total power since its really low.

– Dynamic power only once during configuration. Performance

– Not in the critical path, so not an issue LUT Multiplexer

Both power and performance are an issue Routing Fabric

Both power and performance are an issue

© PSU Impact on LUT MUX4x1Mux

4x1Mux

4x1Mux

4x1Mux

4x1Mux

SRAM

SRAM

SRAM

LUT MUX Design

Threshold voltage(NMOS) Vs Lkg Power of LUT mux

0.00E+00

5.00E-06

1.00E-05

1.50E-05

2.00E-05

2.50E-05

3.00E-05

3.50E-05

4.00E-05

Vt

Leak

age

Pow

er (w

)

2X leakage power increaseNominal operating threshold

Threshold voltage(NMOS) Vs Delay of a Slice

0.00E+00

1.00E-10

2.00E-10

3.00E-10

4.00E-10

5.00E-10

6.00E-10

7.00E-10

8.00E-10

Vt

Dela

y(se

c)

1.3X Variation in delay with 20% Vt variations

Nominal operating threshold

© PSU Impact on Applications

Leakage Power Increase

0.0010.0020.0030.0040.0050.00

Perc

enta

ge In

crea

se

Average increase by 20%

© PSU Solutions to the problem Detect power/delay numbers for

each SLICE. Pre configuration of sensors to

determine slice delay/power.

Caution while placement. Two placement strategies: Block Discard Policy (BDP):

Discard blocks with delay, power product > Threshold (Set based on utilization of device)

Iterative process as indicated Variation Aware Placement

(VAP): Incorporate variation costs in placement algorithm.

Generate Gaussian Distribution of SLICE

Thresholds

Obtain delay and leakage of the SLICEs

Set a leakage anddelay thresholdfor discarding

Generate constraint file

ISE tool flow

If PAR successful

Y NChoose the

Last Successfulplacement

BDP

© PSU Implementation Details BDP Implementation

Xilinx ISE ver. 6.0. Used PAR with User Constraint File (UCF), to constrain the

placement.

Variation Aware Algorithm (VAA) Needed change in algorithm Can’t use Xilinx tools Open source FPGA place & route tool used VPR (Versatile

Place and Route) Modified the cost function of the simulated annealing algorithm

used by the placer.

Used Xilinx reference designs for benchmarking BDP. Used MCNC benchmarks for benchmarking VAP.

© PSU BDP resultsPercentage leakage power savings after BDP

0.00

5.00

10.00

15.00

20.00

25.00

30.00

Perc

enta

ge le

akag

e be

nifit

s

Average 15% savings

* No impact on performance. All designs could meet the required timing

© PSU Results (VAP)

Percentage reduction in leakage power consumption

0.00

5.00

10.00

15.00

20.00

25.00

apex2 apex4 bigkey clma des diffeq dsip elliptic ex5p

Perc

enta

ge re

duct

ion

Delay analysis for benchmarks from VPR

0.00E+00

5.00E-08

1.00E-07

1.50E-07

2.00E-07

2.50E-07

Original PV-incorporated DelayOptimization

LeakageOptimization

Criti

cal P

ath

Dela

y(in

sec

)

apex2

apex4

bigkey

clma

des

diffeq

dsip

elliptic

ex5p

© PSU Conclusion Variation aware placement provides an effective scheme

preventing both power and performance related issues in FPGAs due to process variations.

Routing should also be made variation aware. Detailed impact analysis of such variations in routing fabric

needed.