project on dbms
DESCRIPTION
usefull for b.tech ITTRANSCRIPT
Experiment No-1
Aim: To verify all logic gates.
Software Used:Xilinix ISE Version:14.3
AND Gate: The AND gate is a basic digital logic gate that implements logical conjunction - it behaves according to the truth table (as shown below). A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results.
OR Gate: The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table (as shown below). A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results.
NOT Gate: In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown below
.
NAND Gate:In digital electronics, a NAND gate (Negated AND or NOT AND) is a logic gate which produces an output that is false only if all its inputs are true; thus its output is complement to that of the AND gate. A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results.
NOR Gate:The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator.
EOR Gate:The XOR gate (sometimes EOR gate, or EXOR gate and pronounced as Exclusive OR gate) is a digital logic gate that implements an exclusive or; that is, a true output (1/HIGH) results if one, and only one, of the inputs to the gate is true. If both inputs
are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false.
ENOR Gate:The XNOR gate (sometimes spelled "exnor" or "enor" and rarely written NXOR) is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. The two-input version implements logical equality, behaving according to the truth table to the right. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_gates_e is
Port ( a,b : in STD_LOGIC;
yand : out STD_LOGIC;
ynand : out STD_LOGIC;
yor : out STD_LOGIC;
ynor : out STD_LOGIC;
ynot : out STD_LOGIC;
yxor : out STD_LOGIC;
ynxor : out STD_LOGIC);
endjahaanvi_gates_e;
architecture Behavioral of jahaanvi_gates_e is
begin
yand<=a and b;
ynand<=a nand b;
yor<=a or b;
ynor<=a nor b;
ynot<=not a;
yxor<=a xor b;
ynxor<=a xnor b;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-2(a)
Aim: To verify half adder.
Software Used: Xilinix ISE Version:14.3
Description:The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is A+B. The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits.The output variables are the sum and carry.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_HA_e is
Port ( a,b : in STD_LOGIC;
sum,carry : out STD_LOGIC);
endjahaanvi_HA_e;
architecture Behavioral of jahaanvi_HA_e is
begin
carry<=a and b;
sum<=a xor b;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-2(b)
Aim: To verify full adder.
Software Used: Xilinix ISEVersion:14.3
Description:A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less significant stage.[2] The full adder is usually a component in a cascade of adders. A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with
and .
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_FA_e is
Port ( a,b,cin : in STD_LOGIC;
sum,carry : out STD_LOGIC);
endjahaanvi_FA_e;
architecture Behavioral of jahaanvi_FA_e is
begin
sum<=a xor b xorcin;
carry<=(a and b) or (b and cin) or (cin and a);
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-3(a)
Aim: To verify half subtractor.
Software Used: Xilinix ISEVersion:14.3
Description: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).An important point worth mentioning is that the half adder diagram aside implements (b-a) and not (a-b) as borrow is calculated from equation
VHDL Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_HS_e is Port ( a,b : in STD_LOGIC;diff,borrow : out STD_LOGIC);endjahaanvi_HS_e;
architecture Behavioral of jahaanvi_HS_e isbegindiff<=a xor b;borrow<= (not a) and b;end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-3(b)
Aim: To verify full subtractor.
Software Used: Xilinix ISEVersion:14.3
Description:The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, X (minuend) and Y(subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).So, Logic equations are:
VHDL Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_FS_e is Port ( a,b,c : in STD_LOGIC;diff,borrow : out STD_LOGIC);endjahaanvi_FS_e;
architecture Behavioral of jahaanvi_FS_e is
begindiff<=a xor b xor c;borrow<=(c and(not(a xor b))) or ((not a) and b);end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-4
Aim: To verify MUX.
Software Used: Xilinix ISE Version:14.3
Description:In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.[1] A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output.[2] Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.[1] A multiplexer is also called a data selector.
VHDL Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_mux_e is Port ( a,b,c,d : in STD_LOGIC;s : in STD_LOGIC_VECTOR (1 downto 0);z : out STD_LOGIC);endjahaanvi_mux_e;
architecture Behavioral of jahaanvi_mux_e isbeginProcess(a,b,c,d,s)begincase s is when "00" => z<=a;when "01" => z<=b;when "10" => z<=c;when others => z<=d;end case;end Process;end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-5
Aim: To verify DEMUX.
Software Used: Xilinix ISEVersion:14.3
Description:A logical circuit that takes a single input source and sends it to one of several outputs. In networking, it is used to describe a device that receives a transmission of several signals over a single line and can properly decode the single line signal into multiple signals. The equipment used to de-multiplex the signals into several sources which were multiplexed before is called the De-Multiplexer. This is a reverse of Multiplexing where the analog / digital signals are combined for transmission over a single line or media.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_demux_e is
Port ( a : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
y0,y1,y2,y3 : out STD_LOGIC);
endjahaanvi_demux_e;
architecture Behavioral of jahaanvi_demux_e is
begin
Process(a,s)
begin
case s is
when "00" => y0<=a;
when "01" => y1<=a;
when "10" => y2<=a;
when others => y3<=a;
end case;
end Process;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-6
Aim: To verify binary to gray code converter.
Software Used:Xilinix ISEVersion:14.3
Description:Binary to gray code conversion is a very simple process. There are
several steps to do this types of conversions. Steps given below elaborate on the idea on this type of conversion:
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.(2) Now the second bit of the code will be exclusive-or of the first and second bit of the given binary number, i.e if both the bits are same the result will be 0 and if they are different the result will be 1.(3)The third bit of gray code will be equal to the exclusive-or of the second and third bit of the given binary number. Thus the Binary to gray code conversion goes on.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jahaanvi_binary2gray_e is
Port ( A,B,C,D : in STD_LOGIC;
G0,G1,G2,G3 : out STD_LOGIC);
endjahaanvi_binary2gray_e;
architecture Behavioral of jahaanvi_binary2gray_e is
begin
G0<= B XOR A;
G1<= C XOR B;
G2<= D XOR C;
G3<= D;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-7
Aim: To verify gray to binary code converter.
Software Used: Xilinix ISE Version:14.3
Description:Gray code to binary conversion is again very simple and easy process.
Following steps can make your idea clear on this type of conversions.
(1) The M.S.B of the binary number will be equal to the M.S.B of the given gray code.(2) Now if the second gray bit is 0 the second binary bit will be same as the previous or the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it will be 1.(3) This step is continued for all the bits to do Gray code to binary conversion.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_gray2binary_e is
Port ( G0,G1,G2,G3 : in STD_LOGIC;
A,B,C,D : out STD_LOGIC);
endjahaanvi_gray2binary_e;
architecture Behavioral of jahaanvi_gray2binary_e is
begin
A<=(G3 XOR G2)XOR(G1 XOR G0);
B<=(G3 XOR G2)XOR G1;
C<=G3 XOR G2;
D<=G3;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-8
Aim: To verify half adder using structural modelling.
Software Used: Xilinix ISE Version:14.3
Description:The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is A+B. The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits.The output variables are the sum and carry.
VHDL Code:
libraryieee;
use ieee.std_logic_1164.all;
entityandGate is
port( A, B : in std_logic;
F : out std_logic);
endandGate;
architecturefunc of andGate is
begin
F <= A and B;
endfunc;
libraryieee;
use ieee.std_logic_1164.all;
entityxorGate is
port( A, B : in std_logic;
F : out std_logic);
endxorGate;
architecturefunc of xorGate is
begin
F <= A xor B;
endfunc;
libraryieee;
use ieee.std_logic_1164.all;
entityhalfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
endhalfAdder;
architecturehalfAdder of halfAdder is
componentandGate is
port( A, B : in std_logic;
F : out std_logic);
end component;
componentxorGate is
port( A, B : in std_logic;
F : out std_logic);
end component;
begin
G1 :xorGate port map(A, B, sum);
G2 :andGate port map(A, B, Cout);
endhalfAdder;
Experiment No-9
Aim: To verify full adder using structural modelling.
Software Used: Xilinix ISE Version:14.3
Description:A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less significant stage.[2] The full adder is usually a component in a cascade of adders. A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with
and .
VHDL Code:
libraryieee;
use ieee.std_logic_1164.all;
entityandGate is
port( A, B : in std_logic;
F : out std_logic);
endandGate;
architecturefunc of andGate is
begin
F <= A and B;
endfunc;
libraryieee;
use ieee.std_logic_1164.all;
entityxorGate is
port( A, B : in std_logic;
F : out std_logic);
endxorGate;
architecturefunc of xorGate is
begin
F <= A xor B;
endfunc;
libraryieee;
use ieee.std_logic_1164.all;
entityorGate is
port( A, B : in std_logic;
F : out std_logic);
endorGate;
architecturefunc of orGate is
begin
F <= A or B;
endfunc;
entityfullAdder is
port( A, B, Cin : in std_logic;
sum, Cout : out std_logic);
endfullAdder;
architecturefullAdder of fullAdder is
componenthalfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end component;
componentorGate is
port( A, B : in std_logic;
F : out std_logic);
end component;
signalhalfTohalf, halfToOr1, halfToOr2: std_logic;
begin
G1: halfAdder port map(A, B, halfTohalf, halfToOr1);
G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2);
G3: orGate port map(halfToOr1, halfToOr2, Cout);
endfullAdder;
Experiment No-10
Aim: To verify S-R flip flop.
Software Used:Xilinix ISEVersion:14.3
Description:When using static gates as building blocks, the most fundamental latch is
the simpleSR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
SR latch operation[12]
Characteristic table Excitation table
S R Qnext Action Q Qnext S R
0 0 Q hold state 0 0 0 X
0 1 0 reset 0 1 1 0
1 0 1 set 1 0 0 1
1 1 X not allowed 1 1 X 0
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_srff_e is
Port ( s,r,clk,reset : in STD_LOGIC;
q,qb : out STD_LOGIC);
endjahaanvi_srff_e;
architecture Behavioral of jahaanvi_srff_e is
begin
srff : process (s,r,clk,reset) is
begin
if (reset='1') then
q <= '0';
qb<= '1';
elsif (rising_edge (clk)) then
if (s/=r) then
q <= s;
qb<= r;
elsif (s='1' and r='1') then
q <= 'Z';
qb<= 'Z';
end if;
end if;
end process srff;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-11
Aim: To verify J-K flip flop.
Software Used: Xilinix ISE Version:14.3
Description:The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset)
by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
The characteristic equation of the JK flip-flop is:
and the corresponding truth table is:
JK flip-flop operation[24]
Characteristic table Excitation table
J K Comment Qnext Q Qnext Comment J K
0 0 hold state Q 0 0 No Change 0 X
0 1 Reset 0 0 1 Set 1 X
1 0 Set 1 1 0 Reset X 1
1 1 Toggle Q 1 1 No Change X 0
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_jkff_e is
Port ( j,k,clk,reset : in STD_LOGIC;
q,qb : out STD_LOGIC);
endjahaanvi_jkff_e;
architecture Behavioral of jahaanvi_jkff_e is
begin
jkff : process (j,k,clk,reset) is
variable m : std_logic := '0';
begin
if (reset='1') then
m := '0';
elsif (rising_edge (clk)) then
if (j/=k) then
m := j;
elsif (j='1' and k='1') then
m := not m;
end if;
end if;
q <= m;
qb<= not m;
end process jkff;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-12
Aim: To verify D flip flop.
Software Used: Xilinix ISE Version:14.3
Description:This latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SR latch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to these two input combinations for the next SR latch by inverting the data input signal. The low state of the enable signal produces the inactive "11" combination. Thus a gated D-latch may be considered as a one-input synchronous SR latch. This configuration prevents application of the restricted input combination. It is also known as transparent latch, data latch, or simplygated latch. It has a data input and an enable signal (sometimes namedclock, or control). The word transparent comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_dff_e is
Port ( enable,din,reset : in STD_LOGIC;
dout : out STD_LOGIC);
endjahaanvi_dff_e;
architecture Behavioral of jahaanvi_dff_e is
begin
latch : process (enable,din,reset) is
begin
if (reset='1') then
dout<= '0';
elsif (enable='1') then
dout<= din;
end if;
end process latch;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
Experiment No-13
Aim: To verify T flip flop.
Software Used: Xilinix ISE Version:14.3
Description:If the T input is high, the T flip-flop changes state ("toggles") whenever the
clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristicequation:
(expanding the XOR operator)
and can be described in a truth table:
T flip-flop operation[24]
Characteristic table Excitation table
Comment Comment
0 0 0hold state
(no clk)0 0 0 No change
0 1 1hold state
(no clk)1 1 0 No change
1 0 1 toggle 0 1 1 Complement
1 1 0 toggle 1 0 1 Complement
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityjahaanvi_tff_e is
Port ( t,clk,reset : in STD_LOGIC;
dout : out STD_LOGIC);
endjahaanvi_tff_e;
architecture Behavioral of jahaanvi_tff_e is
begin
tff : process (t,clk,reset) is
variable m : std_logic := '0';
begin
if (reset='1') then
m := '0';
elsif (rising_edge (clk)) then
if (t='1') then
m := not m;
end if;
end if;
dout<= m;
end process tff;
end Behavioral;
VHDL Circuit:
VHDL Simulation:
