EE 599: POWER ELECTRONICS

PROJECT #7

Second Stage of a Photovoltaic Inverter System

Due: December 14th, 2015

By: Vladislav Khalus

Group Partner: Elvys Pontes

I. Objective and BackgroundThe purpose of this lab is to design a second stage of the photovoltaic inverter system, as shown in Fig. 1. The constraints for the inverter must be met, meaning that the inverter should be capable to operate all the way to output power of grid, Pg=¿ 2000W at output voltage of grid, V g = 120V and where the grid frequency, f g = 60Hz. Looking at Fig. 2, it shows a further step into the photovoltaic inverter system. In a short summary, the second stage of the inverter system takes in a DC value and uses an inverter to convert it into an AC value. The overall goal is to reduce the DC link ripple by getting the right DC capacitor and using filters, to reduce the Total Harmonic Distortion by using the right AC LR filter, also to make sure the power factor, pf is unity (meaning grid voltage in phase with grid current), and also designing the inverter so that commercial parts could be used to build the physical circuit.

Figure 1: Two stages of a photovoltaic inverter system

Figure 2: A detailed circuit of the second stage of a photovoltaic inverter system

II. Mathematical Modeling To start off this Sect., a left to right approach of Fig. 2 circuit needs to be done to understand how the system is modeled. To begin with the circuit, it’s required to be known where the boost converter or input current, i¿ is going. By using KCL, the currents can be defined as i¿=ic+idc, (1) where ic is the capacitor current, and idc is the current going into the inverter. With this, Eqn.

(1) can be more simplified P¿

V dc=C

dV dc

dt+idc , (2) where P¿ is

the constant power source coming from the boost converter (which is originally from the PV module), that has a constant value of 2000W. As for the V dc, it’s the voltage

of the electrolytic capacitor. Also noting that the differential equation for ic, it can be

modeled as CdV dc

dt.

Now looking at Eqns. (3) and (4), it shows how the voltage of the capacitor is solved.

dV dc

dt=

P¿

V dc−idc

C (3)

V dc=∫P¿

V dc−idc

C (4)

It makes sense that Eqn. (4) cannot be solved unless the capacitance, C is known, the best way to find C is using change in Energy, ∆ E. The time limits for the Energy is

between −1480 sec and

1480 sec, the reason is this because the sinusoid ends its period

at 1

120 , and so the power, P¿ makes an intersection with the wave four times,

therefore its 1

480 . Looking at Eqn. (5), the power and the cosine are integrated to get

the change in Energy ∆ E= ∫−1 /480

1/480

(P¿cos (2π∗120t ) )dt. (5)

The change can be modeled as ∆ E=Emax−Emin, (6) and

energy can be more simplified to be ∆ E=12CV max

2 −12CV min

2 , (7)

where C, is the capacitance, V max is the V dcref = 400V multiplied by 1.05, which is the max of the 5% chosen voltage ripple. As for the V min, its V dcref multiplied by .95, which is the minimum of the 5% ripple. With this known, Eqn. (7) can be rearranged and solved for C. One thing that is not mentioned is that V dcref value was calculated to be above 120V, the reason is that the voltage needs to be pushed onto the grid, that’s why a value of 250V.

Once the currents in Fig. 2 are described, it was time to go into the inverter. Looking at Fig. 2, the inverter has four switches that are dependent on q, a 0 or 1 switch and iac, or the AC current coming out of the inverter. Looking at Fig. 3, this is a more detailed schematic of the inverter system. Describing the MOSFETs in the circuit, each MOSFET has a Rds, or drain to source resistance of 140mΩ, and a V d of 1.4V. Going further into the inverter circuit, as said before that inverter is dependent on iac and q, therefore, four cases can be modeled to get the functionality of the inverter.

Case 1: if q and iac≥0idc=iac (8) V ac=V dc−2 Rds iac

Case 2: if q and iac<0idc=iac (9) V ac=V dc−2V d

Case 3: if q and iac≤0idc=−iac (10) V ac=−V dc−2 Rds iac

Case 4: if q and iac>0idc=−iac (11)V ac=−V dc−2V d

Looking at just the AC part of Fig. 3, Fig. 4 was made and V ac was substituted as ~V inv

, and V g was substituted as ~V gnom. Therefore to get the exact value to be used for ~V inv, a KVL circuit analysis has to be done for Fig. 4. First the impedance, Z was set at Z=RL+ jωL (12) and by KVL, ~V inv=

~V gnom+Z iac , (13). Therefore, plugging in Eqn. (12) into (13), and knowing that

iac = Pref

V gnom, (14) the inverter voltage is

~V inv=V gnom+(RL+ jωL)Pref

V gnom. (15) The ~V inv can be modeled as a phasor

~V inv=|~V inv|∠~V inv, (16) Now finding the amplitude and the phasor of ~V inv

~V inv=√(V gnom+RLPref

V gnom)

2

+ω2 L2 Pref2

V gnom2 ∠atan2((ωL Pref

V gnom)V gnom+RL

Pref

V gnom ) (17)

With this the control value m ( t ) can be calculated

m ( t )=√2|~V inv|V dcref

cos(θg+¿∠~V inv)¿, (18) where θg is the

θg=ωt+θ (0), (19) and ω = 2πf , and also θ(0) = 0.

Figure 3: Detailed Inverter System

Figure 4: AC part

With m ( t ) calculated, it was time to get the exact equation of inverter current, iac. This step is similar to Eqn. (13) but it more specifically deals with the iac rather than ~V inv. Therefore using KVL on Fig. 4 V ac=R iac+V L+V g , (20)

and converting V L to diff. eqn. V ac=R iac+Ldiacdt

+V g, (21) and

finally solving diacdt

=V ac−R iac−V g

L, (22)

iac=∫V ac−R iac−V g

L. (23)

Once iac is calculated, the THD or the Total Harmonic Distortion can be can be calculated from the Fourier Series coefficients, a1 and b1,

a1=2T∫

0

T

iac ( t ) cos (ω¿t)dt ¿, (24)

b1=2T ∫

0

T

iac ( t )sin (ω¿t)dt ¿. (25)

With these coefficients from Eqns. (24) and (25), the fundamental RMS current can

be calculated iacRMS (1)=√ a12+b1

2

2, (26) and

also the RMS current iacRMS=√ 1T∫0

T

iac2 (t )dt . (27) With this

information that is given, the THD of iac can be calculated to be

THD iac=√ iacRMS2 −iacRMS(1)

2

iacRMS (1)2

. (28)

The only last equation that is important in this project is getting the power factor,

which is pf=Pref

V rms∗I rms. (29)

This can be accomplished by using the real power, Pref over the complex power, S or V rms∗I rms where I rms is conjugated. In this case, V rms is V g and I rms is iac.

III. Model Implementation

Going into this Sect. the second stage of inverter system in Fig. 2 will be explained in parts. Looking at Figs. 5a and 5b, it shows the Simulink implementation for the Eqn. (4) for V dc. The capacitor from Fig. 5b was calculated from rearranging Eqn. (7), therefore it came out to be .33157mF.

Figure 5a: Higher level of Vdc

Figure 5b: Complete Vdc block

Once V dc is figured out, it’s time to go into Pref or the referenced power. Looking at Fig. 6a, two filters were used to cut the ripple from the V dc. Also scopes were used to display the V dc, result for each filter.

Figure 6a: Pref with 2nd order filters

Looking at Figs. 6b and 6c, it shows how the Filter blocks were designed. One thing

to note that T= 602π 120 (30).

Figure 6b: Filter block

Figure 6c: Complete Filter block

Now going into the PI controller block in Figs. 6d and 6e, the k p value was estimated to be 1.5 to adjust the Pref to satisfy the requirements. As for the k i value it was

calculated to be k i=k p

T (31).

Figure 6d: PI Cotroller Block

Figure 6e: Complete PI Controller Block

Now with Pref calculated, it was time to go into the control value of m(t). Using Eqn. (18), it can be can be converted into Simulink blocks, as shown in Figs. 7a and 7b.

As for the repeating sequence block in Fig. 7b, the time values depend on frequency, and the output values depend on zero to 2π.

Figure 7a: m(t) block

Figure 7b: Complete m(t) block

Once the m(t) was figured out, the next step is to get q. This is done by using a Relational operator block on m(t) and a triangle wave (Repeating Sequence block) that has the amplitude values of [-1,1,-1]. As for the triangle wave frequency, it was set at 20KHz. The block is shown in Fig. 8.

Figure 8: Blocks for q

After q was done in Simulink, the next step was to go into the Inverter part, as shown in Fig. 9a and 9b.

Figure 9a: Inverter block

Going into Fig. 9b, it was extracted pretty much from the four cases listed in the Mathematical Model Sect..

Figure 9b: Complete Inverter Block

With the V ac calculated from the blocks in Fig. 9b, it was time to get Fig. 4 or the AC part of the Simulink, as shown in Fig. 10.

Figure 10: AC part

The value for inductor, L was estimated from iac attenuation to be 6.2µH, as for the RL, it was proportional to the L, therefore it came to be .31Ω.

The last Simulink block involved the THD and the pf, looking at Figs. 11a and 11b, it shows the blocks for these values. Because Simulink had a PHD block, it was more efficient to use it. As for the pf calculation, a RMS block was used to calculate the V rmsand I rms.

Figure 11a: THD and pf block

Figure 11b: Complete THD and pf block

Finally, combining all the Simulink blocks together, Fig. 12 can be represented.

Figure 12: Complete second stage inverter circuit

IV. Simulation Studies

Once the Simulink blocks were done, scopes were used to get the simulation outputs.

Figure 13: Voltage of the Capacitor

Figure 14: Vdc after the First Filter

Figure 15: Vdc after the second filter

Figure 16: Power Reference at initial value of Pin

Figure 17: The Control Value of m(t)

Figure 18: The Switching of q

Figure 19: The AC voltage

Figure 20: The current going into the inverter

Figure 21: The AC current from the inverter

Figure 22: The Grid Voltage

Figure 23: Used for pf

V. Analysis In this Section, Figs. 13 to 23 will be analyzed. Starting with Fig. 13, the simulation for V dc was around 350V to 410V, the reason is that V dc ref was chosen to be 400V, and also with V dcref and 5% ripple, the capacitance was chosen, in return V dc looks like that when the current goes through the calculated capacitor. Looking at Fig. 14, this is when the first order filter goes through the V dc, as it can be seen, there is still some ripple going on. Now looking into Fig. 15, another filter (second-order filter) is added to the V dc signal, and now the graph looks smoother, with minimal to zero amount of ripple. Looking at Fig. 16 for Pℜ f , it starts at an initial value of P¿ and then decreases to 1840W at half a second, the reason is that inverter needs power to change DC to AC. Now going into m(t), it was required to be between -1 and 1, the m(t) shown in Fig. 17 is half those values, the reason is that V dcref was a big voltage and also the impact of the cosine signal being multiplied. As for Fig. 18, it shows the correct behavior of the switch, q, which is from 0 to 1, at a switching frequency of 20kHz. Looking at Fig. 19, the AC voltage or V ac can be shown in the range of ±400V, this is due to the reason that V dcref = 400V. For the current going into the inverter, idc in Fig. 20, it’s in the range of ±25A, this is because the capacitor is regulating what current goes into the inverter, and with the chosen capacitor value and it’s voltage, V dc, the current idc is limited to ±25A. As for Fig. 21, the iac or the AC current coming from the inverter should be very similar to the idc. Well comparing Fig. 20 and Fig. 21, their peaks are around 25A and

-25A. Ideally, the current coming into the inverter needs to equal to the current coming out of the inverter, but do to the MOSFET losses of Rds, the iac is little lower than idc. Now going into Fig. 22, this pretty much shows the grid voltage RMS, where the peak is √2V gnom, and also the voltage have a standard frequency of 60Hz. Finally, for Fig. 23, it pretty much compares the iac and V gnom to check if it’s in unity power factor. Sadly it could not reach a pf of 1 because the circuit is not a closed loop system. Using the Simulink block, the pf was measured to be 0.97, so really close the voltage and current being in phase. Finally, talking about the THD, it was calculated by using a Simulink block already provided, and the value read 3.986%, which is good value when dealing with power electronics that have a THD limit of 5%.