Progress Report2013/11/07

OutlineFurther studies about

heterogeneous multiprocessing other than ARM

Cache miss issueDiscussion on task scheduling

Manufacturers Other than ARMQualcomm

◦aSMP(Asynchronous Symmetrical Multi-Processing)

◦Krait: Per-core DCVS (Dynamic Clock and

Voltage Scaling). Core that is not being used can be

completely collapsed independently. Reduce the need for hypervisors or more

complex software management of disparate cores.

Manufacturers Other than ARMNvidia

◦vSMP(Variable Symmetric Multiprocessing)

◦Tegra 3 4 high performance Cortex A9 main

processor + 1 energy-efficient Cortex A9 Companion processor.

Cannot active companion processor and main processor simultaneously.

Main processors have to use the same frequency.

HSA Foundation

Cache Miss Issue“For each switching between

big(A15) and A7(LITTLE), the L2 cache is cleaned, thus cause memory access overhead.”

Cache Miss Issue

Unless a chip(All A15 or All A7) is shutdown, clean L2 cache for each switching between A15 and A7 is weird.

A15L1

A15L1

A15L1

A15L1

A7L1

A7L1

A7L1

A7L1

L2

L2

Task SchedulingTake loading of each task into

consideration.For a given task, assume it

behavior:◦Computation Ops: n time units.◦Memory Ops: 1 time unit.

Different core frequencies cause different loadings.◦F = 1, loading = n/(n+1)◦F= 2, loading = n/(n+2)◦F= 4, loading = n/(n+4)

Single CoreFor a given set of tasks and their

behaviors, find the minimum frequency such the loading of the core is 100%.◦Lower frequency: loading = 100%,

but the performance decrease.◦Higher frequency: loading < 100%,

consume more (dynamic) power.

Scheduling on HMPAccording to the core capability,

assign processes in the runqueue to core.

Each core apply DVFS/DCVS individually.

However, this does not apply for big.LITTLE. ◦Each (pair of) core is homogeneous.

Big.LITTLE core SchedulingAssume that we have n pairs of

big.LITTLE cores.◦Initially all pairs use LITTLE core.

Assume we know the following information of a task Tk. ◦Task deadline.◦Estimated execution time on big

core.◦Estimated execution time on LITTLE

core.

Heuristic Mentioned Last TimeFirst, we define “urgency” U to

indicate the priority of a task.For Task Tk

◦0＜ Uk ≦1, then task Tk can be finished before deadline on LITTLE core

◦Uk > 1, then task Tk can’t be finished before deadline on LITTLE core.

Deadline toTime

core LITTLEon Remaining TimekU

Core SwitchingSwitch one LITTLE core to big

core if there exists a task Tk with urgency Uk > 1.

Find all the Tasks {Tj ,with Uj > 0.8}, assign these tasks to big cores.

Switch big cores to LITTLE cores if there is no task with urgency

greater than 0.8.

Discussion